From patchwork Thu Sep 21 04:26:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113183 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564410qgf; Wed, 20 Sep 2017 21:27:22 -0700 (PDT) X-Received: by 10.159.242.196 with SMTP id x4mr4193679plw.286.1505968041967; Wed, 20 Sep 2017 21:27:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968041; cv=none; d=google.com; s=arc-20160816; b=XYb82uhDjJGyRyyYtJALKdgkpQTaklHxzcK2h0R9RG9nSSDqyNCgXaH9tGbz6rlRgy EhMzc+h+qdkAiYwhuBn2XBsIdwqIJ338OLPknuLzy0SY37hc93bhM0B3zh1MBbm5GNKA rDW4xlWDEEqawYP8Fs1us3JSWw7jsFI99c+Y6EErh3UFc6ALUjtJ2VnYf0LOVL9tr1z6 zXl+OB5NJtowSn9Qk+L3V5q8csELAOLpzxMXzDdE87z1WdaoIPWxf6GRBVuoiF31ugZy KRfNhkfiCix/PX5lQ7e6pZWP6lJ2nK3ztfanXTaCilNRfHf90Jk0m672SxoXVBAm3iyK bspQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=QY2rtnBZrsT93Rm3p1p9CQpLsk5OAbSAXOiNpaxC96g=; b=UuPmlR55X7LumSYeKtE+wvpNKqHIBI80//cQ3xLDs+9cGLaeL8A/cVbmMlxWEzM1GB bm5w70xA0KQzeH4TWiTArYi8wPIs7nEP7YJ+rnavY/YXYMCU3GFaI9ZvNvSVGAxkKDtZ u26CZlNvTUP21stcZlAdq5Z/PbnKsQjsceTLno/LIuPSAV/XV0wIFLcEKhdnZfQdZ8X2 OMxC+NkDvPgduI+JqwiZTRcKke1YXe4cyw03gTv4iiDeQ3gh4LykT424np/O9NUgNEhO RJIWLCWXXnTK6+1AamP4S3hKXup40IPmaglf6shrpcPnS8W7x6zL13ujO/NoaMKUGWks 44hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=D1tRPGyH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r15si402941pfd.416.2017.09.20.21.27.21; Wed, 20 Sep 2017 21:27:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=D1tRPGyH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751617AbdIUE1M (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:12 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:36781 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdIUE1J (ORCPT ); Thu, 21 Sep 2017 00:27:09 -0400 Received: by mail-pg0-f67.google.com with SMTP id d8so2788478pgt.3; Wed, 20 Sep 2017 21:27:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=QY2rtnBZrsT93Rm3p1p9CQpLsk5OAbSAXOiNpaxC96g=; b=D1tRPGyH+a2Z+6mqmuuwPBx0Mpsax4SG5Wwo1y6qyvzxmoy5R7P4WveL5VOcq6fHFb C0mK5hNEA+zXdLkYHMgkiyfN7V/cLFNPDfWuB+JDAwXdHMprUpAqqUsXjFXyumPs+PyM BmPDVa2oczqroDZiJ168WZESu9nV78UtX2D6ZVSvH268AyYX762p7sHgIgbxnqhoHUHg IKArrDivImtALHDzNRKTC8xb1H+kbdc7UroOSQd5+sYLWA+dxtNrjNu+bztj5OgzVVJT 6DBmDl3afqH8wAB+sAUis9Ga3PvYtIFvRd4pY4AkeGtMqUoiwl+V2iIl7xcprwvY0BZF T8ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=QY2rtnBZrsT93Rm3p1p9CQpLsk5OAbSAXOiNpaxC96g=; b=bZBh2jlrmH3huJ2Lie483Y274HFc9VqfAanTTYWMC8mz1JQKEtARSlV1qsGy869XNO MI7VA1lU3eFislHdtwpEdp71SSaxQtTC5dmtgTIDVR/g9pGaQHWqmJyYFb3kVKxRTn/z Ec4glWa61YR+zgwfBeXAGdDkGw+9PLs4zbe/em0uahTfeA07yXduU6dpaPktm54TSVUc lw8M1CB6a1CKZVXOi2hmmRHVnK/26+rcDd1FMm+jOAovQ8JZwYgU773JsP3I/so4OzTS PoyiFAqybIRE72vGwhBWplq80/+EAKzp+Xw8iJ+FoANCZC0QTtUmFRYLXaz/0o4sJeHB EiVA== X-Gm-Message-State: AHPjjUhS331qcVxiTJ+AaAeN8t+s5Ic8T0Xnyi0lWEi/tgN/E09yMeDd ZPiYcHZM5pH/PyzUUOLdwMw= X-Google-Smtp-Source: AOwi7QBgIYJ4VKv1fRwgdfBsseVqHFG89JPiiA0nzFBNPqnhRlWkfBOxXi4YU+ILgutOoQ5SYmibOQ== X-Received: by 10.98.223.210 with SMTP id d79mr4281916pfl.67.1505968028475; Wed, 20 Sep 2017 21:27:08 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id l30sm620040pgc.78.2017.09.20.21.27.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:07 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:56:59 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 1/5] clk: Add clock driver for ASPEED BMC SoCs Date: Thu, 21 Sep 2017 13:56:37 +0930 Message-Id: <20170921042641.7326-2-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Signed-off-by: Joel Stanley --- drivers/clk/Kconfig | 12 +++ drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 162 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 43 ++++++++ 4 files changed, 218 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1c4e1aa6767e..9abe063ef8d2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI This driver supports the SoC clocks on the Cortina Systems Gemini platform, also known as SL3516 or CS3516. +config COMMON_CLK_ASPEED + bool "Clock driver for Aspeed BMC SoCs" + depends on ARCH_ASPEED || COMPILE_TEST + default ARCH_ASPEED + select MFD_SYSCON + select RESET_CONTROLLER + ---help--- + This driver supports the SoC clocks on the Aspeed BMC platforms. + + The G4 and G5 series, including the ast2400 and ast2500, are supported + by this driver. + config COMMON_CLK_S2MPS11 tristate "Clock driver for S2MPS1X/S5M8767 MFD" depends on MFD_SEC_CORE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c99f363826f0..575c68919d9b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o +obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c new file mode 100644 index 000000000000..824c54767009 --- /dev/null +++ b/drivers/clk/clk-aspeed.c @@ -0,0 +1,162 @@ +/* + * Copyright 2017 IBM Corporation + * + * Joel Stanley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#define pr_fmt(fmt) "clk-aspeed: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +#define ASPEED_RESET_CTRL 0x04 +#define ASPEED_CLK_SELECTION 0x08 +#define ASPEED_CLK_STOP_CTRL 0x0c +#define ASPEED_MPLL_PARAM 0x20 +#define ASPEED_HPLL_PARAM 0x24 +#define ASPEED_MISC_CTRL 0x2c +#define ASPEED_STRAP 0x70 + +/* Keeps track of all clocks */ +static struct clk_hw_onecell_data *aspeed_clk_data; + +static void __iomem *scu_base; + +/** + * struct aspeed_gate_data - Aspeed gated clocks + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @name: the clock name + * @parent_name: the name of the parent clock + * @flags: standard clock framework flags + */ +struct aspeed_gate_data { + u8 clock_idx; + s8 reset_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +/** + * struct aspeed_clk_gate - Aspeed specific clk_gate structure + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling gate + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @flags: hardware-specific flags + * @lock: register lock + * + * Some of the clocks in the Aspeed SoC must be put in reset before enabling. + * This modified version of clk_gate allows an optional reset bit to be + * specified. + */ +struct aspeed_clk_gate { + struct clk_hw hw; + struct regmap *map; + u8 clock_idx; + s8 reset_idx; + u8 flags; + spinlock_t *lock; +}; + +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) + +/* TODO: ask Aspeed about the actual parent data */ +static const struct aspeed_gate_data aspeed_gates[] __initconst = { +/* clk rst name parent flags */ + { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ + { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ + { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ + { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ + { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ + { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ + { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, + { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ + { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ + { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ + { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ + /* 11: reserved */ + /* 12: reserved */ + { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ + { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ + { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ + { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ + { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ + /* 18: reserved */ + { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ + { 20, 11, "mac1clk-gate", "clkin", 0 }, /* MAC1 */ + { 21, 12, "mac2clk-gate", "clkin", 0 }, /* MAC2 */ + /* 22: reserved */ + /* 23: reserved */ + { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ + { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ + { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ + { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ + { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ + /* 29: reserved */ + /* 30: reserved */ + /* 31: reserved */ +}; + +static void __init aspeed_cc_init(struct device_node *np) +{ + struct regmap *map; + u32 val; + int ret; + int i; + + scu_base = of_iomap(np, 0); + if (IS_ERR(scu_base)) + return; + + aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) + + sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS, + GFP_KERNEL); + if (!aspeed_clk_data) + return; + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (i = 0; i < ASPEED_NUM_CLKS; i++) + aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + map = syscon_node_to_regmap(np); + if (IS_ERR(map)) { + pr_err("no syscon regmap\n"); + return; + } + /* + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + ret = regmap_read(map, ASPEED_STRAP, &val); + if (ret) { + pr_err("failed to read strapping register\n"); + return; + } + + aspeed_clk_data->num = ASPEED_NUM_CLKS; + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); +}; +CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); +CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..afe06b77562d --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,43 @@ +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_NUM_CLKS 34 + +#define ASPEED_CLK_HPLL 0 +#define ASPEED_CLK_AHB 1 +#define ASPEED_CLK_APB 2 +#define ASPEED_CLK_UART 3 +#define ASPEED_CLK_SDIO 4 +#define ASPEED_CLK_ECLK 5 +#define ASPEED_CLK_ECLK_MUX 6 +#define ASPEED_CLK_LHCLK 7 +#define ASPEED_CLK_MAC 8 +#define ASPEED_CLK_BCLK 9 +#define ASPEED_CLK_MPLL 10 +#define ASPEED_CLK_GATES 11 +#define ASPEED_CLK_GATE_ECLK (0 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_GCLK (1 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_MCLK (2 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_VCLK (3 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_BCLK (4 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_DCLK (5 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_REFCLK (6 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_USBPORT2CLK (7 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_LCLK (8 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_USBUHCICLK (9 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_D1CLK (10 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_YCLK (11 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_USBPORT1CLK (12 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_UART1CLK (13 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_UART2CLK (14 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_UART5CLK (15 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_ESPICLK (16 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_MAC1CLK (17 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_MAC2CLK (18 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_RSACLK (19 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_UART3CLK (20 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_UART4CLK (21 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_SDCLKCLK (22 + ASPEED_CLK_GATES) +#define ASPEED_CLK_GATE_LHCCLK (23 + ASPEED_CLK_GATES) + +#endif From patchwork Thu Sep 21 04:26:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113184 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564498qgf; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) X-Received: by 10.98.68.82 with SMTP id r79mr4444051pfa.184.1505968048068; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968048; cv=none; d=google.com; s=arc-20160816; b=i9kUmRycAtWZrkw55FjSVP+vdNL8xVceAfsJpb4MSQdfM6PCLCkiGHJQ+7f6A/ObiN UdLqHSdTT0/p5gTcRoO5qL6o+nCpztCzancnknMU3FZT41ZMiiyzeVDuNEHPn2uWr7J8 0m/sBJGwI2c5QMSt7iiyEa7UP6sR1zmC6rDvt/7wkAJFVlieQ1fno+aP6AstPdtYz8lk L4/H6FBop0WGMSXtsBEukvYJjl8wjIkdQCzTelE8B3FAaGZXAg20A27PRUAkjJveAxKf d8dDUiYD4RygsCMhvoVj3EEQq4nn9Yjeo7cATrPSTrYj/xw1qHu6DLIZms12B2SfeTaj 70OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=nOAS8NFjz6elAP4ZadWC6rLmJUpie66qeffz6fO9kvVVMNKBa3UV3TxUFlFx5GKSh8 jUeAzFQgP92/nMA0DWCiNLSESD4sdKQrkiGR9QZr4OK25sK564Va1PHnR8QNGdjJ16VE BAq/mbcbEWvZSkqbz4UDUQIG6QW+ze4gFdTzLZ2wqx0KGMfPe4PvcgiFLbhGjrElJ9mb E/UsC37/dCIrE2K5NAmGfkvgn7EpqG04B6/p1uRETyv0UNl6W4n2h60oP8QbLiqWk85h GOatha623/e58b8YDImVo8VnyANGs1Pkdpaldeg6CwrUYMWpPBOfcQULm1OpmHJahDo1 Db6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Qa/1bEae; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 5si410614plx.272.2017.09.20.21.27.27; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Qa/1bEae; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751681AbdIUE1V (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:21 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35762 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751635AbdIUE1S (ORCPT ); Thu, 21 Sep 2017 00:27:18 -0400 Received: by mail-pf0-f194.google.com with SMTP id i23so2021517pfi.2; Wed, 20 Sep 2017 21:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=Qa/1bEaetZlSC3q63lSdmLuwFvqpaRba7mT8Tj0fm6gwrumM9FkmSSGUVjJOWqPc9X oSgM/UOjqbTgR9YKx9OoD4VpqTkEPfpzMqXG4sp2M71TgnWfaFulouDpixwVkaiEXc5u ikjaW4YobByQQfdLGH95zhrh1SJuYWYVqjx97Sw8gIOxKynkJy8upadf49l6UoWKQAZs dpzCvcDz5fjvBtO0w4/1Bj6/gcblHoO7v1nqQGPzP6JGJXRykD3a6PS12vzqWL6UGd+O bCipIJlhM9KK4rH/FPcyZ7M56vADtrfpMqw/8/bXVFFEmcaHY4Er9KgYo8p1C0EvUy8U jO9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=DUYZuWdi50KDJFM6t80JeyKTr/492KB2PRRH4jW3Eh8jYk7CCZLJKZGjcBvgQZFEAt N1tN6pyhXpHVO2GQsmyAxbWp/NeA6gJMq8zT5GFA4Hfckj1VvIX0DeQ5gg030yWjNTxB A8uLfq8EYlOEocMH+tuiy9JHqir27A2IUBCbg8nneC/9zZ2Yko0h62oPbgaqc9U0AZIt 5Pq1RYeehifTtiSCSDVcbrsYPuC8qZVrPfA2hkC5NFkMTwmpv7x9hlMCUtM/sOnI+/3b kXOjn6ZIjZHg/BYDfzOyute8Tmi9UyanXXYhdH6gvPBKk4Bxp/ik8thdvQ20eKGH6Pgv GWGA== X-Gm-Message-State: AHPjjUgh3SMko9+TuFFGvxVjjxw8PLsTWTTxuBkkSgm2BilM+h6Na2Po d1iB0NyrOaOdZqydid4aRYU= X-Google-Smtp-Source: AOwi7QA3ckqtQnj8Ue7M+tQJ+TzuE+YFNqArnGPil/ezqmh/fr0E2JtpPEfq5mAUqCKiMysDG4lOAg== X-Received: by 10.84.131.105 with SMTP id 96mr4306064pld.229.1505968037841; Wed, 20 Sep 2017 21:27:17 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id v71sm676017pfa.45.2017.09.20.21.27.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:16 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:08 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 2/5] clk: aspeed: Register core clocks Date: Thu, 21 Sep 2017 13:56:38 +0930 Message-Id: <20170921042641.7326-3-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers the core clocks; those which are required to calculate the rate of the timer periperhal so the system can load a clocksource driver. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 3 deletions(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 824c54767009..e614c61b82d2 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -11,12 +11,12 @@ #define pr_fmt(fmt) "clk-aspeed: " fmt -#include -#include #include +#include +#include #include +#include #include -#include #include @@ -28,6 +28,9 @@ #define ASPEED_MISC_CTRL 0x2c #define ASPEED_STRAP 0x70 +/* Globally visible clocks */ +static DEFINE_SPINLOCK(aspeed_clk_lock); + /* Keeps track of all clocks */ static struct clk_hw_onecell_data *aspeed_clk_data; @@ -112,9 +115,137 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { /* 31: reserved */ }; +static const struct clk_div_table ast2400_div_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2500_div_table[] = { + { 0x0, 4 }, + { 0x1, 8 }, + { 0x2, 12 }, + { 0x3, 16 }, + { 0x4, 20 }, + { 0x5, 24 }, + { 0x6, 28 }, + { 0x7, 32 }, + { 0 } +}; + +static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ + u32 p = (val >> 13) & 0x3f; + u32 m = (val >> 5) & 0xff; + u32 n = val & 0x1f; + + mult = (m + 1) / (n + 1); + div = p + 1; + } + + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +} + +static void __init aspeed_ast2400_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, div, mult; + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + WARN(val & BIT(18), "clock is strapped not configured"); + if (val & BIT(17)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ + u32 n = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 d = val & 0xf; + + mult = (2 - od) * (n + 2); + div = d + 1; + } + hw = clk_hw_register_fixed_factor(NULL, "hpll", "clkin", 0, mult, div); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; + + /* + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) + * 00: Select CPU:AHB = 1:1 + * 01: Select CPU:AHB = 2:1 + * 10: Select CPU:AHB = 4:1 + * 11: Select CPU:AHB = 3:1 + */ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 10) & 0x3; + div = val + 1; + if (div == 2) + div = 3; + else if (div == 3) + div = 2; + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, + ast2400_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +} + +static void __init aspeed_ast2500_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, div; + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_calc_pll("hpll", val); + + /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 9) & 0x7; + WARN_ON(val == 0); + div = 2 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + /* TODO: this is wrong! */ + regmap_read(map, ASPEED_CLK_SELECTION, &val); + val = (val >> 23) & 0x7; + div = 4 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +}; + + static void __init aspeed_cc_init(struct device_node *np) { struct regmap *map; + unsigned long freq; + struct clk_hw *hw; u32 val; int ret; int i; @@ -153,6 +284,21 @@ static void __init aspeed_cc_init(struct device_node *np) return; } + /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ + if (val & BIT(23)) + freq = 25000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%lu MHz\n", freq / 1000000); + + if (of_device_is_compatible(np, "aspeed,ast2400-scu")) + aspeed_ast2400_cc(map); + else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) + aspeed_ast2500_cc(map); + else + pr_err("unknown platform, failed to add clocks\n"); + aspeed_clk_data->num = ASPEED_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret) From patchwork Thu Sep 21 04:26:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113185 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564582qgf; Wed, 20 Sep 2017 21:27:35 -0700 (PDT) X-Received: by 10.99.42.11 with SMTP id q11mr4311370pgq.7.1505968055248; Wed, 20 Sep 2017 21:27:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968055; cv=none; d=google.com; s=arc-20160816; b=vQsSbV1T8gmjo5wKWNNQpdjVho4CZ+sfjpqjMMd606zVOSXpkwA1DeAQtDtSNcKKPW TnUeNlR8+yL/RxHStVSCOKMnp4Ps1ZlZLgNJjYO69TDwHl7kwsHFWEOLqw1EMCUJ6zpo dw0oZ9Lk1QnU9lYmjrwXnpqZwvp7vl59zhjhortWRxGlWj7QN0XmYHSZlvPLcGj2LhY0 yfRVJjeu/KZ3R80MNcnY+HcD9Myd/GNbQnirYt4a4ZxO1T4ltdfrgIVWbKnke8sklNjf 1rqxPYdCnUZxKaAVkhw6IciSj9nYx1XZG43FYBAk0u0Sbzao+0ZrBGHfSI1GnNsQXa5+ e6dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=71OEE59wegSaKwixxe4ovMVJpQZrOikv73NsqgYfjWM=; b=EYhIoYTGTAOkPTxRvJGsjTnAk2w8rJ4esBijNSUcZzJPWFgXwdVlDLZUL0ZEzrmsWH NIOFYTa6my+FSFv+wsjZJxEjub4dg28aHdZ6giuSrnUKIgFkBxzL8oQWkWMB2HPSWBAb p5fS+fFtG8Yg3Yie2YHhInN1hzpOZpMLTmezjMyRwu8MyYX1tH/cUZmjm9xZX3ACPo8N af79iNp/2DKeE4nv/S9a1eisfSvCF0QjZcNCv2Fj+V5pd8qfF3+GEwGyh19KengvytQI 609D8aV9UCYKaF9Js130m5KSJRis1wUfeH+xaH7NrMMvlMJadIE3/wsS/0wAwCJ7i+G5 vS5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TWGytX5K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o20si413140pli.593.2017.09.20.21.27.34; Wed, 20 Sep 2017 21:27:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TWGytX5K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751730AbdIUE1c (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:32 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33240 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751692AbdIUE12 (ORCPT ); Thu, 21 Sep 2017 00:27:28 -0400 Received: by mail-pf0-f195.google.com with SMTP id h4so2030702pfk.0; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=71OEE59wegSaKwixxe4ovMVJpQZrOikv73NsqgYfjWM=; b=TWGytX5K0TMenYDPZO7xfjLpQrjUX10ewaVSWp9UbSahdsh8GDJ4YVgr09RvUuytJJ Wf0tTRorWmxXDcidtTCMy9WrJexxrzKjJmymMnTt+7bgh6anpwD+n1wUNjzoWHLRaDRh Gud/haISBhvTEDVHXWRwv/K2ZHS15vif9I4v8TQdYJIBApf5Xv4hQ0nKyNxALxKUF1Ce p4/F9TA90ggClVyxuD+gEPY1JZI3Ttn3plIZa/o0I0RHqEByS3kgDeuUSkqfouovcSxj Zo3mxiu06UOvnmUnMGfGmn9RVd63daygvDHTYYYRfxOpMziObAR2gABJPGjwZ9DePM4C /D/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=71OEE59wegSaKwixxe4ovMVJpQZrOikv73NsqgYfjWM=; b=r0Ll6TKkMNMsKoVVfCkUwlkP/vnIc7+zv+3Sx/U686/HLCE7qXQG6SSCWVPMhps96A WPcHJJdr07w7nLrBtdorpdHEyyXXlRDaoic3uGRShq4OFAfpL3Q72rI37YyBvilfrTwH xJCCKbZOcjvlJJKlcA9UznDCS4jiSZ6skvCABT1ojpE3mw2628YLCSeCw2yc9f+xS+gd 7JDZqkBXJe8j5Oh4v1LZryatyu2iRb3i42AzFDzCYe2QSQEKnGu3j89MUMfP+1L1Rt0K 8Jkr8RlOWbrX+Qe/MGluchtXfRIwMJUbjaRyqxh8+aRqxYMwJKZHCAeVtZN+aLNbmqQ9 OlGQ== X-Gm-Message-State: AHPjjUg2+AuyQ/jgyg/oKX24kY0mDsyjTpNu4K9L3PyiAlpO+h6JDqUS wvpF71ryRzHH4GCJCkSmqGg= X-Google-Smtp-Source: AOwi7QD1jKerE7EJrB1AHcuX/FVNWKOstKwQr8yJ3MMQSM8hnKpOnXiAsKrsIshFqDWjaotFN4A18g== X-Received: by 10.84.193.131 with SMTP id f3mr4080378pld.90.1505968047894; Wed, 20 Sep 2017 21:27:27 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id v2sm558715pgo.38.2017.09.20.21.27.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:26 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:18 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs Date: Thu, 21 Sep 2017 13:56:39 +0930 Message-Id: <20170921042641.7326-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 129 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index e614c61b82d2..19531798e040 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -115,6 +117,20 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { /* 31: reserved */ }; +static const char * const eclk_parents[] = {"d1pll", "hpll", "mpll"}; + +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -139,6 +155,21 @@ static const struct clk_div_table ast2500_div_table[] = { { 0 } }; +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, +}; + static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) { unsigned int mult, div; @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) mult, div); } +static int __init aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + const struct clk_div_table *mac_div_table; + const struct clk_div_table *div_table; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(&pdev->dev); + div_table = soc_data->div_table; + mac_div_table = soc_data->mac_div_table; + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & BIT(12)) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(NULL, "uart", NULL, 0, rate); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll("mpll", val); + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(NULL, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(NULL, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + mac_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* Video Engine (ECLK) mux and clock divider */ + hw = clk_hw_register_mux(NULL, "eclk_mux", + eclk_parents, ARRAY_SIZE(eclk_parents), 0, + scu_base + ASPEED_CLK_SELECTION, 2, 2, + 0, &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; + hw = clk_hw_register_divider_table(NULL, "eclk", "eclk_mux", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 0, 2, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { }, +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw; From patchwork Thu Sep 21 04:26:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113186 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564650qgf; Wed, 20 Sep 2017 21:27:42 -0700 (PDT) X-Received: by 10.98.204.157 with SMTP id j29mr4433888pfk.100.1505968062651; Wed, 20 Sep 2017 21:27:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968062; cv=none; d=google.com; s=arc-20160816; b=FTi+vcUbWl32s8VawJprvcdciibE/Pft7ToQ6EhexQtj6fJ/rH8sAyv2SYP2XFeuFL +qxY27MU4RsisIRq/mfJ+42dZEGWm4qDg35MU64i1VVqD2dIyM0ralkVk/Ho0CoHNNQd JrfGIzSOxMv5QpTqrwF4ujlUvhPk6LWVKxQ0dflnsKI36bS1Sxywj3eydbWjW6EfAEBY FP1GQb9UZdPnVVXECLbXETZG6GUWZQUcSTzSMMtzXhQmJowYLALlz6Gvu8bHmMU2QOqk qorlnKT+j/zkPEnR2cQxnl7pDvszp0ZJ5QAOaozKzqeaEXeC9oRIxMuOIB2hn4sU4lwI Rb4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=LynmDiW2yu969B2RaKDWO/+SAdOqh+VivvWviNFvFp4=; b=Q3Wm+eHD4jv24rsXkpZRt5rcvq11wYikAbKdF0n0N/wz/GkOMYqGTjp4gXMNVgAPk4 UJOS0CBrsY67HCJ8kq0JjN2D2Hcwtqdij2Vuy/vWDMtrWYze1gThiNYTttL4TQtfB0kQ LHBt9lvkdcJsuVZ/bgVEkaLSC8tSQquq4GuzyBQdPRPVSbOLXA2nFM8Sprd6S/iVM9XR uR0rfTsxE8DIKfv0YBzJSwKjEkz8oMTWoth2bqlwWilasRhWePKoJiGCvW3L/IO0qhG2 U0HTp9AUPkbZPGE9z6VxIgmFXbq9AK5qZZr8C0xePF5XpQRmOZ39MGA075uH33i8gPGr M7fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TzH0sKbH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o20si413140pli.593.2017.09.20.21.27.42; Wed, 20 Sep 2017 21:27:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TzH0sKbH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751775AbdIUE1l (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:41 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:34525 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751735AbdIUE1i (ORCPT ); Thu, 21 Sep 2017 00:27:38 -0400 Received: by mail-pg0-f65.google.com with SMTP id u18so2795797pgo.1; Wed, 20 Sep 2017 21:27:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LynmDiW2yu969B2RaKDWO/+SAdOqh+VivvWviNFvFp4=; b=TzH0sKbH4nlrRoqrS6IiR5CpNHY0a5/LLGBaOGEt1LqqHeV7UucyZDPO6eTEJmlMnz KPaDVA5xZzzR1+o9yadCz3oElHQOsFqu7/HrurrdhEVWhmaggbeFpM/eDfVTGONcOBJq A7M7DxLVGcZxKLgUaFLr3dHR+Lz26WhvEYt1mSjBJGZNehmRAjITkNVWJofYM0XBy0IH BHIgPHdmzxcbY3NpUY2EcVrQ9IBw3o2E4pRgvw3+dgOLlHQ/QCjab+F8QGM3HX+bOKVB dsjvzW3zZSKlPISBl7QgAV4R0JbT7NDWmuySvTJTZLyjz8TId/RowAxT0hNSNUBaCZjU 5QTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=LynmDiW2yu969B2RaKDWO/+SAdOqh+VivvWviNFvFp4=; b=N7bOY4V5Q1tphXW1p5MWiRB03FokjwC7+xv50QM9y0nMIvVuUEOd/vSOM5VChYP5xm F1ppZganrQ0QMiYVMQaFJJxvm7ba0FeKidsiNNN44ZPLOeMiebB4EHOOVTzEbwtZSJkN /Obf8wLamWQaz96uHIhPpmcuDlwHDrGLWpiN2N28p43cKnYDG70jIdf7DpxavRkJha81 jbi1VnMoxOcd72qvnJ7BQadZ/bUxCKMZQEOBPnjAzPKlC5cEDezERl/KPilxxKa+Ayiw k1qzqfNt3aI6elnYec66PynqQ4LYK/A0rDuT1tSqq0A/sHzPGmzguqYGh6oQ56v1Vgvr ltHw== X-Gm-Message-State: AHPjjUhDNuDQNrdOeBaUSFBiaXfznnsgRYpMWeCM2WzXsP6yWGDkLfhB TaH64CQK2fBouqubLGiUhEI= X-Google-Smtp-Source: AOwi7QB1JXS8fapXZcSz94sWrx9UL2CRYFn39T+IQ+2a1nxZc8JtKpiX7X/182aHCk1zv3qQxAPrPQ== X-Received: by 10.98.211.76 with SMTP id q73mr4354442pfg.348.1505968057698; Wed, 20 Sep 2017 21:27:37 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id w90sm705502pfi.80.2017.09.20.21.27.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:28 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 4/5] clk: aspeed: Register gated clocks Date: Thu, 21 Sep 2017 13:56:40 +0930 Message-Id: <20170921042641.7326-5-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 19531798e040..dec9db4ec47b 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -191,6 +191,108 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) mult, div); } +static int aspeed_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + u32 rst = BIT(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); + + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0); + + if (gate->reset_idx >= 0) { + /* Delay 10ms */ + /* TODO: can we sleep here? */ + msleep(10); + + /* Take IP out of reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + /* Disable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk); + + spin_unlock_irqrestore(gate->lock, flags); +} + +static int aspeed_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = BIT(gate->clock_idx); + u32 reg; + + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + + return (reg & clk) ? 0 : 1; +} + +static const struct clk_ops aspeed_clk_gate_ops = { + .enable = aspeed_clk_enable, + .disable = aspeed_clk_disable, + .is_enabled = aspeed_clk_is_enabled, +}; + +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_clk_gate_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + static int __init aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; @@ -200,6 +302,7 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) struct regmap *map; struct clk_hw *hw; u32 val, rate; + int i; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -269,6 +372,31 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) &aspeed_clk_lock); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* There are a number of clocks that not included in this driver as + * more information is required: + * D2-PLL + * D-PLL + * YCLK + * RGMII + * RMII + * UART[1..5] clock source mux + */ + + for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { + const struct aspeed_gate_data *gd; + + gd = &aspeed_gates[i]; + aspeed_clk_data->hws[ASPEED_CLK_GATES + i] = + aspeed_clk_hw_register_gate(NULL, gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + CLK_GATE_SET_TO_DISABLE, + &aspeed_clk_lock); + } + return 0; }; From patchwork Thu Sep 21 04:26:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113187 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564714qgf; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) X-Received: by 10.84.233.65 with SMTP id k1mr4181489plt.284.1505968071659; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968071; cv=none; d=google.com; s=arc-20160816; b=yMDVC+5YCbZTVitckkSpWsXbibDAvrkiArOuftxpoNmY7UeoGq6YVMr9bxeRDp/bIG 3ctMrHZV7PbQuZrrMG9Q+0gYjU9AviOVn2mKnBe5mt7twV0zTyf7j5J3AZ+QNTssAOSN qYHbB72vybFm9wIrrHRraWpeJCJSR+Ydb3abLlq3EpSmEx6oRdJB2lKa2ElckJ4W8F5z ommLgiTHNB+MKE7TpdhlLkE2Pu8ZJovr0hVHmGRaSJP2TLjCbQBHgiVYPlL8l4D22JZs mOjLpUR74d6G6UQS3SgiePNN756aOM6m4MFHS+sHKDBsEqMdyr76F/Pztqz5XTucO7Aa kPcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=Aj1+8vDLMMcYsu6JvsiIiyGlvEOFjcumho3ENj8+LkR+kBTkdPqdTvV1qKPscH14Ri p0650BiUcqJO5WmMntrt3tnNdaBc041NUpWj7sjvUSLsPxq1Rkbws2EpHNVSbK/iQ6SY 2y20iuimv+xNWwae9GTNovlbJdNJxlrPqb5eeqq9nhSefpYDvWhEDMTPHSt1iKp0mKqB h+NjLu4XSzC7fMUTviSwNmKnKHqTs9F7QmbdYjiye6iVmIGL3TmiP4Yk/JLobAwMClC9 Jd0ED0sFkrbvJ+XlnM1JYqDdPv1dn450m1/bFYMGw3oPUK6kyMlLbvf6ur3rnfAPs/dw fqhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ag8Kmszw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x15si421341pff.156.2017.09.20.21.27.51; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ag8Kmszw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751796AbdIUE1t (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:49 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:34562 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750912AbdIUE1r (ORCPT ); Thu, 21 Sep 2017 00:27:47 -0400 Received: by mail-pg0-f66.google.com with SMTP id u18so2796037pgo.1; Wed, 20 Sep 2017 21:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=ag8KmszwNGiafFBoi7LWcyblhw0lViod7hXYMeY40mxn7UIlcd3TQk5RLwkMYApuzl iO8m9l/BjrcBpxV83c8w0U4WBugQdOaoB7r3DHvgL24Ggv5OtSyI/oXuczDaEw3ypvE0 J4viI8HHia9p17jnRVdUC6HlJzAQGzayDH/mllMCp2Mpd29ZYge/682hxpC7X/5FSS+7 7qwyBdmza9cBVFuu1HL5wWL1axB14/Onrs3vp7uriSQny7piiyvpdxzpd9KQjmuHJa/l WI1mcJ4TEuPRuIZiTmZuA5liVC9F4r4W2ztU52nml8IpRb7XvTj9Da/uwmXNemJIZt94 A3wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=POh7iMI9Wa38A40+/0BOnzkZA3N1R+mRCtDArd1YNxvtO/eqrpGJTBxKuoQoKdE1NT 6AoyLxOndob2jqcksFkTg9ycwHfVvXE1P9WtQW9j/NWSxtRtixRsey1pIh4uzwLu4AoX T3eDE6O23NEtN63vPdykpQOkJDlZJZuGbohAykiHLhcWFSq78NlP6l4jn2IXM9uu3Fh2 zQDxRZy66+KJgpeRUIihuhE/TUKOPaUyv0VVAOPA+rj5mODtVk6GcIe5SV7ugzF9/EcB DdLgw8BSOk9dqPKruvphqkGGmjXatBylh4STLcG/ZUrgS85odwNXQ9RNSpYWnL2KYr2/ mJbg== X-Gm-Message-State: AHPjjUgyaEy666GBbDUJlTlg8Hi89ZY0iXYrawA96a21cLQ/11fUzy1C a8YZ1u9kZlZudJaJcQiQNgE= X-Google-Smtp-Source: AOwi7QB3t5w5Z3U56cLul6J7t2v/DmBvaCPyFy7CHlgCYEqRPWA4+fSzI897XkB8KuMsuu3DCSwoNA== X-Received: by 10.98.32.139 with SMTP id m11mr4423522pfj.172.1505968066868; Wed, 20 Sep 2017 21:27:46 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id 65sm584995pgh.31.2017.09.20.21.27.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:45 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:38 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 5/5] clk: aspeed: Add reset controller Date: Thu, 21 Sep 2017 13:56:41 +0930 Message-Id: <20170921042641.7326-6-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are some resets that are not associated with gates. These are represented by a reset controller. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 9 ++++ 2 files changed, 90 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index dec9db4ec47b..db97c0f9f99e 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -256,6 +257,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + 25, /* x-dma */ + 24, /* mctp */ + 23, /* adc */ + 22, /* jtag-master */ + 18, /* mic */ + 9, /* pwm */ + 8, /* pci-vga */ + 2, /* i2c */ + 1, /* ahb */ +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -299,10 +362,11 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) const struct clk_div_table *mac_div_table; const struct clk_div_table *div_table; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -310,6 +374,22 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(&pdev->dev); div_table = soc_data->div_table; diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index afe06b77562d..a9d552b6bbd2 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -40,4 +40,13 @@ #define ASPEED_CLK_GATE_SDCLKCLK (22 + ASPEED_CLK_GATES) #define ASPEED_CLK_GATE_LHCCLK (23 + ASPEED_CLK_GATES) +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_JTAG_MASTER 2 +#define ASPEED_RESET_MIC 3 +#define ASPEED_RESET_PWM 4 +#define ASPEED_RESET_PCIVGA 5 +#define ASPEED_RESET_I2C 6 +#define ASPEED_RESET_AHB 7 + #endif