From patchwork Thu Sep 21 16:49:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113881 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp2093755edb; Thu, 21 Sep 2017 09:52:16 -0700 (PDT) X-Received: by 10.98.155.220 with SMTP id e89mr6452173pfk.120.1506012736074; Thu, 21 Sep 2017 09:52:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012736; cv=none; d=google.com; s=arc-20160816; b=DBHfoUh72eNQNVlTVJF+sUgajWEUUs4ACzuDgo9cSfZj/J10dH8WXWwmEO7rZeGWOy q0FeRw/7XlUiV/I+KVhG/N1WgwYCOWMEm9S558dz0PQLUYjDEWCZzHSV9CZhf7Tk4ugX /I5GWmajQ4B/njLjMkQy9csX0QYY0KExQzxSw+eborqURdDnfaLcGSQQp1HmBQM2bwAm HEexDdxn8oPT5Gw2QSp7VdrMdFRT9PxORkC/kGl7FH7vMk+VZu56B+cmQvwhYvIsHwtC JUUeoWhxVySZ5fUeJZwNgZ8pBG0o9JmVoqGV+2MjrQDXiOUmCrHWuKO0DII4QoXgwVX1 pTRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1QIZ9fOhgp+Mwd8ZF/LzSbbyEXZYeItAy+5XESFmLxQ=; b=EACeGJ9f44QDfq/WwMTKNF4GF9+FGYwNBIvFChtHFqsx6opJkCDSz+0pSd3Sk3cVEu LhS+BqoEDExfmDHPzXESOSseZEvziuMRV+kRKey4x/LirwsBZl/6k7als4uPnTQue1tl 27hkFa0IED3p5UDI+wZ9JAhh/KXuZajDVud7sKVqwVotRwdjrQH5VzYj6AFbxUIZVUhF /d4jwZiUFPf8I0bCoDRYYlEB+Ci+N6m8Sjd7tjXnxD53R31ajzzOdjfx00qSjrkypKvd nca4dXbHOiTAUx6zcrD7GcXlM78HZend/WPG7AV8JxIArbiQgo5Y2FTParaQ7XHA/9Kn psvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LrZ8NMy0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z15si1200144pfd.587.2017.09.21.09.52.15; Thu, 21 Sep 2017 09:52:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LrZ8NMy0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751718AbdIUQwO (ORCPT + 6 others); Thu, 21 Sep 2017 12:52:14 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:45387 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751786AbdIUQto (ORCPT ); Thu, 21 Sep 2017 12:49:44 -0400 Received: by mail-wm0-f45.google.com with SMTP id q124so3600393wmb.0 for ; Thu, 21 Sep 2017 09:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cQ6nctdD3xxvI++h3kyzuAgAJ5SWN5qaOMScnTFfGOQ=; b=LrZ8NMy0MAU7MMlVlDnnkJjM/n33CxY93PA/M3Up54hiMr9pj/i89w7Yg0J/1scQ/i SduY73Erni+ypc6aLbLyh7S+aqA43mmjxledHegW/SByLAtm2tyqgdifFjHx6K5h+f6N 5zUk/EQKqh31ufeHmcMZ3CccB/4PMULkQYhkg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cQ6nctdD3xxvI++h3kyzuAgAJ5SWN5qaOMScnTFfGOQ=; b=Z4IwZtZJyYtBu8anYtw7wghJfpz4KcDBDttnxLueDI8RplWz3OlbazKr0h/GxKrKQf hr1GKvNu75QbVrEbHULKE3Y+8TEOZlXZDLeruoZ4Ta7Gzu57cZTOOCBC2dCdccmjutpX M5YzOQy//gsl//KGdKtLNqw0rDYn0OzpFvYuC6tLj+E6P9m/bbdOBxIeuo52Q6GBmHyw 9r/D/pDLi7foa49ZST9jxoZ9BkAnHt18GtEzoqiHFEkMtB+a4m6lBJfeB4aI800/zQC5 NrBbk5EWuBKz727lNsKreUT0Zkcu+VdyeY4BOzwy2i10AITl3PYJbu8xivZ7rVRHlvVF uwCA== X-Gm-Message-State: AHPjjUhB9dxPaKYI1oG/f0WQQxAfca+JfNDCSrdQJG5P3xJRdd61SnEm yWmUQkcn2oPpzjXc0H98rKb/Pw== X-Google-Smtp-Source: AOwi7QBHW5sX2jrgiRnwl55Mt7pbHNSSZaNrqqf4pwgZPBTfj854Kv4ll7v0IqssNslMYmbxV6Mf3w== X-Received: by 10.80.241.92 with SMTP id z28mr1864936edl.294.1506012583652; Thu, 21 Sep 2017 09:49:43 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:42 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 1/7] mailbox: qcom: Convert APCS IPC driver to use regmap Date: Thu, 21 Sep 2017 19:49:34 +0300 Message-Id: <20170921164940.20343-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This hardware block provides more functionalities that just IPC. Convert it to regmap to allow other child platform devices to use the same regmap. Signed-off-by: Georgi Djakov --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9924c6d7f05d..ab344bc6fa63 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #define QCOM_APCS_IPC_BITS 32 @@ -26,19 +27,25 @@ struct qcom_apcs_ipc { struct mbox_controller mbox; struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS]; - void __iomem *reg; + struct regmap *regmap; unsigned long offset; }; +static const struct regmap_config apcs_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data) { struct qcom_apcs_ipc *apcs = container_of(chan->mbox, struct qcom_apcs_ipc, mbox); unsigned long idx = (unsigned long)chan->con_priv; - writel(BIT(idx), apcs->reg); - - return 0; + return regmap_write(apcs->regmap, apcs->offset, BIT(idx)); } static const struct mbox_chan_ops qcom_apcs_ipc_ops = { @@ -47,7 +54,9 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { static int qcom_apcs_ipc_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct qcom_apcs_ipc *apcs; + struct regmap *regmap; struct resource *res; unsigned long offset; void __iomem *base; @@ -63,9 +72,14 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + regmap = devm_regmap_init_mmio(&pdev->dev, base, &apcs_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + offset = (unsigned long)of_device_get_match_data(&pdev->dev); - apcs->reg = base + offset; + apcs->regmap = regmap; + apcs->offset = offset; /* Initialize channel identifiers */ for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++) From patchwork Thu Sep 21 16:49:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113877 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp2093150edb; Thu, 21 Sep 2017 09:51:34 -0700 (PDT) X-Received: by 10.98.215.6 with SMTP id b6mr6309722pfh.220.1506012694412; Thu, 21 Sep 2017 09:51:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012694; cv=none; d=google.com; s=arc-20160816; b=KQrcvcNjkBpphfVeXJN/8+E0GDn8+I0jjgPxOaCbesrZBPgfOzdYIctrNynBdm4NMC V5F5vaRew2e+lpEG1xi5bns1Ts1zFOUG0DFY5xVNJ6dZnlN06mG1SjEDG2nISSzE0+BM VHzPwBFVP9hIltfuTfAbrscwYtmSWc0L58tLYKlbTw3cXyAkLnW+9QYjMOFGaAUpPdAR vcCcLh+f+JUWURRafADGjtULQqBFGXmjOCncN2xHw6zQT2ppi/idd7x2VCg3YeUXrk69 HNv6B9i6JL5Io43Dux4OXM7hG059Kw7Xyt1QVXuiNnyCyGv/JwcygoRaeOiA2rHU8zWc da4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=PijP79LaIICnVhnygy9mGHTKx4fsWco6XE4O3kX5yQU=; b=AP0WRdJ1EzZs0NNUUx7poWoLxYU7/7W7JedfY2Yqqpnxu5Bs7PqwslKvmHqEQbEf0C f+VDbiJqXuaT9+wc0HBOw9j2OG539AAlKw1KiMPGmZqMB+EWOctnxaTA22SQ5eTeBm/N rBhHWkSGmybHN6UD4ZFjOiHda5bOKo3ZPd27/ehcfw4pHQfhXDyvX4ynilBfs4w2Ku0T Tf7nkFTr5iRjGwl5hsBYdGIjPQgTeiuzyV8PMRZIQjjCe1QIM0hx2jFNihmgbqPymOhB P5yivIwIvNe2YsBPawYbyEbDTAz9haj6ar1K7dzRP+iDvZBHgEINyBanR4cDS+Rln1VJ Q2zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T74in/PE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v89si1256577pfi.21.2017.09.21.09.51.34; Thu, 21 Sep 2017 09:51:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T74in/PE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751745AbdIUQvc (ORCPT + 6 others); Thu, 21 Sep 2017 12:51:32 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:50182 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751870AbdIUQtu (ORCPT ); Thu, 21 Sep 2017 12:49:50 -0400 Received: by mail-wm0-f47.google.com with SMTP id b195so3559859wmb.5 for ; Thu, 21 Sep 2017 09:49:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PwwBcdzRnJVhmA9Fo2vN/PO33kPNYzKtlUlIy+FKAx8=; b=T74in/PEHnYvT/jnUkToaOXxqWxnjsjUO0UIHnZI8zHFc4iTBHztH9y+CDhsu7qXiT S595C2wjft81M+0WofTQdWJQNGhvDBVICk2uvDrmEs56iwYL3Uy4Ws5AIj9XLxMeu4rP eFb1O62t+uCam/jVFR8qC8LjEZ5Wnnv1dxs8E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PwwBcdzRnJVhmA9Fo2vN/PO33kPNYzKtlUlIy+FKAx8=; b=UWhKt6cgcIYc6CPWs43HY+WmfUt43rE1eP06+lRTpJkQnSdGFZTOfco/flAL1pY00v Bqb25GugWe90qId8zn7V6Z/jixgVS0nr11EhAfev/X3+rUMAZ+wIpSDzxZiA++6b24gi w4m7TYtq6Ilo1gSu3Da8gU2XPyEqeI4J4p+A6XlLjMwjED/EtUTLD6fGqB0t5Hwg94lH wGH3rro24dr/F3rfov7CWqIuI7bAP6OhreHmb8Fx+q4jc5xnLgP/9cy3xQ+VpaC9jltS wfn1qkH7wXmu/nr1bE7N89jdwdLran5qhgAdzRXYIsET15kHcYrO3nMVWFcZeHIQhdph LT/w== X-Gm-Message-State: AHPjjUjAio7lE8vRc8TW71tZRgvN9486OchktK2HBCi+L3/Ii7T/8NfZ qXd2SfJm4lOFwWNrj1AADzicZ2f093w= X-Google-Smtp-Source: AOwi7QClC9Po6MEghA/9E9GRI++LgJ67tCWa+LsIGTAAgEEnfm2en5SNb5I6cIz5ZiJ7wwKs7NJtsA== X-Received: by 10.80.224.79 with SMTP id g15mr1845079edl.259.1506012588584; Thu, 21 Sep 2017 09:49:48 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:47 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 4/7] clk: qcom: Add A53 PLL support Date: Thu, 21 Sep 2017 19:49:37 +0300 Message-Id: <20170921164940.20343-5-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++ drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 107 +++++++++++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..e3fa8118eaee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..81ac7b9378fe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -12,6 +12,16 @@ config COMMON_CLK_QCOM select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_A53PLL + bool "MSM8916 A53 PLL" + depends on COMMON_CLK_QCOM + default ARCH_QCOM + help + Support for the A53 PLL on MSM8916 devices. It provides + the CPU with frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on MSM8916 + devices. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 3f3aff229fb7..19ae884b5166 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -31,5 +31,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..6276934daa0a --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 65, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, +}; + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,msm8916-a53pll" }, + { } +}; + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct clk_pll *pll; + void __iomem *base; + struct clk_init_data init = { }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + ret = devm_clk_register_regmap(dev, &pll->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + return ret; + } + + return 0; +} + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver); From patchwork Thu Sep 21 16:49:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113872 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2244482qgf; Thu, 21 Sep 2017 09:49:58 -0700 (PDT) X-Received: by 10.99.140.29 with SMTP id m29mr6278536pgd.126.1506012598786; Thu, 21 Sep 2017 09:49:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012598; cv=none; d=google.com; s=arc-20160816; b=BSvR1YeE+f7aNWP4fOjlM/pQtoehY3xtS9coIGTqNrShE0Z437GEVBd3FtrKHLdNvq CUgRyV+AMP+RGKIBW6t5CIH1qHbdCyeHPxTX2T7PAf6Hd7RdMYdU017IlsEWWquSrbFy BM4zys/ETRAPNG3oBFFuzz+ym5G5oe72Z5HPMuy0nHmW047CstAx7u8LkloF/1gbCZGD WX4JcnzOKKOLQ/HVNP5LLKyaiARyxt8yohDiNxIni2E1ERGeQJREup5DmgI/Q94OCA5w OxUnAO0CmZTWwnmAE98jwVWIVC8Pmk/KFB+hIlb8zLh5xKbSnJRbz5LT0mr2q0VgXul/ tXfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=bPasPpduKW8lvxA4eKimmxtSWg0WLHGLTXm8tYQgj5E=; b=cxzkiXtDLszF8hqW8ORNaihGxBU0mWBXXtkYC9j5gVsHc4F8uV3acycN608YkEu18y MxVFtZNsqJ6aOsh84jr3TWzorBn5tjdiFYsJEb1OjihlygICpvJmLqpwPQBa/8CtAnu1 8I629ObYJ+MGTmIbOdbLS3ju/1sRIgUuqFSvq5/CVkj3JF4Co2o6XeQi45TrVw8Rb0LD QiNJ+6I8KO+CbW9EhAKhNUAq2CSN3J1X+jYOjBsiHi5Ty/YLfL5lU1F2scKQWl+Gh6Rt Br9yAewx4DDgDtqHOl4CY7CjPZ/ZwiEAcKe395vrKa9fsEtRybnZyr7DWnMP6GhxiKgJ JF5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=I7o+lbE8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s125si1246347pgc.548.2017.09.21.09.49.58; Thu, 21 Sep 2017 09:49:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=I7o+lbE8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751860AbdIUQt4 (ORCPT + 6 others); Thu, 21 Sep 2017 12:49:56 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:47402 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751879AbdIUQtw (ORCPT ); Thu, 21 Sep 2017 12:49:52 -0400 Received: by mail-wm0-f44.google.com with SMTP id r136so3582443wmf.2 for ; Thu, 21 Sep 2017 09:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tDdFWTC7RAr+bYMyj4FY5nPYqfJVlTHloyadnyhlHzA=; b=I7o+lbE8PodbWaypsyjVh/kT4BwwTFyZFP5vZ7p70kCy2XiFO00MPLl7ami1M08Ocb Y9LuFEB+Udr4BUM+H06M+ps9P3YKffHGPqSqSAE65c39OX1u1ErmLAbp+gd6APk5IK/u R+6K962C4Mxbt5917y8BWnwcbiWM1VFrLGKqk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tDdFWTC7RAr+bYMyj4FY5nPYqfJVlTHloyadnyhlHzA=; b=cftnxOttwFmVrf3+zcYVEFnz+/HbSKgjeIjxDDm+HrJ6nHkpBZvuJ04vaFw9KRG59k luYo1EKQfq4HwaViGZWL4CJxm+oGGTmCtNtv6KQhk+f75gq184LKpocPwGUZGyfbwAIa Sm31A4rFdM0qngN2w09cYaRil6CAISXujQ0hQ+kVU2DGjtRqlmJI7TWramAN538V0Tza ZWD/aIGl4mkHVovRnjN7kAWOmwQ9mJSELOOuvHlLOH7yGY3ADaE09rPng4kyhClhRybx SdmQmUJXlFL3r/moIMbLOPdWQMh6GyH5h6YagXFojjaiszU7DCes7aTxhfelFxpuBm6c Sd+Q== X-Gm-Message-State: AHPjjUg7ZA7ZaQ/L963MivoAHWsHnoS3Y7N5KjafH5D2s1WBD9GCQEXb ciQwdLgSjEpOKQVWgzJjGODbcg== X-Google-Smtp-Source: AOwi7QAMKOWsLwRbfOeSt1IhFeAhyiXN9CPnRtm/Lk/v/oCR9F5bHNuvr/YPOw+2NKfFMP6n/1Bujg== X-Received: by 10.80.220.12 with SMTP id q12mr1813241edk.219.1506012590384; Thu, 21 Sep 2017 09:49:50 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:49 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 5/7] clk: qcom: Add regmap mux-div clocks support Date: Thu, 21 Sep 2017 19:49:38 +0300 Message-Id: <20170921164940.20343-6-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for hardware that can switch both parent clock and divider at the same time. This avoids generating intermediate frequencies from either the old parent clock and new divider or new parent clock and old divider combinations. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-regmap-mux-div.c | 237 ++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-regmap-mux-div.h | 54 ++++++++ 3 files changed, 292 insertions(+) create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 19ae884b5166..ac38c2b21847 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,6 +9,7 @@ clk-qcom-y += clk-rcg2.o clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o +clk-qcom-y += clk-regmap-mux-div.o clk-qcom-y += reset.o clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c new file mode 100644 index 000000000000..5ec31ec3efa7 --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-mux-div.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "clk-regmap-mux-div.h" + +#define CMD_RCGR 0x0 +#define CMD_RCGR_UPDATE BIT(0) +#define CMD_RCGR_DIRTY_CFG BIT(4) +#define CMD_RCGR_ROOT_OFF BIT(31) +#define CFG_RCGR 0x4 + +#define to_clk_regmap_mux_div(_hw) \ + container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr) + +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) +{ + int ret, count; + u32 val, mask; + const char *name = clk_hw_get_name(&md->clkr.hw); + + val = (div << md->hid_shift) | (src << md->src_shift); + mask = ((BIT(md->hid_width) - 1) << md->hid_shift) | + ((BIT(md->src_width) - 1) << md->src_shift); + + ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset, + mask, val); + if (ret) + return ret; + + ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset, + CMD_RCGR_UPDATE, CMD_RCGR_UPDATE); + if (ret) + return ret; + + /* Wait for update to take effect */ + for (count = 500; count > 0; count--) { + ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, + &val); + if (ret) + return ret; + if (!(val & CMD_RCGR_UPDATE)) + return 0; + udelay(1); + } + + pr_err("%s: RCG did not update its configuration", name); + return -EBUSY; +} + +static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src, + u32 *div) +{ + u32 val, d, s; + const char *name = clk_hw_get_name(&md->clkr.hw); + + regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val); + + if (val & CMD_RCGR_DIRTY_CFG) { + pr_err("%s: RCG configuration is pending\n", name); + return; + } + + regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val); + s = (val >> md->src_shift); + s &= BIT(md->src_width) - 1; + *src = s; + + d = (val >> md->hid_shift); + d &= BIT(md->hid_width) - 1; + *div = d; +} + +static inline bool is_better_rate(unsigned long req, unsigned long best, + unsigned long new) +{ + return (req <= new && new < best) || (best < req && best < new); +} + +static int mux_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + unsigned int i, div, max_div; + unsigned long actual_rate, best_rate = 0; + unsigned long req_rate = req->rate; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(parent); + + max_div = BIT(md->hid_width) - 1; + for (div = 1; div < max_div; div++) { + parent_rate = mult_frac(req_rate, div, 2); + parent_rate = clk_hw_round_rate(parent, parent_rate); + actual_rate = mult_frac(parent_rate, 2, div); + + if (is_better_rate(req_rate, best_rate, actual_rate)) { + best_rate = actual_rate; + req->rate = best_rate; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } + + if (actual_rate < req_rate || best_rate <= req_rate) + break; + } + } + + if (!best_rate) + return -EINVAL; + + return 0; +} + +static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u32 src) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + int ret; + u32 div, max_div, best_src = 0, best_div = 0; + unsigned int i; + unsigned long actual_rate, best_rate = 0; + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(parent); + + max_div = BIT(md->hid_width) - 1; + for (div = 1; div < max_div; div++) { + parent_rate = mult_frac(rate, div, 2); + parent_rate = clk_hw_round_rate(parent, parent_rate); + actual_rate = mult_frac(parent_rate, 2, div); + + if (is_better_rate(rate, best_rate, actual_rate)) { + best_rate = actual_rate; + best_src = md->parent_map[i].cfg; + best_div = div - 1; + } + + if (actual_rate < rate || best_rate <= rate) + break; + } + } + + ret = __mux_div_set_src_div(md, best_src, best_div); + if (!ret) { + md->div = best_div; + md->src = best_src; + } + + return ret; +} + +static u8 mux_div_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + const char *name = clk_hw_get_name(hw); + u32 i, div, src = 0; + + __mux_div_get_src_div(md, &src, &div); + + for (i = 0; i < clk_hw_get_num_parents(hw); i++) + if (src == md->parent_map[i].cfg) + return i; + + pr_err("%s: Can't find parent with src %d\n", name, src); + return 0; +} + +static int mux_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div); +} + +static int mux_div_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long prate) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_rate_and_parent(hw, rate, prate, md->src); +} + +static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u8 index) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + + return __mux_div_set_rate_and_parent(hw, rate, prate, + md->parent_map[index].cfg); +} + +static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw); + u32 div, src; + int i, num_parents = clk_hw_get_num_parents(hw); + const char *name = clk_hw_get_name(hw); + + __mux_div_get_src_div(md, &src, &div); + for (i = 0; i < num_parents; i++) + if (src == md->parent_map[i].cfg) { + struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate = clk_hw_get_rate(p); + + return mult_frac(parent_rate, 2, div + 1); + } + + pr_err("%s: Can't find parent %d\n", name, src); + return 0; +} + +const struct clk_ops clk_regmap_mux_div_ops = { + .get_parent = mux_div_get_parent, + .set_parent = mux_div_set_parent, + .set_rate = mux_div_set_rate, + .set_rate_and_parent = mux_div_set_rate_and_parent, + .determine_rate = mux_div_determine_rate, + .recalc_rate = mux_div_recalc_rate, +}; diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h new file mode 100644 index 000000000000..0cfcb9f4429a --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-mux-div.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__ +#define __QCOM_CLK_REGMAP_MUX_DIV_H__ + +#include +#include "clk-rcg.h" +#include "clk-regmap.h" + +/** + * struct mux_div_clk - combined mux/divider clock + * @reg_offset: offset of the mux/divider register + * @hid_width: number of bits in half integer divider + * @hid_shift: lowest bit of hid value field + * @src_width: number of bits in source select + * @src_shift: lowest bit of source select field + * @div: the divider raw configuration value + * @src: the mux index which will be used if the clock is enabled + * @parent_map: pointer to parent_map struct + * @clkr: handle between common and hardware-specific interfaces + * @pclk: the input PLL clock + * @clk_nb: clock notifier for rate changes of the input PLL + */ + +struct clk_regmap_mux_div { + u32 reg_offset; + u32 hid_width; + u32 hid_shift; + u32 src_width; + u32 src_shift; + u32 div; + u32 src; + const struct parent_map *parent_map; + struct clk_regmap clkr; + struct clk *pclk; + struct notifier_block clk_nb; +}; + +extern const struct clk_ops clk_regmap_mux_div_ops; +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div); + +#endif