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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:43 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 01/14] ARM: dts: sunxi: h3/h5: Fix simple-bus unit address format error Date: Tue, 26 Sep 2017 09:22:21 +0200 Message-Id: <20170926072234.27481-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 74 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 37 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index a8e9b8f378ba..b37ed3461229 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -91,7 +91,7 @@ reg = <0x01c00000 0x1000>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; interrupts = ; @@ -100,7 +100,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c0f000 0x1000>; resets = <&ccu RST_BUS_MMC0>; @@ -111,7 +111,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c10000 0x1000>; resets = <&ccu RST_BUS_MMC1>; @@ -122,7 +122,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { /* compatible and clocks are in per SoC .dtsi file */ reg = <0x01c11000 0x1000>; resets = <&ccu RST_BUS_MMC2>; @@ -133,7 +133,7 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; clocks = <&ccu CLK_BUS_OTG>; @@ -158,7 +158,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, <0x01c1a800 0x4>, @@ -190,7 +190,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = ; @@ -199,7 +199,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = ; @@ -209,7 +209,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = ; @@ -220,7 +220,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = ; @@ -232,7 +232,7 @@ status = "disabled"; }; - ehci2: usb@01c1c000 { + ehci2: usb@1c1c000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = ; @@ -243,7 +243,7 @@ status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = ; @@ -255,7 +255,7 @@ status = "disabled"; }; - ehci3: usb@01c1d000 { + ehci3: usb@1c1d000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1d000 0x100>; interrupts = ; @@ -266,7 +266,7 @@ status = "disabled"; }; - ohci3: usb@01c1d400 { + ohci3: usb@1c1d400 { compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; reg = <0x01c1d400 0x100>; interrupts = ; @@ -278,7 +278,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -287,7 +287,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20800 0x400>; interrupts = , @@ -400,7 +400,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = , @@ -453,7 +453,7 @@ }; }; - spi0: spi@01c68000 { + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = ; @@ -469,7 +469,7 @@ #size-cells = <0>; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c69000 0x1000>; interrupts = ; @@ -485,13 +485,13 @@ #size-cells = <0>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = ; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-spdif"; reg = <0x01c21000 0x400>; @@ -504,7 +504,7 @@ status = "disabled"; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun8i-h3-pwm"; reg = <0x01c21400 0x8>; clocks = <&osc24M>; @@ -512,7 +512,7 @@ status = "disabled"; }; - i2s0: i2s@01c22000 { + i2s0: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-i2s"; reg = <0x01c22000 0x400>; @@ -525,7 +525,7 @@ status = "disabled"; }; - i2s1: i2s@01c22400 { + i2s1: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-i2s"; reg = <0x01c22400 0x400>; @@ -538,7 +538,7 @@ status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-codec"; reg = <0x01c22c00 0x400>; @@ -552,7 +552,7 @@ status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = ; @@ -565,7 +565,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = ; @@ -578,7 +578,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = ; @@ -591,7 +591,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = ; @@ -604,7 +604,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; @@ -617,7 +617,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; @@ -630,7 +630,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; @@ -643,7 +643,7 @@ #size-cells = <0>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -654,7 +654,7 @@ interrupts = ; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = , @@ -671,12 +671,12 @@ #reset-cells = <1>; }; - codec_analog: codec-analog@01f015c0 { + codec_analog: codec-analog@1f015c0 { compatible = "allwinner,sun8i-h3-codec-analog"; reg = <0x01f015c0 0x4>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; @@ -686,7 +686,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; From patchwork Tue Sep 26 07:22:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114244 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3517230qgf; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:44 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 02/14] ARM: dts: sunxi: h3/h5: Fix i2c2 register address Date: Tue, 26 Sep 2017 09:22:22 +0200 Message-Id: <20170926072234.27481-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The unit address and register address does not match. This patch fix the register address with the good one. Acked-by: Maxime Ripard Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index b37ed3461229..289f2cd06dfe 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -632,7 +632,7 @@ i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; + reg = <0x01c2b400 0x400>; interrupts = ; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; From patchwork Tue Sep 26 07:22:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114241 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3516723qgf; Tue, 26 Sep 2017 00:27:50 -0700 (PDT) X-Received: by 10.98.76.70 with SMTP id z67mr10074739pfa.78.1506410870149; Tue, 26 Sep 2017 00:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410870; cv=none; d=google.com; s=arc-20160816; b=x9JTwlrL57TzjcAiz4ZtA8Hk8drp8JmikAtJ03TzwVDtgC1tHVKsKtD4lc4yAvfbJY mTyucD3sg9EXm80ikmc6F+lexeaHj0coglPSIKWphsEjoekjtPrcMl8vzHfyd91Rerrs d5vtLCjGM5H2gA4kY2/WEz8yt8lPrCK5192MKvdGcW1JQlyRTgnsObPmS3+DFa1lYm7b ixB8YkgYvr8KGIDnV5EeShL9bJJFngKL4NS1faIjKDlEu99Y+pS3eUiE//e63KO4Wk3K JS/CljqmgV54JSsuXQS3wYeonDpK2rQOKk7TRILAJFMO5K1XPd919oah6SqSU4NjuEWM W2og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=qjMLmQdbHkim8wq4DE6HGRm/5urGJfM/6ID3Ld052+s=; b=m8sFieYF855QVn2DBQE37abpWfQTZUxzzXhF3uhLRQ+FHbPZF8X8ueDVleBkVZzBmm jticgpJ1iPU7lUAOnsiUA8RRPt2wGF1767V6tLUIhRdi3v8C7ISmBvphm/jnjL9IWcBN lqhmcNcut07edOEbA89WSia0KOg1VZIh5S0C5j5eKPp3+eBIZD2loAHJsF3u/YbKVmsq 68tW+9YUusZ18rWiKcyjbe7Sto0d70K2dhWW1wvnoRQMNDqLrorjcGkRN4gQdpUTomHq i9mmBmRabOMj1muqUMAeQMjOeOgRCU5ESYGse5LKUXIkqs9OmLzgU21IXcsfHrRBP+mk +ZnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Dcuqs5Mx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:45 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 03/14] ARM: dts: sunxi: h3/h5: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:23 +0200 Message-Id: <20170926072234.27481-4-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 289f2cd06dfe..2e4bae988acd 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -322,7 +322,7 @@ function = "i2c2"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins_a: mmc0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -330,13 +330,13 @@ bias-pull-up; }; - mmc0_cd_pin: mmc0_cd_pin@0 { + mmc0_cd_pin: mmc0_cd_pin { pins = "PF6"; function = "gpio_in"; bias-pull-up; }; - mmc1_pins_a: mmc1@0 { + mmc1_pins_a: mmc1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -354,7 +354,7 @@ bias-pull-up; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pins_a: spdif { pins = "PA17"; function = "spdif"; }; @@ -369,7 +369,7 @@ function = "spi1"; }; - uart0_pins_a: uart0@0 { + uart0_pins_a: uart0 { pins = "PA4", "PA5"; function = "uart0"; }; @@ -697,7 +697,7 @@ interrupt-controller; #interrupt-cells = <3>; - ir_pins_a: ir@0 { + ir_pins_a: ir { pins = "PL11"; function = "s_cir_rx"; }; From patchwork Tue Sep 26 07:22:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114233 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3514552qgf; Tue, 26 Sep 2017 00:24:57 -0700 (PDT) X-Received: by 10.99.171.9 with SMTP id p9mr10420534pgf.30.1506410697132; Tue, 26 Sep 2017 00:24:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410697; cv=none; d=google.com; s=arc-20160816; b=akHbxabkPZgtbgAhZVGTKH4gzWm5Fj34VsHbrfv3Qm6LNk4Nts86xYL+O7zwqpV/gO GGhHE7eBtSWEtbTWEpxkwN1vuXUzzJ5VI7Xwwd9lxs8KIjw7KCorFzORaXth/gEOdYHa LovyndVJY8keM4GUlgj3V9SH853xXL+HC4lpvCcjb3R5mrzN/l5MqRpRutkWjm77pPN6 TYxibV2k9+4Uw1R+A6fbR0l2GdPLMAsTsSTVr953duf8VyeeOPvC8YO2AuySB6NzX0s3 bLPnSFg/NJ4ltUPmlKiqYFoOp8amQTimwYlBQPKQ9a9w80rwS4e9TdR1nzUQYZRnDNQ7 JAAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=jHgnvI82fhLGBeri8aBjg9ab73rfBCO0P8omXzvbfak=; b=A4hce3oORQ3KKp8+Ote+brsQQnupNGtXEi96XGqt9kKbxPAgc8GQWtKX5BWjMt51Rz wuQpy0077wTW0WQVBGxzjnHdqs5epOSOs05LgJSd/PysbIoUMr+YFIhS8Ht2TPPIYxag 2oN/klz+zoC8wkqpsfKF9A6SsVTdeDvXfxuwjzW1S2qkPZU8Oe81F30Icc/ZSyWWFhxw h2sJBEE8E5av1S11iXt3148BnjnhqsjKw+dBoXS7uFIeIx/3Mvia1u1bFNngYisGN6Q/ tnh473CSGLcngNru59H7fBRTbGjZWsmSSSxCXAf3s9ILhK52qS5lFQcfHYDduorlGLHL FH3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=SGE7e3zZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:46 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 04/14] ARM: dts: nanopi: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:24 +0200 Message-Id: <20170926072234.27481-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index c6decee41a27..7646e331bd29 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -81,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sw_r_npi>; - k1@0 { + k1 { label = "k1"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -108,19 +108,19 @@ }; &pio { - leds_npi: led_pins@0 { + leds_npi: led_pins { pins = "PA10"; function = "gpio_out"; }; }; &r_pio { - leds_r_npi: led_pins@0 { + leds_r_npi: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_npi: key_pins@0 { + sw_r_npi: key_pins { pins = "PL3"; function = "gpio_in"; }; From patchwork Tue Sep 26 07:22:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114243 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3517000qgf; Tue, 26 Sep 2017 00:28:12 -0700 (PDT) X-Received: by 10.84.216.78 with SMTP id f14mr9904186plj.394.1506410892182; Tue, 26 Sep 2017 00:28:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410892; cv=none; d=google.com; s=arc-20160816; b=VNkcKMgSVjyssOT5D87W05b97ep+VEGfVaaW290r0y6l2nhMr5mG5rMWl7df0s4zH1 ohoaasg++cwLuQD1PgLAGF205OA3yJjxUuuTl+YidXfZpJN9kDNhwmgGYPZzPywvI6vI LhbaJBr06UDw+ZYprNHHTHdIcxqZp1qrviEAB6gvb2q3GcOdUdStqAupLF3UVW0+4Kmx P3Szr3JZKsM0Gv87/cojJgUMSq3gS/4lMBTgbm/kFtwRLCgj0DYsyDPk4H33gHbiFUEG 40B6jWh3AdkbnDWdj0pHqh75WEpTaLE+dJb6QxSaZI07EOru2O9Mr6ByyI4OUUqKu83g k4RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=XTKWzNyzlr+ubbFU2nk9Rx8/t70R3/PDTUKswdbSsoQ=; b=O+T7/P55lHheI1gupi8n2YdQr8iTFCE7/g5mwnqs6VvGcFv/MxCEBrkSycbp3OK2MB 6A2jtWqo7b76m4ZDuPLDFBWZnSOp4vv4q7D8gzciU8arlW+sejNqgTbxyLgsGkGb2jgS AcyOoecbhfjyGcrLmrYAtr4CObHIH7gEeINg1CfMDG7IPwHn+qKAEg02Y3BTAYoIBPOC 4l2lq0S/ZJdKr3L+fk/FeuCWBQZAM50APnCutjYBHLkSdBearZdQqBx0sNACP1PXwb/L keqUcR2uQqXtt7LGecVuZRsffZbxCXl9MbJPMSy+153f4nzj745gDuxylpj7bPWr6am5 1l6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=USP2TL+J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:49 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 06/14] ARM: dts: sun8i: orangepi-lite: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:26 +0200 Message-Id: <20170926072234.27481-7-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 9b47a0def740..a70a1daf4e2c 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -141,19 +141,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; From patchwork Tue Sep 26 07:22:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114242 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3516743qgf; Tue, 26 Sep 2017 00:27:52 -0700 (PDT) X-Received: by 10.84.171.193 with SMTP id l59mr9724860plb.133.1506410872131; Tue, 26 Sep 2017 00:27:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410872; cv=none; d=google.com; s=arc-20160816; b=wuTD3xraiNGZyo4TMJplHTTIoa8WqfFw1yvcPzynUdkztt5do7RCh7jXf+fYT20j7n mc6l/o8l6fdsqOlRA+qZS7uczaINZNLRr4tOEVDh6lYBA9PaPh7hp1fAb4zvgsRoyJj3 jVzhSGLAqcWatPzMYcedbNA76ZfMfeNhUbCKnSsxrK2V2y1t5qhqd9eLIeV67xxi4NDC B9pG211LnfK3VxVAeZ4AuCHkXP4tuDTxGE8XZV9S1DjmEx/R3yaStjUy606QJ5qRfZI0 k3l85by+0uZtgRCN8RTgrxCep/RL1yYbULAjTxcBKBFM9wvkgMMfGB6bihmLErE2Z/Hg tDbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=X3DBFk8vEhH4RsalATcLm7j4hRqspjRM0h0t1l3vbv4=; b=a+qTnH2wNwgaxIbJhOrZcc/XTB2S09swFaFuUPmMnTdd0O0Kf1DVx6tPVIJt6pTY7c TAU7gqdUpMkYqAJilNYBpPOgalzx/I2/mbo330uTmSfwltmUdIzRtWf41VcPB+FyPwlq h3h3V5ZFgHHZU2JKGdLOOz1Msq91bGd6jPpanoNhF+WU/D25l7WVgv8ClNKg/RjKeeE7 gu8nyb3dRE81lGcU6N7vvEH2ul/yGSr4hfVRkbb73ozUjb/gPe4h2HvrPKpIqAuQeczd Pyqu0zzwIPO7CqK8bAxyu8CH8Bf7moYtPeEyW7GPGadk8IArb79xXQrJXWDXXYFMqM3U yeAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UhSMEjxG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:50 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 07/14] ARM: dts: sun8i: orangepi one: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:27 +0200 Message-Id: <20170926072234.27481-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 6880268e8b87..82e5d28cd698 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -124,19 +124,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; From patchwork Tue Sep 26 07:22:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114240 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3516038qgf; Tue, 26 Sep 2017 00:26:58 -0700 (PDT) X-Received: by 10.84.238.197 with SMTP id l5mr9504564pln.298.1506410818572; Tue, 26 Sep 2017 00:26:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410818; cv=none; d=google.com; s=arc-20160816; b=PbeTIPm0e24W6Rm640e2GkWWwKcffz7ylL+GJ7i6x45FCy8KWDefMHTg9BkH4Jx5vc u73lr5wEJnqWCw77pr8alTATtBIuTqJlvtHitpn0kmCKOpeLFixYpRUd8m+rt+/ZWspu BzyJjSREmnfdBpb9yt/8AM949ruhwR93jPwiN4pYZW8y15QM7lzYIllwx2UPCjr6r4En 6V0IBsMhdnQxLKzaCoEzlLqPmkhaSC4Cw5wl5w/2AskqxefEkdj2j5JEdkREGwiiB4lo 8jv+3TAVMXznP4vGfSvJ2yRzrRsdSy6BWnPxB60MyEe7i4c7WyOiLrsKBLjWLRwsbXip rS/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=X31kT/VlqJ2/dHrZ4FcxzGFxWC8N7RBm8LaGdpavESg=; b=sec8ynwHjkhoPO2V+Sx/GWoOACl+sLZ1/hUHnw0wtJnzZm7nQ0SI5GJ9yixqO8Ae9c lp2pvv7vyVdaJbA6W6++3B2hb6DDioM3MShVInyW7AHx7WN+LtnCrOQB4L3y/Ug4/Wf9 vaguyT0HutPy4R5C//PPPqFWRLKyTgQ+02FP/JwujSjwkw1F6hjlfp/5vJt/w2ILf2jv qZb9hyH7xTi5NueDbPZZR4fEIDcoDtXvNEUdiZBgOwTZDa7yLE6CkI0u20mHi2qyyljD +r06zCXxsKsedoDGRPmeVUIi5mSKbTp73jqKytg9xb+zJk5opOOeBw1X4b7oGp8tcqoz 8jag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BMI0d79W; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:51 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 08/14] ARM: dts: sun8i: orangepipc: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:28 +0200 Message-Id: <20170926072234.27481-9-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index f5f0f15a2088..6d98bcfbe877 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -158,19 +158,19 @@ }; &pio { - leds_opc: led_pins@0 { + leds_opc: led_pins { pins = "PA15"; function = "gpio_out"; }; }; &r_pio { - leds_r_opc: led_pins@0 { + leds_r_opc: led_pins { pins = "PL10"; function = "gpio_out"; }; - sw_r_opc: key_pins@0 { + sw_r_opc: key_pins { pins = "PL3"; function = "gpio_in"; }; From patchwork Tue Sep 26 07:22:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114238 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3515632qgf; Tue, 26 Sep 2017 00:26:23 -0700 (PDT) X-Received: by 10.98.34.15 with SMTP id i15mr10036201pfi.257.1506410783090; Tue, 26 Sep 2017 00:26:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410783; cv=none; d=google.com; s=arc-20160816; b=N97+txaNCJDc0ardDUs+C+Yi3QAAtoDKxpCi+dIQtrXfG/e5jZzPMhb6QZfrkCCNmp zN+sEQIkSy9AqehF/KkDTlywvW652Cf0L9SCXI0yoe1ypYEBK9eAhLPBYRljKRybJLLC G5GjbMHTAvse6VywzNlqxk+B4jY2ymt7uzL+2TNiVgoMXGNFJaLf7/sg9S7eiDtvV8ky TitFktUxQ+qIxlBuGVXDdip4Ya4A/HDtSwEhC4HLx2Zfl91T0FsRKt+s9dQ6AJK3/1GJ 63wHEgtRraN44zbDttDBUgKWr/aHSkO9jhfjtQTZVqAGYUNZOwjPxC9e1e5+9uKu9CaS EJ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=hrcUYcEX+8n60Ey7j1OVpLjb1ledK25Lreu2ToewSiY=; b=d3evpGLsi14Xz23YLF0o2pX3ZHFB3CUOH+EVFNgh5axRNXuUdBqDa9OP0AvBHw3tam CTZtqQ+Wg1WSgimq3//a0EV84nBkLwh7R9gnU/VR5CYQKvj4fOk9SbN+TWjrEk8GHECk oCKKL2HoHFc+bTAMae/0GMAlcbHJBIx7WQjVrlXwvn1X9RpY9OuuZ0Ft+0iFl7vVSvqc UgB+Kv7pruNXdXKibzLUbq1IrA8ZAUdgIX6e6CDKgDZOuZNn94Q7zStgEtIml5MY17w4 bjQ8i3E56M9cLXp8yH66Kpginlci45BgWBLkLhpc9had6v65LdCAZTXt1ToIB9Mvmu4n C8zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=uY28bFZb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:52 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 09/14] ARM: dts: sun8i: orangepi-plus: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:29 +0200 Message-Id: <20170926072234.27481-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 331ed683ac62..119732505844 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -114,7 +114,7 @@ }; &pio { - usb3_vbus_pin_a: usb3_vbus_pin@0 { + usb3_vbus_pin_a: usb3_vbus_pin { pins = "PG11"; function = "gpio_out"; }; From patchwork Tue Sep 26 07:22:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114239 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3515770qgf; Tue, 26 Sep 2017 00:26:34 -0700 (PDT) X-Received: by 10.99.126.84 with SMTP id o20mr10318766pgn.239.1506410794234; Tue, 26 Sep 2017 00:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410794; cv=none; d=google.com; s=arc-20160816; b=sJwNrMRLj+SAv9T7ewJZ5aJbrLIk4klO8BmTNJ3M4ltkXyLQsFsw2aJWwI1ftp5Pww cels/ewcVv9zWbDq8qBdkYBEjIDxuwe7IwHGtXzuE0+XD1RSzKjb5oNvE68Qs74vhcpq mP9BAzzR1a6FKmvdz7rh6rXI0M+Lh0EJ5UufmOvVemLaTopea4GiYbM2nmCzX2y+rEw9 7g4itlP0/ZqM7Cl3KiMLeX8FNg8a7DqfZbt/uhH6muzzUxwfzhLVOlll6uQHNoNc0TG3 y24KX1EwXlvAYsqJ9G1B17024cmdBALZqusai3b9aPXqxa2VjZKkiRr5qhU84b4rb8qT cIjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mj5//RXB6t/Oma5YAbZ4JJeysSzGcxnMQU+R1V07vaM=; b=nYcvCRx68NpZ1jtZ/si431vMf3dw/KDUMzbUKsHqH8Mtv3r1Q1P01txebDcuE3VsK+ k/HS++oYSene3lb8CpZGHO/eY5ivg4rAxmRN71kU8+Lu9wL6MBkoMIEzh+tF3L+oSDmR 7rDZ0K4W6l1pypC+0U9BiJj4KKTK0yAm62Ydw2NoW0naS33bSdbEIW10DewodSbU3khp BP2xDzbDMPzfPnR3g5HgaV3+eiqk0/UbaVlEgWnZBDeZXLSVYMEcgylOZx7Avv6KHaXi C+puKfGMK6tn+aRD5NJJaNo9fyOdjWzNPRBlzYM17+E4rci3xV5wC7gbUs4pN7nLH+3h siIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=dsh19poH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:53 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 10/14] arm64: allwinner: a64: Fix simple-bus unit address format error Date: Tue, 26 Sep 2017 09:22:30 +0200 Message-Id: <20170926072234.27481-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index e30476f05802..662e8b7981b5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -190,7 +190,7 @@ status = "disabled"; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -203,7 +203,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun50i-a64-usb-phy"; reg = <0x01c19400 0x14>, <0x01c1a800 0x4>, @@ -223,7 +223,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = ; @@ -235,7 +235,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = ; @@ -245,7 +245,7 @@ status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = ; @@ -259,7 +259,7 @@ status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = ; @@ -271,7 +271,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -472,7 +472,7 @@ }; - spi0: spi@01c68000 { + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = ; @@ -487,7 +487,7 @@ #size-cells = <0>; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c69000 0x1000>; interrupts = ; @@ -560,7 +560,7 @@ #reset-cells = <1>; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; From patchwork Tue Sep 26 07:22:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114237 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3515426qgf; Tue, 26 Sep 2017 00:26:07 -0700 (PDT) X-Received: by 10.98.178.133 with SMTP id z5mr10043872pfl.312.1506410766898; Tue, 26 Sep 2017 00:26:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410766; cv=none; d=google.com; s=arc-20160816; b=qXyifVQD24D5juSzkWJ+TdowrgkM8dTi6kjc+ir7sREf8VTgj7t2SdjmOBcx7cRDfQ J/scEbyAv2Yc8qZwzFZCM/ghGzwZtvYyStIPX2bTaBWWqgy2iK/dyLaycmkx5JwcuZev QmEstpFDbh//eqQFo8wq28dZQOVBWEK4QsDdpPRzZN6HUWsOMYevXvi6GrlWpa9M7UuX k8ECemTIL3H5yFao0Y5gTJ+37QZoxQNvYYpWdnfZ9s0s6Vc2Mn5it6ilRwwP/4QclkWy yAqkAWhKAsnvfuhEVc2fpBLMSViEhf9Kzn6xykENbDG5jU/rQ6WCB1ziI5sPFCKiYuai zdnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=LVDlycFfJ7n2CLrooVO3hPpvzTIPdprtrhkbHYghLMg=; b=oh2zhxbBaya9AakVQwDEW79Nm0dNhnN6PHCacJPgJHgFJRF+ceqEVV30cahN12FLf6 2SpwqfmtIGtUm7P+z6VjIPb1hlckI8JVF7cQEMJh6P8dsiAg3HfTDm6+1dAV1UPQhXTz P9OP2P0wBgLDX39gs57R7+qAZwoF2UuOWGrCVvYDk7ztKO5e9Czq5bXdUcFgOeuFu0il s9kg6+4bE71xOoghhLv+3IhpNbJCb4k8upMeeSCv5wApcNtOPkbJ/+2WuzYhHIZn7Yjb 3Y3eLvRZW6arzEWw1/IJRYNYdMq1ZC97RQTdmik8xhAu95JgcT6JUJXjL1Psb/94oxbK yWcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=YDXAbMwR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:54 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 11/14] arm64: allwinner: a64: Fix node with unit name and no reg property Date: Tue, 26 Sep 2017 09:22:31 +0200 Message-Id: <20170926072234.27481-12-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 662e8b7981b5..b02a8476b0c8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -347,7 +347,7 @@ function = "spi1"; }; - uart0_pins_a: uart0@0 { + uart0_pins_a: uart0 { pins = "PB8", "PB9"; function = "uart0"; }; @@ -571,7 +571,7 @@ interrupt-controller; #interrupt-cells = <3>; - r_rsb_pins: rsb@0 { + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb"; }; From patchwork Tue Sep 26 07:22:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114236 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3515195qgf; Tue, 26 Sep 2017 00:25:49 -0700 (PDT) X-Received: by 10.159.244.18 with SMTP id x18mr9814224plr.117.1506410749851; Tue, 26 Sep 2017 00:25:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506410749; cv=none; d=google.com; s=arc-20160816; b=N+I9UgU+CpMBW0cyPMYJXmS+yyWeUPCOiERcjpOxRYCVyREk6KxD4Yc4a3iedbyxWW PF5NQUo9CeZ9fxTKVnkhwVrdxSRg+mfS2OF9/7jB/5RPlzER5PnvUQZH6AqFZzKf2vjk CQ7H/h4PRmYH4eQbi5Qsvafnfi9u+Do4HExxEfpKFT5tlmYtp0b0I+rYDJ/91BaWffcX zMvq58IaRXDkre6j8d1aZ73z86shcDVuFQx5382P7/P+4ANN/056ALebNMXmMFep7rVF QkcfmF7VGsXSOWKKCqe10OBgyFYYI9U/domi4KUVsM3x+GFGGY2MH/N49sJlPA8PTVpA AJog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=S2vXNrGrHlzqQdBLBYRzoHsnXl4nY5k1FfccyzE01V8=; b=CyS1n+oaxjOYYmesjogEoCcAEAH1Ihk9F7+9zkE2o3hTAFI7HaTR3JSerotbl0dktq o655sagkdvsN2O1O4+VfGQKQ0U7XdnXQ6Nc3EyHlqM0ZU+/Pl5oQvAtQXhfBtGpAb+md mEJRMSvO2253JwiswtH5rjovacBamn+aeXWVXJTLnlnRN/HuAwE+tSRXFG6UvMt9ok19 BURwBlXRHJh06Zu3IZYmhXsjRXnZdao+urjHyr5Aax9+fBUCssEQrGKWUikv//XwqxyT JoAgc/8zzVTfDHF0X4gYxuxlNYbA2+PSp+VUz9fbYC0S+FGOwKx+ZVaGF456J59tN3aP Fz5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=JIn5Ph7u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 204sm1824998wml.10.2017.09.26.00.24.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Sep 2017 00:24:57 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v3 14/14] ARM: dts: sun8i: fix pin name Date: Tue, 26 Sep 2017 09:22:34 +0200 Message-Id: <20170926072234.27481-15-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170926072234.27481-1-clabbe.montjoie@gmail.com> References: <20170926072234.27481-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All pinmux nodes should have the suffix "_pins" or "_pin". In the case where there are multiple choices, the node name should convey what or which pingroup the choice is. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 8 ++++---- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 8 ++++---- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 10 +++++----- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 4 ++-- arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 4 ++-- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 4 ++-- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++---- arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 8 ++++---- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4 ++-- arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 6 +++--- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +++++----- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 6 +++--- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 4 ++-- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 6 +++--- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 8 ++++---- .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 4 ++-- 18 files changed, 53 insertions(+), 53 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 6713d0f2b3f4..8b1e2dace4da 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -113,7 +113,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pf_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -123,7 +123,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc_wifi>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -139,7 +139,7 @@ }; }; -&mmc1_pins_a { +&mmc1_pins { bias-pull-up; }; @@ -166,7 +166,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index cc20d676a642..575510a5fd01 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -125,7 +125,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; @@ -138,7 +138,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -148,7 +148,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -194,7 +194,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 10da56e86ab8..2631a3619dc4 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -110,13 +110,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -126,7 +126,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; @@ -166,13 +166,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 818f9bf5df66..7beb10c6940c 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -91,7 +91,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; @@ -104,7 +104,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts index 3a2ccdb28afd..08f3577c9b0a 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -57,7 +57,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts index 03ff6f8b93ff..a9d4d0b01439 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts @@ -76,7 +76,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -86,7 +86,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index 7646e331bd29..ca63c383d4ed 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -98,7 +98,7 @@ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; cd-inverted; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; status = "okay"; vmmc-supply = <®_vcc3v3>; }; @@ -128,7 +128,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index b20be95b49d5..6845fbcc306b 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -127,13 +127,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -143,7 +143,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -190,7 +190,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index a70a1daf4e2c..cebf0f0c84c4 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -101,13 +101,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -117,7 +117,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; @@ -161,7 +161,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 82e5d28cd698..cf6d273992f7 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -107,7 +107,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -149,7 +149,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index a10281b455f5..2307f750293a 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -60,7 +60,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 6d98bcfbe877..76e8fbd22c38 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -127,13 +127,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -183,7 +183,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 2e4bae988acd..f9d6411f4b39 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -322,7 +322,7 @@ function = "i2c2"; }; - mmc0_pins_a: mmc0 { + mmc0_pf_pins: mmc0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -336,7 +336,7 @@ bias-pull-up; }; - mmc1_pins_a: mmc1 { + mmc1_pins: mmc1 { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -354,7 +354,7 @@ bias-pull-up; }; - spdif_tx_pins_a: spdif { + spdif_pin: spdif { pins = "PA17"; function = "spdif"; }; @@ -369,7 +369,7 @@ function = "spi1"; }; - uart0_pins_a: uart0 { + uart0_pb_pins: uart0 { pins = "PA4", "PA5"; function = "uart0"; }; @@ -697,7 +697,7 @@ interrupt-controller; #interrupt-cells = <3>; - ir_pins_a: ir { + ir_pin: ir { pins = "PL11"; function = "s_cir_rx"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 7c028af58f47..3b242136306c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -135,7 +135,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ @@ -144,7 +144,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -178,7 +178,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 968908761194..eafa116b1c18 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -127,7 +127,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ @@ -144,7 +144,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index a8296feee884..3e028b18d703 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -148,7 +148,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; @@ -161,7 +161,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ @@ -186,7 +186,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index d906b302cbcd..bb9554fe7389 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -155,7 +155,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&ir_pin>; status = "okay"; }; @@ -168,7 +168,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ @@ -177,7 +177,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -203,7 +203,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts index b6b7a561df8c..71c9b05e1740 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -68,7 +68,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pf_pins>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; @@ -87,6 +87,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; };