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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm6211950pgu.51.2020.07.16.17.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 17:16:22 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org, John Stultz , Vinod Koul Subject: [PATCH v2 1/5] iommu/arm-smmu: Make all valid stream mappings BYPASS Date: Thu, 16 Jul 2020 17:16:15 -0700 Message-Id: <20200717001619.325317-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717001619.325317-1-bjorn.andersson@linaro.org> References: <20200717001619.325317-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Turn all stream mappings marked as valid into BYPASS. This allows the platform specific implementation to configure stream mappings to match the boot loader's configuration for e.g. display to continue to function through the reset of the SMMU. Tested-by: John Stultz Tested-by: Vinod Koul Suggested-by: Robin Murphy Signed-off-by: Bjorn Andersson --- Changes since v1: - Mark arm_smmu_setup_identity() static - Picked up tested-by tags drivers/iommu/arm-smmu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705..fb85e716ae9a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1924,6 +1924,22 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static int arm_smmu_setup_identity(struct arm_smmu_device *smmu) +{ + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + if (smmu->smrs[i].valid) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count++; + } + } + + return 0; +} + struct arm_smmu_match_data { enum arm_smmu_arch_version version; enum arm_smmu_implementation model; @@ -2181,6 +2197,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + err = arm_smmu_setup_identity(smmu); + if (err) + return err; + if (smmu->version == ARM_SMMU_V2) { if (smmu->num_context_banks > smmu->num_context_irqs) { dev_err(dev, From patchwork Fri Jul 17 00:16:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235662 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1243367ilg; Thu, 16 Jul 2020 17:16:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzR7hkDOe61yhsbj+jZcvCOPdbX8sWfouj8Ly0O5P1ECuR6jyvu0WyeN0WZ570NsDIX9vNm X-Received: by 2002:a17:906:1102:: with SMTP id h2mr6015873eja.356.1594945004352; Thu, 16 Jul 2020 17:16:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594945004; cv=none; d=google.com; s=arc-20160816; b=DSPJ6gYJtjTrjb3lorAsnz5fDK0D5yNtEIjWhs7gRb75pgwQB5o2/nfmrNK3s0q2hA Yg6ct/0qlBDVui0Znd/CsAvNIRg5gOvnZas9bFsS0uBsVTL1mA+2pp9qKhfDqS9CngWx lTo99Zj18dIn8NYiuIEoXn/B/s+pXHrQ3EwDGIXVjgI+U6NtwK5dosMChI+5mdJtlDcK yRARwzQKCac0sKBASu2gyJYI7nKQr5DREmNOFBq3ngRlSgVnxemBSNjQPRNuOX2PRKzZ fAS5SrHRNpohfS5vB9x0rQKYD4aN+aw1otDYagrY4dPymyhOVNkxKeU0701zrhkliO75 eglw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jYsMERNFzcWVzzWKbxXkh/fS5B+pLfajmEgKGDyW4yE=; b=wP+cl1OPH42fYY856nZo/45B2pCozGms7qZogkVxaK/Yy/IJ7ureZO4hp2eSiCYGZW +I8URJuFig5P9ogZ/KGvNeEkzPFELzaoAngZ8vYG+9Dx2NP1MPGO5cTQJnFjKmyzjZPo 0vSdMWVXcg+u+YlceMOLn92ftGgG1TGprf/j6EcpSUyf30Yhk2T5tv8dqbws4WcZsf0R /KukOLIqlD+jOPbUMEWrrU4ikJQpfc4IVXKFmbKIsNjeCkPypKaQeoT2k+idLX3y3d0k IHNDQCY1pIieS8cCLFL0lgj/8KQsjx4F6b/cg/8rPpUf0hLgG3+32IqiwWCg7WikFoN5 Id2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ACUa/dg0"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm6211950pgu.51.2020.07.16.17.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 17:16:24 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org, John Stultz , Vinod Koul Subject: [PATCH v2 2/5] iommu/arm-smmu: Emulate bypass by using context banks Date: Thu, 16 Jul 2020 17:16:16 -0700 Message-Id: <20200717001619.325317-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717001619.325317-1-bjorn.andersson@linaro.org> References: <20200717001619.325317-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some firmware found on various Qualcomm platforms traps writes to S2CR of type BYPASS and writes FAULT into the register. This prevents us from marking the streams for the display controller as BYPASS to allow continued scanout of the screen through the initialization of the ARM SMMU. This adds a Qualcomm specific cfg_probe function, which probes the behavior of the S2CR registers and if found faulty enables the related quirk. Based on this quirk context banks are allocated for IDENTITY domains as well, but with ARM_SMMU_SCTLR_M omitted. The result is valid stream mappings, without translation. Tested-by: John Stultz Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Picked up tested-by drivers/iommu/arm-smmu-qcom.c | 21 +++++++++++++++++++++ drivers/iommu/arm-smmu.c | 14 ++++++++++++-- drivers/iommu/arm-smmu.h | 3 +++ 3 files changed, 36 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index be4318044f96..d95a5ee8c83c 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -23,6 +23,26 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { } }; +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) +{ + unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 reg; + + /* + * With some firmware writes to S2CR of type FAULT are ignored, and + * writing BYPASS will end up as FAULT in the register. Perform a write + * to S2CR to detect if this is the case with the current firmware. + */ + arm_smmu_gr0_write(smmu, last_s2cr, FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT)); + reg = arm_smmu_gr0_read(smmu, last_s2cr); + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + smmu->qcom_bypass_quirk = true; + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -61,6 +81,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index fb85e716ae9a..5d5fe6741ed4 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -654,7 +654,9 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) /* SCTLR */ reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | - ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; + ARM_SMMU_SCTLR_TRE; + if (cfg->m) + reg |= ARM_SMMU_SCTLR_M; if (stage1) reg |= ARM_SMMU_SCTLR_S1_ASIDPNE; if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, if (smmu_domain->smmu) goto out_unlock; - if (domain->type == IOMMU_DOMAIN_IDENTITY) { + /* + * Nothing to do for IDENTITY domains,unless disabled context banks are + * used to emulate bypass mappings on Qualcomm platforms. + */ + if (domain->type == IOMMU_DOMAIN_IDENTITY && !smmu->qcom_bypass_quirk) { smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; smmu_domain->smmu = smmu; goto out_unlock; @@ -826,6 +832,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, domain->geometry.aperture_end = (1UL << ias) - 1; domain->geometry.force_aperture = true; + /* Enable translation for non-identity context banks */ + if (domain->type != IOMMU_DOMAIN_IDENTITY) + cfg->m = true; + /* Initialise the context bank with our page table cfg */ arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); arm_smmu_write_context_bank(smmu, cfg->cbndx); diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..a71d193073e4 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -305,6 +305,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + bool qcom_bypass_quirk; }; enum arm_smmu_context_fmt { @@ -323,6 +325,7 @@ struct arm_smmu_cfg { }; enum arm_smmu_cbar_type cbar; enum arm_smmu_context_fmt fmt; + bool m; }; #define ARM_SMMU_INVALID_IRPTNDX 0xff From patchwork Fri Jul 17 00:16:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235659 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1243246ilg; Thu, 16 Jul 2020 17:16:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxF8SSTh95Ek4G5sG180GnxVmSmslpXqDYxsylo+lvzDtyQOi/r9eZDnjRXgn/dKAsMxMlP X-Received: by 2002:a17:906:7387:: with SMTP id f7mr5869907ejl.131.1594944990103; Thu, 16 Jul 2020 17:16:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594944990; cv=none; d=google.com; s=arc-20160816; b=pILgBCqF09CE8JsuJDpPUilnWjUS/Zrmf9WpuyMTPa/lsinwYVku7v/3FIENYk5A2H Lv3ZIsO38/lU9PBuKwqcxVtDSOaUtc1S6LGzfGC2tNE/2crg62D/uxYo8loQlV/JxzJN Ohrva39m7+sDmW12XRODrezvlLglk8A5uP1/Q/oWEaBpb6zG1RlXJlvdv2DO2psny+m8 o0cXSTGYuyIgzc9sg8shaqnCf1zxwPn6HNofcHaKXq6SW3WbI/Lc6O6VZF0QMOau8DNO qYm01jPQu27LG/bOboHc1hjhw4BvQYzunLRiAsUBLsMjuuct76iUXykYwVgwBd4z4bP+ ePcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uWqUMnqB20Yorh5LQCiLslCOOm0+DCqawJ+UCE1bquU=; b=mlxewNYxOTdVGICzXkJoWce8aAn0OLFIEn6V5rIuB1wBJG4PC0xI1+B7uo/2ee7RxU Y73FpmYM45v+vQsXSJGMXASNL7Xpq7F4yFwpLZIrRzp8AKVfmqrfLx2/ynu8ukXeUPrf wcZcZYaLmDtQ+T/hpjcnW39Jmk75WEcNoVCVCSeNStIU1rjfjlIJgkrBobHTwl2Sx/l3 TfA50ff2kngXCzVjHL/P0FpFu0lg4Un0x078ttlwDmGhEAkqB+LU5+as4uk4yJmfGTL3 Hf1pI9mN+EB8bkMTrhG0sk/NeZcBv2WmW0uDyXrMQ4bKx+45pXGIBkTOdOJJKgD0LNfV Kj3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HFN+J5la; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm6211950pgu.51.2020.07.16.17.16.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 17:16:25 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org, John Stultz , Vinod Koul Subject: [PATCH v2 3/5] iommu/arm-smmu: Move SMR and S2CR definitions to header file Date: Thu, 16 Jul 2020 17:16:17 -0700 Message-Id: <20200717001619.325317-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717001619.325317-1-bjorn.andersson@linaro.org> References: <20200717001619.325317-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Expose the SMR and S2CR structs in the header file, to allow platform specific implementations to populate/initialize the smrs and s2cr arrays. Tested-by: John Stultz Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Picked up tested-by drivers/iommu/arm-smmu.c | 14 -------------- drivers/iommu/arm-smmu.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 5d5fe6741ed4..08a650fe02e3 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -68,24 +68,10 @@ module_param(disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); -struct arm_smmu_s2cr { - struct iommu_group *group; - int count; - enum arm_smmu_s2cr_type type; - enum arm_smmu_s2cr_privcfg privcfg; - u8 cbndx; -}; - #define s2cr_init_val (struct arm_smmu_s2cr){ \ .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \ } -struct arm_smmu_smr { - u16 mask; - u16 id; - bool valid; -}; - struct arm_smmu_cb { u64 ttbr[2]; u32 tcr[2]; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index a71d193073e4..bcd160d01c53 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -251,6 +251,21 @@ enum arm_smmu_implementation { QCOM_SMMUV2, }; +struct arm_smmu_s2cr { + struct iommu_group *group; + int count; + enum arm_smmu_s2cr_type type; + enum arm_smmu_s2cr_privcfg privcfg; + u8 cbndx; +}; + +struct arm_smmu_smr { + u16 mask; + u16 id; + bool valid; + bool pinned; +}; + struct arm_smmu_device { struct device *dev; From patchwork Fri Jul 17 00:16:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235661 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1243332ilg; Thu, 16 Jul 2020 17:16:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy92j/dXpKjfZE832ejs40zpB9mkmjyQmSo649EeaZZ/pn/C5V2JW7nYxKaxoST1o7TmmYr X-Received: by 2002:aa7:dad6:: with SMTP id x22mr6635953eds.310.1594944999379; Thu, 16 Jul 2020 17:16:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594944999; cv=none; d=google.com; s=arc-20160816; b=CUYx1y9m6SAqVqxFsYYDBv4a/v5KJbDBVBlzmMEi8nuQsyFyw5nsFC/ijEq2hKbxY1 T1us0PAqUAKbrT3PvsQzHjgJKaKAfmRKgywsnM0yCXjvK/Nu/QKOYSQ3/bI831WxS7ze 8HIu27BLFGcS9Oy5wHfpgpAJVHxSkWzFC/CfPRNIoJxjPMIrKQScs3oOqPTICHXQ680J G49mzBxhx1F191hSXUUZUS2LsE63moC6J9oO+f4iPz7HH+dmJ0upLkzr2mEPni72tRwZ F1Ynqqfh/ihB5uhavIQ0cXKk9OQJSYSE4Po/y9aPxn3ZXIgRbwXK5yEbiz+kOpAtMPLr 627A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iuuJuMaKgUlLRcc6gFCZ7HFqvJc6qzprtp/8FUZq9U4=; b=QWy+JcKKL9LTb4EQBeU2s9TPUQE+mQG3heZdFRfDWIumVeWhSAv6xZVHjKNUislIaH pOtk0yvgTyYP7F4oa7q2vYU0+FT57L9mSEE1Ija0ARAvUnReO0Aw08Al2wLjuN699PiJ yhzRJeGzPwbWULlxyHbGA51howaC25/dQWYtLNWF8cVW/JORmxs12rq60v9bUufrJax4 pc/xb58QduM6hxZ+CU0r7PkfF8Cw6mB5arbKY3cMu0Re2Jp4qbbXMI4DXjhNi3xKdhNx xbcOgNroyF5bKN869Pbm+D4Zw20twRwn413FmbGaG5qUBFS6X88hIm5IlgAWrHakvW/X drPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oGrAw2FW; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm6211950pgu.51.2020.07.16.17.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 17:16:27 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org, John Stultz , Vinod Koul Subject: [PATCH v2 4/5] iommu/arm-smmu-qcom: Consistently initialize stream mappings Date: Thu, 16 Jul 2020 17:16:18 -0700 Message-Id: <20200717001619.325317-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717001619.325317-1-bjorn.andersson@linaro.org> References: <20200717001619.325317-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Firmware that traps writes to S2CR to translate BYPASS into FAULT also ignores writes of type FAULT. As such booting with "disable_bypass" set will result in all S2CR registers left as configured by the bootloader. This has been seen to result in indeterministic results, as these mappings might linger and reference context banks that Linux is reconfiguring. Use the fact that BYPASS writes result in FAULT type to force all stream mappings to FAULT. Tested-by: John Stultz Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Fixed subject spelling mistake - Picked up tested-by drivers/iommu/arm-smmu-qcom.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index d95a5ee8c83c..10eb024981d1 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -27,6 +27,7 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); u32 reg; + int i; /* * With some firmware writes to S2CR of type FAULT are ignored, and @@ -37,9 +38,24 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT)); reg = arm_smmu_gr0_read(smmu, last_s2cr); - if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { smmu->qcom_bypass_quirk = true; + /* + * With firmware ignoring writes of type FAULT, booting the + * Linux kernel with disable_bypass disabled (i.e. "enable + * bypass") the initialization during probe will leave mappings + * in an inconsistent state. Avoid this by configuring all + * S2CRs to BYPASS. + */ + for (i = 0; i < smmu->num_mapping_groups; i++) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count = 0; + } + } + return 0; } From patchwork Fri Jul 17 00:16:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 235660 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1243317ilg; Thu, 16 Jul 2020 17:16:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyG8sKsNZSMdGQswWclEIVPnfIwcpwO8CwCPTUgY0B4xSCnMx/Tr+3JtIu/IFp/IaMx+Lhz X-Received: by 2002:a17:906:e213:: with SMTP id gf19mr6071869ejb.433.1594944997504; Thu, 16 Jul 2020 17:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594944997; cv=none; d=google.com; s=arc-20160816; b=MSV3/7gD9MBcbR4MpOv7Q4aAk3TyO5DsF7xR5DwxTEgJsFVTRXvD1SKPs+roV2ifdg BJOjb23wl0AB7yBtBsnuxBqhvaQh5y5eX5X7q6eTi2PuSfQNQPN0s0if8RZ+xt8u+qjG rhnbe+b1gQMwRhBSUbllHOjh/52RUXrwtDWxakKds17Wnc1FyP1/DhUffj72Okc3SrRs C+xVqs+RwxNbpJ1dYNGGErXqERdZ3NloapT9GFKs2qwQx1TdmD77Hf2JOxjO+gt+hIIU 4nXEt66XFZebfpHiX/6DGwzQdChGVLhIttD/0Njib0+U0OCUUnVlqpD2nWjtUyQvPKeJ yjhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jlkntRV846aUEo1Gl28BULv9E1NJaLJ91w5u0IdGAqY=; b=QHwJioZxIBXbaDWa7TX+Ep6QHYk8CY350Dm7c5TAEurgQ3atJGLe0db22/aeR80waZ AfcWz/Q6imsR4I56r3zTFap+QydKcecwelJgvAAtDnI4j25oy7s9FzORFRSsaZFeH+Gc JqDIxGRL3ejl2l0OJjU0YOA2GAi3FfEzWo5keWRhs8ZELp9/BwXDBNBLd5uayvfBzZEf gxPjSXPB97U5JZiqABC3ftdaf42oTHzc5t5fpNRfTFU6IucnRlspWH1bfi1abm79Jtqu XDk5ROopd6DeWll6WbqChtpl+mMGbpDz4McwUK/cEJBOrp1XX/kHSn4qk4UbZIvC68Gm bKGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OiQXSDCW; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r7sm6211950pgu.51.2020.07.16.17.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 17:16:28 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org, John Stultz , Vinod Koul Subject: [PATCH v2 5/5] iommu/arm-smmu: Setup identity domain for boot mappings Date: Thu, 16 Jul 2020 17:16:19 -0700 Message-Id: <20200717001619.325317-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717001619.325317-1-bjorn.andersson@linaro.org> References: <20200717001619.325317-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With many Qualcomm platforms not having functional S2CR BYPASS a temporary IOMMU domain, without translation, needs to be allocated in order to allow these memory transactions. Unfortunately the boot loader uses the first few context banks, so rather than overwriting a active bank the last context bank is used and streams are diverted here during initialization. This also performs the readback of SMR registers for the Qualcomm platform, to trigger the mechanism. This is based on prior work by Thierry Reding and Laurentiu Tudor. Tested-by: John Stultz Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Rebased to avoid conflict - Picked up tested-by drivers/iommu/arm-smmu-qcom.c | 11 +++++ drivers/iommu/arm-smmu.c | 79 +++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu.h | 3 ++ 3 files changed, 89 insertions(+), 4 deletions(-) -- 2.26.2 diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index 10eb024981d1..147af11049eb 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -26,6 +26,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 smr; u32 reg; int i; @@ -56,6 +57,16 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) } } + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + } + } + return 0; } diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 08a650fe02e3..69bd8ee03516 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -652,7 +652,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + bool boot_domain) { int irq, start, ret = 0; unsigned long ias, oas; @@ -770,6 +771,15 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } + + /* + * Use the last context bank for identity mappings during boot, to + * avoid overwriting in-use bank configuration while we're setting up + * the new mappings. + */ + if (boot_domain) + start = smmu->num_context_banks - 1; + ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); if (ret < 0) @@ -1149,7 +1159,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_master_cfg *cfg; struct arm_smmu_device *smmu; + bool free_identity_domain = false; + int idx; int ret; + int i; if (!fwspec || fwspec->ops != &arm_smmu_ops) { dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); @@ -1174,7 +1187,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, false); if (ret < 0) goto rpm_put; @@ -1190,9 +1203,33 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto rpm_put; } + /* Decrement use counter for any references to the identity domain */ + mutex_lock(&smmu->stream_map_mutex); + if (smmu->identity) { + struct arm_smmu_domain *identity = to_smmu_domain(smmu->identity); + + for_each_cfg_sme(cfg, fwspec, i, idx) { + if (smmu->s2crs[idx].cbndx == identity->cfg.cbndx) { + smmu->num_identity_masters--; + if (smmu->num_identity_masters == 0) + free_identity_domain = true; + } + } + } + mutex_unlock(&smmu->stream_map_mutex); + /* Looks ok, so add the device to the domain */ ret = arm_smmu_domain_add_master(smmu_domain, cfg, fwspec); + /* + * The last stream map to reference the identity domain has been + * overwritten, so it's now okay to free it. + */ + if (free_identity_domain) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + /* * Setup an autosuspend delay to avoid bouncing runpm state. * Otherwise, if a driver for a suspended consumer device @@ -1922,17 +1959,51 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) static int arm_smmu_setup_identity(struct arm_smmu_device *smmu) { + struct device *dev = smmu->dev; + int cbndx = 0xff; + int type = S2CR_TYPE_BYPASS; + int ret; int i; + if (smmu->qcom_bypass_quirk) { + /* Create a IDENTITY domain to use for all inherited streams */ + smmu->identity = arm_smmu_domain_alloc(IOMMU_DOMAIN_IDENTITY); + if (!smmu->identity) { + dev_err(dev, "failed to create identity domain\n"); + return -ENOMEM; + } + + smmu->identity->pgsize_bitmap = smmu->pgsize_bitmap; + smmu->identity->type = IOMMU_DOMAIN_IDENTITY; + smmu->identity->ops = &arm_smmu_ops; + + ret = arm_smmu_init_domain_context(smmu->identity, smmu, true); + if (ret < 0) { + dev_err(dev, "failed to initialize identity domain: %d\n", ret); + return ret; + } + + type = S2CR_TYPE_TRANS; + cbndx = to_smmu_domain(smmu->identity)->cfg.cbndx; + } + for (i = 0; i < smmu->num_mapping_groups; i++) { if (smmu->smrs[i].valid) { - smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].type = type; smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; - smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].cbndx = cbndx; smmu->s2crs[i].count++; + + smmu->num_identity_masters++; } } + /* If no mappings where found, free the identiy domain again */ + if (smmu->identity && !smmu->num_identity_masters) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + return 0; } diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index bcd160d01c53..37257ede86fa 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -321,6 +321,9 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + struct iommu_domain *identity; + unsigned int num_identity_masters; + bool qcom_bypass_quirk; };