From patchwork Wed Sep 27 07:34:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114364 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4723903qgf; Wed, 27 Sep 2017 00:40:29 -0700 (PDT) X-Received: by 10.98.208.129 with SMTP id p123mr497402pfg.273.1506498029593; Wed, 27 Sep 2017 00:40:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506498029; cv=none; d=google.com; s=arc-20160816; b=KZ8yKPJnwBdsUkI+ZZt1Xi4F9z3m7Xq1hvUjf3wc5jyyEHuRZDfzzaVMBsuvDPVvxk 57WhBP9cTfrO+09VOKEgAjwpya5Y/r0FWuauVO3lruA2XKNbKKz/2Ef55yyzUZMQlkRn SIAfJGnSYTLccZb3QXMn0rYrJIIgOHHrqwdnF00nC8Vh7yrJ4Yp8YLaEbYkDClqPwHFW MNMDcG7QGkyLA+LnWGo6SAi+HmHaZGCJj35Ix+GrA8JSzwsUhoSDYEPIQ1w7IWYWE+wa PjWlYpEWq1kQn0imeeyVx+tKdtP75f7g1u2aK8Lb51f/d14Bh/q4+DlGNc4A4gUeRer1 EbLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TCaq+L0ACn83URvot4Qh0PvleIfjU5dQTuprZW0mEnw=; b=VqOB1bLAqVmZPA+QoR9XQyRrP/cV6uvKKM0U1vwJvXIAcYW37XLHK9nJVvePWAv0gt uW1k9Kiyhe2h8CNLh51EdCg+H9YomAhPo0jfUGqAsRPh9RJiN2PDN4LOHV1OQK2QSdGP 3cJoQ7RSo+DzAlp1p1yrWfcwuc4NJ2JHb6oDcWikfAAqRqUYh2qiijZp8QOE8TNswpeJ xdRd8QSmANGVkOKqDZ5cKgaBF+Y/TuMqPY8fh9XSnXKxvf27dLCzUYdvUJucjHwfrm7R YrIlBygOPQVvW2TRC/h4LGyPVibRloXRH1l2v+f3//J+v017Uf8n3nftAFnrpOcQ6XAS aHyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=s9I2WE6c; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:33 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 01/11] dt-bindings: net: Restore sun8i dwmac binding Date: Wed, 27 Sep 2017 09:34:04 +0200 Message-Id: <20170927073414.17361-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.5 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Wed Sep 27 07:34:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114354 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4721368qgf; Wed, 27 Sep 2017 00:36:46 -0700 (PDT) X-Received: by 10.84.196.131 with SMTP id l3mr466615pld.195.1506497806643; Wed, 27 Sep 2017 00:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497806; cv=none; d=google.com; s=arc-20160816; b=FpNqfPZP1aXRxU3PC2mKj8XACHPT0pZUeZKyrLqMKrMuLSpNqJYvAKA1P5zaVYL+C7 uFBPH774u+z5nyBicY8afqPj/zGIgnrgV9OHbSIR+8kJx8DH7NH3xk1sa19kBfKU9yoT SSyvqNtczYlsqw8ER+JM80RvPwKQ0pY7JfUPFj/ITGXYFGXNHBlIfaR3Y24aNtFqHZTi LMiG8jphANmAuMKpp3Y/7yfXHJez9eXnl/QTOwMb1wZlUSghoA8Lmg2XfhSBLvBqlmz4 FgElXpF2ivWCKH3Tnr+B7uAOk+Qwup0yfBuUTt3Onks7uLgAMf9w44olSHWBb1xSgjuE 2fBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tXvK43lwJIZaVIzV0ZkJ0J6pwzQK1KRpouoKuQWSpDI=; b=fiHd6lRHoNANQ9giGH7BC9MKeTTsyJj76CPFdwzSiadoWWiDOFWA1xYoT5x/H5HaDF JdOS7KS5E54eV/YrkX2OT3KxcEi0MVOk0mOLEosDAagR7JtUkuYf0f/Ibbc+CHxQLb0R pVbbO9cDFiRotfmeRZYOKzUmP/4d4K2C7Ga6BaKQ7EX3dihDt3+TiAYkB8zgXmoUTx+k yQTmWQM0r9XdQeOViHwDL1r7rdEFBQOz8cLwhcHOLziguk37ZxECQZazpnTK+EDbua45 tbKzgcdXt0YiaPyveCDNIlcRBF5i4/SNNFJdskZDRZYsbcMB1VQWOHhfJJ8pncNonijj 8GOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Rp7he77o; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:34 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 02/11] arm: dts: sunxi: Restore EMAC changes Date: Wed, 27 Sep 2017 09:34:05 +0200 Message-Id: <20170927073414.17361-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore arm DT about dwmac-sun8i This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 ++++++++ arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 +++++++++++++++++++++++ 10 files changed, 128 insertions(+) -- 2.13.5 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index e1dba9ffa94b..cc20d676a642 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -111,12 +112,30 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 8ff71b1bb45b..17cdeae19c6f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 5fea430e0eb1..6880268e8b87 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index c88518b3f538..f5f0f15a2088 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 828ae7a526d9..331ed683ac62 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..80026f3caafc 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index f68f6c534e2a..3b7d953429a6 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -408,6 +408,32 @@ clocks = <&osc24M>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; From patchwork Wed Sep 27 07:34:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114362 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4723279qgf; Wed, 27 Sep 2017 00:39:35 -0700 (PDT) X-Received: by 10.99.95.194 with SMTP id t185mr514690pgb.145.1506497974978; Wed, 27 Sep 2017 00:39:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497974; cv=none; d=google.com; s=arc-20160816; b=No/0ZqaElz2LRF3YSH+Gbh/zk1JS5VF6VCFhARzvw2isMoeEMd4ZNhTSuBvGTSqw6K xdMMxz4nwAc5NbaUPzPrfhfoLYm6rBQhXs65SBg7HukXZ0TSuxob/yOsl1Yg7bBEPS8u ffLE57DYzBqkW20fnSshAQN3224PYKVhCaW9ZPhrQdmDG1uYRdGAezQUHc9ndc49Ftyp DbBaqzXKeDIAdEBfuUWWSRvX3YvrqFu/YYgWIQ/UeCzvEoFc1D3MXNArYcd8q7gdAnnh JPDn0BkNs5KEmvDZrzIXRuoORnttgP+3nMDliKc9n9n1+R3zkZWY4HkDMX5F2lD6VEkw omZg== ARC-Message-Signature: i=1; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:35 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 03/11] arm64: dts: allwinner: Restore EMAC changes Date: Wed, 27 Sep 2017 09:34:06 +0200 Message-Id: <20170927073414.17361-4-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore arm64 DT about dwmac-sun8i This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ 8 files changed, 135 insertions(+) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index d06e34b5d192..806442d3e846 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -71,6 +72,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -81,6 +91,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 39ca22d418a2..75494cd90e40 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -502,6 +502,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..968908761194 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a8296feee884 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,12 +137,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..d906b302cbcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,12 +144,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; From patchwork Wed Sep 27 07:34:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114363 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4723447qgf; Wed, 27 Sep 2017 00:39:50 -0700 (PDT) X-Received: by 10.84.179.67 with SMTP id a61mr495155plc.230.1506497990537; Wed, 27 Sep 2017 00:39:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497990; cv=none; d=google.com; s=arc-20160816; b=izRsobikF44E03ONqFqZDTJnw7A58nzTqTv5DnPKsS63jzh8bGQKoBLCSO+GMAwZly D99uhsoFawXq/D0hHoBD/7Wlv+XRKsO9ZvozjIXWSoY3usa6maWmXAoOu4gVfNWtvWey 2Hfu8PmEWzhkcXEq9x1aG9nQmuHeQNUJZwgGz7Ac4xF2CZBctEvaaJsN1ZbeUKpUMWFl i/yqZphdDnuLAP40cltpskKud/mK6eMDrDBkyN5Vz/rgpH46F4ai1vEa8LDDOe2GRH7q ZVXB+Yw2UD9mhOJww+vceIZw6zZJ3iXoQ/DgA1eHmUjzfjUXPC/bP7TaF08SwpKQtu4B f9qg== ARC-Message-Signature: i=1; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:36 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 04/11] net: stmmac: sun8i: Restore the compatibles Date: Wed, 27 Sep 2017 09:34:07 +0200 Message-Id: <20170927073414.17361-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch restore compatibles about dwmac-sun8i This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles") Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 39c2122a4f26..fffd6d5fc907 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } static const struct of_device_id sun8i_dwmac_match[] = { + { .compatible = "allwinner,sun8i-h3-emac", + .data = &emac_variant_h3 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = &emac_variant_v3s }, + { .compatible = "allwinner,sun8i-a83t-emac", + .data = &emac_variant_a83t }, + { .compatible = "allwinner,sun50i-a64-emac", + .data = &emac_variant_a64 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); From patchwork Wed Sep 27 07:34:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114361 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4722840qgf; Wed, 27 Sep 2017 00:38:59 -0700 (PDT) X-Received: by 10.99.115.92 with SMTP id d28mr527891pgn.280.1506497939891; Wed, 27 Sep 2017 00:38:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497939; cv=none; d=google.com; s=arc-20160816; b=ERQ0B6LhyLnqGA6ZrHEtb8hGNrLMi3iX6nhPBT+2dU14tPWIukgCkgVrsoDXqtIIi+ ZnCTLfZltRTLLGIe3ZI1hCJKSQi3ypMRhwaGAvJ6ZyAe7ebbmo1DrXrMOS8zMg4VGeVo FYUvJtzuzRm6NGGudPm/BO6+r2wslCtmJwT/sWMAZtRcbi7Dxyv+DmVghBNXsbNd7haY 1nAS4vedLedzIw+rujfae4eTElnPy+ta6SrVMYUEyhayKaxQNf42Wim5wFmH8JlQ3kPc x4Z+imoJJEB8ZT7EA68mO9ztWyhcIcaLHLrh1nzf/qTq/3QVmmEdvO7eJNNtlk5IwEsK oyWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=32R5TgMDZYCR9hvyqW2q/ceSSSJ6voqy3f/ojhl7Mu4=; b=YIOjAgAKwXiKLksFb4V0Wi4Qi6eVKn47YmwyLUzeWcs5MwlkNLTegoNHB0R/ENQin7 R6YCEgCJlQ8AC8bwwlKn+uGsmw10mdQuBgoy4b7heqTw1CLD5AmwAlztktPFwyGd29AF Qv1Y7TTVT4lg0UVeBYlorMKfxgBndCN0JF+Vs/pj1CXXVPrUZs8XwyAjV/S9g5HMymOu J/o/3PU/bGYEyUsZnyK4v6rV52y4YDDCi8o37KYXQfyAQowVR9MyRXTCUM8OyXbswRRG M1XSRCDMKCC4nb/3XSLzbFSIChz+zUGtzZV79fIbocattxepzyOetFgLh1fnmNlUTb3i f2BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=r2K1lJHP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:38 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Wed, 27 Sep 2017 09:34:08 +0200 Message-Id: <20170927073414.17361-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 138 +++++++++++++++++++-- 1 file changed, 126 insertions(+), 12 deletions(-) -- 2.13.5 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..e2ef4683df08 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the mdio node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux" + - one child mdio for the integrated mdio + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- phy-is-integrated +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; From patchwork Wed Sep 27 07:34:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114359 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4722331qgf; Wed, 27 Sep 2017 00:38:15 -0700 (PDT) X-Received: by 10.98.131.193 with SMTP id h184mr496515pfe.307.1506497895828; Wed, 27 Sep 2017 00:38:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497895; cv=none; d=google.com; s=arc-20160816; b=qM8PajM95pJr7YSOgVWqKm0uHjxezpYofAEn3CgJ+3RhCR7dzn9l0cAb39nVTc8qMC Il8J7bXopXh2f8FOtQFD1QZWfSPmzvOYgNuapMEECHQnnpu3t+OXz26B4E7SDbjkpN4V 2eOATP3Cxe8LMcV56NJa3gsVJsXET7gqBvtfTIufefABst5vZDl8CWQMCGKutGlEY55N Y+SkawQrKFFJFeyZEfJFj7c+A0YnlnpcaDrl/qCloG01QvRJOWN6zFupPx9XV1JwZJXv QAcdCx+cIyxeMuT/0YpnH9lKWmV0V9uASSATidxK/L/2/VLW9V+FyuefOsfW5AY0P4YO 3xNA== ARC-Message-Signature: i=1; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:39 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac Date: Wed, 27 Sep 2017 09:34:09 +0200 Message-Id: <20170927073414.17361-7-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) -- 2.13.5 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 3b7d953429a6..a8e9b8f378ba 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -422,14 +422,33 @@ #size-cells = <0>; status = "disabled"; - mdio: mdio { + mdio0: mdio { #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; From patchwork Wed Sep 27 07:34:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114355 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4721403qgf; Wed, 27 Sep 2017 00:36:50 -0700 (PDT) X-Received: by 10.101.68.193 with SMTP id g1mr531930pgs.232.1506497810737; Wed, 27 Sep 2017 00:36:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497810; cv=none; d=google.com; s=arc-20160816; b=fl69/ItQC1jbkydcmDG4GZPUvOp3J1cqaIh8Qfn0ecbYSeJsy3IZlorioE8JY7gjaw vNQMoBBn9qJE4WsSAyh276XYCu1ARpAXpfg9pgPGNYkYPrkwquWGZkJxpcDFE2m6QrUg MvgUoBcWrHuzVho3qg2xeKG7m60AEbPI07n4qlSMIdH7IAQJ1BzjSZVdrYQfS8+ZE3An IGVf+oD7AESCHbWAas3j1NId8nn6UzGqeF1L2oNEJnw0OWn0awwloVOFV++Ra5lBYYXG TiL5j7o1Jb6FMv8PlxwwJAtw1Ktmgai2DSZYxzHKNgkUR9VVZ+A6QamneTsKuenyTwhI 5Tgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=82eaKss+xoRtGstnmGkj7ELU1/z9QGwl4wD7iLhgcK0=; b=mFUbodP4PYoBElgFFBOhgjI3qzXfsfLqq5VMZF9vL7/s2kAf6daXZS2FYMSS/j4gbo e3f8yeoaI5HgetJsw1m3myHov8EQpgpY4XW+vunHLlpc0IoJnux4VxiwdOl6XXP9zqoH f5k6nAZTGCEwwjBs6CAFuaRoOiP65WsMjVJRjEHnD/f1lCRjv5uzjCgxSWRikXFR1ppz h30ssapL5UnMLA8t2764bV5ohnfVchie8FWvTEeH8IkJtFhK3HC6AwQH+FuJ2176ANgP VmHKJx87Z+72ugy333OfQJsPO4L1ex3772kb3cmlNJGXk07nz/PnCkfQVs1JSgIcR+/t UmGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=aEp2ZHxT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:40 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 07/11] arm64: dts: allwinner: add snps, dwmac-mdio compatible to emac/mdio Date: Wed, 27 Sep 2017 09:34:10 +0200 Message-Id: <20170927073414.17361-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.13.5 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 75494cd90e40..e30476f05802 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -517,6 +517,7 @@ #size-cells = <0>; mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; From patchwork Wed Sep 27 07:34:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114360 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4722577qgf; Wed, 27 Sep 2017 00:38:38 -0700 (PDT) X-Received: by 10.98.29.199 with SMTP id d190mr535014pfd.74.1506497918041; Wed, 27 Sep 2017 00:38:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497918; cv=none; d=google.com; s=arc-20160816; b=T2e3OFHYp+fuWr/cbO7wzTf+6wZO3L9/jhngLPHMIX7V2W5lMacO3/2BrDEjp8GCQB RqpOg7pKWw8firiXtd4h+zaDsOiVi/LjOUnMJNLuwfzUdvm47stRBwTSROqQ2fhKgYzj tPttFWc77pvcHBYPoZ6Ozhqdl9AUSuqshcZLayNP6lB0W/9uLth7ptIvbfX0Fft4szTy HZLMzPDUBf2gfDdFyyTy6oPlHrG9PM/0mnY+oRydsOSLi+KU9qQeozVf3btlTNHAJQIF 5DPndaEk/LyGRQmdI54RTYoVz+tfg1/PU2kO3LF+eQ86LphLOgRUs+Rb3P6I89lBdf8i ryVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=jUvcFe9QWednzI/mKcQUunuyg004ubQNh8y8VDgDc4E=; b=HZJDOoEFUk/N/pMZLL603DVCximbLboDCaYZbkcBHD1srZq0g1+DDynFdEjkLhaimq H+bFwt9kNen+/jltLcHQdfYxJOedfOFS5p+Rzd7eXHUuwubpWR4Dqf4GXu3TGCPpzx35 BWB9c5Y7e/mLK9anidS+G0m/u+Rx+EBbs/IKQWbkei+q5v5FxlLZURXKJvWW/4wT/15V rHEJyBU+JIFL2lu+P3ItmiYWT98ERd2bumZeK5oOmWt5OgjMyakTE8Iy+It1R2zwQvdw QlulTgwuaibW+EwdyaVXFDcmF4HbKFVQO8IsV6NiM7cS1MVrF4HCqcu28r1lOiipVSev CVrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Be8DQaKR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:41 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 08/11] net: stmmac: snps, dwmac-mdio MDIOs are automatically registered Date: Wed, 27 Sep 2017 09:34:11 +0200 Message-Id: <20170927073414.17361-9-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Since these compatible is automatically registered, dwmac-sun8i compatible does not need to be in need_mdio_ids. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 8a280b48e3a9..9e616da0745d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, bool mdio = true; static const struct of_device_id need_mdio_ids[] = { { .compatible = "snps,dwc-qos-ethernet-4.10" }, - { .compatible = "allwinner,sun8i-a83t-emac" }, - { .compatible = "allwinner,sun8i-h3-emac" }, - { .compatible = "allwinner,sun8i-v3s-emac" }, - { .compatible = "allwinner,sun50i-a64-emac" }, {}, }; From patchwork Wed Sep 27 07:34:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114358 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4721972qgf; Wed, 27 Sep 2017 00:37:42 -0700 (PDT) X-Received: by 10.84.233.69 with SMTP id k5mr501369plt.260.1506497862529; Wed, 27 Sep 2017 00:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497862; cv=none; d=google.com; s=arc-20160816; b=xmwp8VLEXVOlvBN+eNnf5xQBsTvM3bCs4hnrXKlV5H+4Jejdr2iFrrBuKtAmRlHofb XLi+3z9AUTIN4+OktSRof6HVbCKo6+nLmvVqM3SMH+53/5XJ1Tg91UkzG5XFNv/khTRF inw0UUxbzID/PiGYC9Pihl6WubdRtyfmwgPCVcur66uj0R7t9qAFzA4xJ7eTh7EoWUOM 1uvCXZ+788XcGfC+9c08kOUvcz6JIJ0mLX55bZiLD2FKzAz+i8sbxOmybHOZIF+xAYw+ SIRUC2rN9tJu2FVujUmbyDw5p0TK5dgtrAoy4sVtgG52p4qF/xgrdyXfxYHUOKxwsUcL 2Jqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ZDRqn6oM7YLvC7qyulEsdiG4u/Ek3wP9CmcxSAqe5YU=; b=Nc6uji68B/No8NY39yXim+ZkKOT/2grblDQU64LeBA0JHeevvi/mEKebbVFoBPJiX8 GZaQNQB2usWkPUsSPFPslIeVD0/fvYET5vEUoi1JufpfWwVboc/7Nz3UM1H+St2LCn1D DJdw9uhEegjOQRgxogYadQIcjHiQTCq1fIe8WiXwvvqW55CwkT8U818REkTNl36BD7Sg EOtTs/jFHkMyU8sYhQl5Y5kVIWm+7xlG8L4FHZ1w6/RPeVJK0SSL85mzpqPNQZJj7AQp OOuDZnMmzt5bFF40NDPQw/4BLpdgXFipIcdrEz5SeN0mgzYJgJ8HsX7D+CAFIPI01k9w Jyow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Y5xkQZv7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:42 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 09/11] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated Date: Wed, 27 Sep 2017 09:34:12 +0200 Message-Id: <20170927073414.17361-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the internal one. This patch adds a new way to find if the PHY is internal, via the phy-is-integrated property. Since the internal_phy variable does not need anymore to contain the xMII mode used by the internal PHY, it is still used for knowing the presence of an internal PHY, so it is modified to a boolean soc_has_internal_phy. Signed-off-by: Corentin Labbe Acked-by: Chen-Yu Tsai Reviewed-by: Florian Fainelli --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index fffd6d5fc907..672553b652bd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -41,14 +41,14 @@ * This value is used for disabling properly EMAC * and used as a good starting value in case of the * boot process(uboot) leave some stuff. - * @internal_phy: Does the MAC embed an internal PHY + * @soc_has_internal_phy: Does the MAC embed an internal PHY * @support_mii: Does the MAC handle MII * @support_rmii: Does the MAC handle RMII * @support_rgmii: Does the MAC handle RGMII */ struct emac_variant { u32 default_syscon_value; - int internal_phy; + bool soc_has_internal_phy; bool support_mii; bool support_rmii; bool support_rgmii; @@ -75,7 +75,7 @@ struct sunxi_priv_data { static const struct emac_variant emac_variant_h3 = { .default_syscon_value = 0x58000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = { static const struct emac_variant emac_variant_v3s = { .default_syscon_value = 0x38000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true }; static const struct emac_variant emac_variant_a83t = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rgmii = true }; static const struct emac_variant emac_variant_a64 = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) "Current syscon value is not the default %x (expect %x)\n", val, reg); - if (gmac->variant->internal_phy) { + if (gmac->variant->soc_has_internal_phy) { if (!gmac->use_internal_phy) { /* switch to external PHY interface */ reg &= ~H3_EPHY_SELECT; @@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } plat_dat->interface = of_get_phy_mode(dev->of_node); - if (plat_dat->interface == gmac->variant->internal_phy) { + if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) { dev_info(&pdev->dev, "Will use internal PHY\n"); gmac->use_internal_phy = true; gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); From patchwork Wed Sep 27 07:34:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114357 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4721731qgf; Wed, 27 Sep 2017 00:37:20 -0700 (PDT) X-Received: by 10.84.252.129 with SMTP id y1mr476531pll.107.1506497840133; Wed, 27 Sep 2017 00:37:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497840; cv=none; d=google.com; s=arc-20160816; b=q0L3D8gbFemR1j/NQ9KgwLM66a+DsOwBLfe4TBDfdTLbWRuXYtq7B4229rWSucJL4x 8WOq0ev9tJcPguNyyyE/JBZiH18TylowUiOy36hCVUvkvMiFP2al4n9XvMcmRtr+j267 6Nn4YhdovWSokUJfrZXuAfSAN2/nmWt7wYElPdVHOuyJSUGBt6MdE8HXk/s8kj28jjCY CRmpuSgbuBUpEi3dR8JNkLT1iCZFJd8LibwiPX/v4ynzY/pJ+WvYh2oxvISc/vZT/xoz l7eU6Yn0TH2He8v6VFIcmMNSdQiZG+Cr6c1UmveM0gXE0SM7XCFETURHLvaRqjNyr4Z+ E81A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Cq7Y0f+J5EAQNxEaYiqIxrHLCjh0HE/SHmEZg/inewk=; b=JZUSuD11Th0H31U0BdcANWYoQAXGXr99AMxgIPJUp94SNmagsBF5nJ7JI176hA+26Q +RGNJmaiaOTMTwhKVm3zDTLNPV7wFgLcKOS6leevo0Ioc8YSLlAEH1VL3ocMY3hWsq3g iAJODKyTcTzvyGspb1jxykbkzC9GbDyNY/IpREQ2I7iKxEqw7TxIioBDFpsh5CwR0vyw Fl3Ip+gzYd0d4cx8jUar+whNlBD6jtHP5qv1kmko80GIk9RUCKVcM00jV0rw/JXQ6Mhp DmDiiMpbG6WKjl89pIxQmoV8pnzgXBwmeLnhw7Sz2AhTbBaTS/TN9l4aWDG8CIyKwfdl bGFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BHceTr1E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:43 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 10/11] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Wed, 27 Sep 2017 09:34:13 +0200 Message-Id: <20170927073414.17361-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Allwinner H3 SoC have two distinct MDIO bus, only one could be active at the same time. The selection of the active MDIO bus are done via some bits in the EMAC register of the system controller. This patch implement this MDIO switch via a custom MDIO-mux. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++++++++++++++++++--- 2 files changed, 104 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 97035766c291..e28c0d2c58e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -159,6 +159,7 @@ config DWMAC_SUN8I tristate "Allwinner sun8i GMAC support" default ARCH_SUNXI depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX ---help--- Support for Allwinner H3 A83T A64 EMAC ethernet controllers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 672553b652bd..8bd500c351b4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -71,6 +72,7 @@ struct sunxi_priv_data { const struct emac_variant *variant; struct regmap *regmap; bool use_internal_phy; + void *mux_handle; }; static const struct emac_variant emac_variant_h3 = { @@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = { #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) +#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 +#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) return 0; } +/* MDIO multiplexing switch function + * This function is called by the mdio-mux layer when it thinks the mdio bus + * multiplexer needs to switch. + * 'current_child' is the current value of the mux register + * 'desired_child' is the value of the 'reg' property of the target child MDIO + * node. + * The first time this function is called, current_child == -1. + * If current_child == desired_child, then the mux is already set to the + * correct bus. + * + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to + * know easily which bus is used (reset must be done only for desired bus). + */ +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, + void *data) +{ + struct stmmac_priv *priv = data; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + u32 reg, val; + int ret = 0; + bool need_reset = false; + + if (current_child ^ desired_child) { + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); + switch (desired_child) { + case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: + dev_info(priv->device, "Switch mux to internal PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + if (gmac->use_internal_phy) + need_reset = true; + break; + case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: + dev_info(priv->device, "Switch mux to external PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; + if (!gmac->use_internal_phy) + need_reset = true; + break; + default: + dev_err(priv->device, "Invalid child id %x\n", desired_child); + return -EINVAL; + } + regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); + /* After changing syscon value, the MAC need reset or it will use + * the last value (and so the last PHY set). + * Reset is necessary only when we reach the needed MDIO, + * it timeout in other case. + */ + if (need_reset) + ret = sun8i_dwmac_reset(priv); + else + dev_dbg(priv->device, "skipped reset\n"); + } + return ret; +} + +static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) +{ + int ret; + struct device_node *mdio_mux; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + + mdio_mux = of_get_child_by_name(priv->plat->mdio_node, "mdio-mux"); + if (!mdio_mux) + return -ENODEV; + + ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, + &gmac->mux_handle, priv, priv->mii); + return ret; +} + static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; @@ -649,12 +724,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) val, reg); if (gmac->variant->soc_has_internal_phy) { - if (!gmac->use_internal_phy) { - /* switch to external PHY interface */ - reg &= ~H3_EPHY_SELECT; - } else { - reg |= H3_EPHY_SELECT; - reg &= ~H3_EPHY_SHUTDOWN; + if (gmac->use_internal_phy) { dev_dbg(priv->device, "Select internal_phy %x\n", reg); if (of_property_read_bool(priv->plat->phy_node, @@ -743,6 +813,8 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) { u32 reg = gmac->variant->default_syscon_value; + if (gmac->variant->soc_has_internal_phy && gmac->mux_handle) + mdio_mux_uninit(gmac->mux_handle); regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } @@ -801,12 +873,6 @@ static int sun8i_power_phy(struct stmmac_priv *priv) if (ret) return ret; - /* After changing syscon value, the MAC need reset or it will use - * the last value (and so the last PHY set. - */ - ret = sun8i_dwmac_reset(priv); - if (ret) - return ret; return 0; } @@ -889,6 +955,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; + struct stmmac_priv *priv; + struct net_device *ndev; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -973,9 +1041,31 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + goto dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + /* The mux must be registered after parent MDIO + * so after stmmac_dvr_probe() + */ + if (gmac->variant->soc_has_internal_phy) { + ret = sun8i_dwmac_register_mdio_mux(priv); + if (ret) { + dev_err(&pdev->dev, "Failed to register mux\n"); + goto dwmac_mux; + } + } else { + ret = sun8i_dwmac_reset(priv); + if (ret) + goto dwmac_exit; + } return ret; +dwmac_mux: + sun8i_dwmac_unset_syscon(gmac); +dwmac_exit: + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); +return ret; } static const struct of_device_id sun8i_dwmac_match[] = { From patchwork Wed Sep 27 07:34:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 114356 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4721495qgf; Wed, 27 Sep 2017 00:36:59 -0700 (PDT) X-Received: by 10.99.98.7 with SMTP id w7mr512419pgb.338.1506497818906; Wed, 27 Sep 2017 00:36:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506497818; cv=none; d=google.com; s=arc-20160816; b=JH3+OGxRl4zD6ewLN/g/5K9e49c9QqD+wC5ZpJHaR5rwH5a5ylMA7FV4uwulc/WXA8 qR2adoAJFcnZDQVOKMzYfLdWM1lEFXSlpvhm/RH0f5ng5t+sW3euDAXbqwfp6JE2cgAr WK+qZe7i+gcptg36aK0HZbMcfs3PZSXJrdbkwBXhMkOJ4aMw0lmrnO8bVcZOxTStcQIM /2spR4iWx/G7CHDcnME5m4RQDUAmvi7qwdKciYC+Gc6G/aU3barvx8+4TcoslgurECdZ 0mwp+BHvuUf+vHxJiQJSgnkFI8AKSdSzqre+FrEUQ800LfRd9u7f0S3Aq351emocNCtV zAVQ== ARC-Message-Signature: i=1; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id n9sm5660526wmd.12.2017.09.27.00.36.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Sep 2017 00:36:45 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v6 11/11] of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes Date: Wed, 27 Sep 2017 09:34:14 +0200 Message-Id: <20170927073414.17361-12-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170927073414.17361-1-clabbe.montjoie@gmail.com> References: <20170927073414.17361-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Each child node of an MDIO node is scanned as a PHY when calling of_mdiobus_register() givint the following result: [ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c30000/mdio/mdio-mux has invalid PHY address [ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0 [ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1 [...] [ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30 [ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31 Since mdio-mux nodes are not PHY, this patch a way to to not scan them. Signed-off-by: Corentin Labbe --- drivers/of/of_mdio.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.13.5 diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index d94dd8b77abd..d90ddb0d90f2 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -190,6 +190,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) struct device_node *child; bool scanphys = false; int addr, rc; + static const struct of_device_id do_not_scan[] = { + { .compatible = "mdio-mux" }, + {} + }; /* Do not continue if the node is disabled */ if (!of_device_is_available(np)) @@ -212,6 +216,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) /* Loop over the child nodes and register a phy_device for each phy */ for_each_available_child_of_node(np, child) { + if (of_match_node(do_not_scan, child)) + continue; + addr = of_mdio_parse_addr(&mdio->dev, child); if (addr < 0) { scanphys = true; @@ -229,6 +236,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) /* auto scan for PHYs with empty reg property */ for_each_available_child_of_node(np, child) { + if (of_match_node(do_not_scan, child)) + continue; + /* Skip PHYs with reg property set */ if (of_find_property(child, "reg", NULL)) continue;