From patchwork Wed Sep 27 13:32:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 114369 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5050359qgf; Wed, 27 Sep 2017 06:35:12 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBOAJUiNGqKbFt2sMOXv7OyRICYu1rpgyGZPqS3XK10o7u5gdDNazE4xsx+NYxOTffBj6/X X-Received: by 10.99.114.29 with SMTP id n29mr1386665pgc.258.1506519311929; Wed, 27 Sep 2017 06:35:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506519311; cv=none; d=google.com; s=arc-20160816; b=rPcdHxU+9Q6XavZiiZ0I7hGOg/eg7kzsMkLkSyoZi5pZvmSpJf5iYHKzgEu0ogCtDe /U2QOqQT79RReoMux9GrOmcm6ugkmXFHkxiFNjl4Kinbsrrfl8GdvuN7hmttnaBzWI2z lxY5nlZoasXmvDwSqN+X0mwMk2cSI3t4phA6c4cXg+IYd4/bsuDvo+6OL3KytR5pWBfI j8kFdha+2nRYmtJPN8buoBRup3J8UyBtGv3qa0McCvn+e9cBg43OYOQtU3SZzY+whib9 zVKYeY4mrdzn01OJ7wbiP8wxv4nmDjaaxMeskBRAB9esJe7cVUlMn0lq0cHTu29irIs9 a5GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=7PuMzhE73aZd2IdlVFjvki7Zu7txRoSGuoDnIMfnFTE=; b=vYJ6OODw7Hps6ApaX8LJRfegx3W/u2OsT6xG2mSsL/b3GjJz9SLKHXuf3SudxSOV6U Lfw/A7nkmz4KxwsLdJKTZ4DnWO6KUpMcQ3LbLY1b9PQdRI963kTATAfzdZNR9cCvvSEZ WASy3LC7Vg+L5FXrarB+yZtXAx6B79PwMy9kXSAVA4Tb8xKm1sqVJd2J+/v6I1kE6UfL Ke+hiCOuvzu2QHoOKDL6Hy1hZ0D75UFlPwvXqbI4wlpkW49swoiy/RuTafwU9ZV5R3bC HHfmA7t3ATB477gWtmmM8m3tzrynataR4yZLmy0pj00IBM9eJcInd6uiahmJE3Xf2M/T k/5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u9si7660961pge.139.2017.09.27.06.35.11; Wed, 27 Sep 2017 06:35:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751926AbdI0NfK (ORCPT + 7 others); Wed, 27 Sep 2017 09:35:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7449 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbdI0NfK (ORCPT ); Wed, 27 Sep 2017 09:35:10 -0400 Received: from 172.30.72.58 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16842; Wed, 27 Sep 2017 21:35:06 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:34:58 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v8 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 Date: Wed, 27 Sep 2017 14:32:37 +0100 Message-ID: <20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.59CBA90A.015A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1199e1a103f72e2595b31297b988f396 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: John Garry The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMU mappings for MSI transactions. On these platforms, GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch adds a compatible string to implement this errata for HiSilicon Hi161x SMMUv3 model on hip06/hip07 platforms. Also, the arm64 silicon errata is updated with this same erratum. Signed-off-by: John Garry [Shameer: Modified to use compatible string for errata] Signed-off-by: Shameer Kolothum --- Documentation/arm64/silicon-errata.txt | 1 + Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 66e8ce1..02816b1 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | +| Hisilicon | Hip0{6,7} | #161010801 | N/A | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index c9abbf3..3b0d599 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -7,11 +7,18 @@ the PCIe specification. ** SMMUv3 required properties: -- compatible : Should include: +- compatible : Should be one of: + + "arm,smmu-v3" + "hisilicon,hi161x-smmu-v3" + + depending on the particular implementation. * "arm,smmu-v3" for any SMMUv3 compliant implementation. This entry should be last in the compatible list. + * "hisilicon,hi161x-smmu-v3" for HiSilicon hi161x + SMMUv3 implementation on hip06/hip07 platforms. - reg : Base address and size of the SMMU. From patchwork Wed Sep 27 13:32:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 114372 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5050654qgf; Wed, 27 Sep 2017 06:35:28 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBIxVKgUpxbRWu6tjHIl8fdcPehXdTtgPpp3tj8/1KwOqMeR2qfNLQPj1EQkg0jwFggtqpL X-Received: by 10.98.236.17 with SMTP id k17mr1379565pfh.191.1506519328702; Wed, 27 Sep 2017 06:35:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506519328; cv=none; d=google.com; s=arc-20160816; b=pvo16Ja9Hq6YGK1gvz4tm7GZQh7uVIIWmsbGyTeypZxnXgJLi4oRyBTGWOiXcogf98 h8vkXgxbGsfjPp7Bcoyk8J2B4cR/asU/iHTq5kUBGWIu+06khJUCI/dCPOSFs1CCCE8+ kaONcVME7JpMOr86b2CAI6RQwfQVTyw3g2dUNz+FRRSUq42zzfFOoO3flUGQTNZi+Stx /MasGU/BIPIkUqmDo6zd3EQ1GKjGtvIAEPSjJ9DP4wr0wsdr2sK7SGmgaylFVxpqZPOo bj0FzNuRFJYtO7s2mLjzvxlAfH3imGsY8MZg1KqQ1JagGr5shiLXlORk8MKHacX6D+aI N0pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=ZAFUJV/JskuWjjMWKykUZ3a/fyD41ekBoyXbE8o9PLc=; b=baOsFy5vO7GPBUB4rAXNRMdrGAWf3xg4/UzXJRgQeOfYBj8PVv54E5iteQsTDTod51 dR/VUEH0UeoCrzfARzIXBjXmMtnpagk+USkYwoZO6Rp0mjb36/Wp7z5P1Ycso7xRDAh4 F8lY0RyZIqDNWZqPgJYcK5eZP2lswiXJmRgwlcMGt0I7UslmV1sXFbNKwbmWl4g2pNlK Rr6o00hAwLxyj+xvXbqq7LaXXURoy+rg0vZ9YIy5exFM7tJqpgLBw4qhNpFJaQzO1hso PZ9K0TsGpiiEVbluBglZwp6VovPBmqnL0+uXFUOqsZq7OGwywYgelRiaGzirpj57ZZhK S5Hw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u9si7660961pge.139.2017.09.27.06.35.28; Wed, 27 Sep 2017 06:35:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752845AbdI0Nf1 (ORCPT + 7 others); Wed, 27 Sep 2017 09:35:27 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7450 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbdI0Nf1 (ORCPT ); Wed, 27 Sep 2017 09:35:27 -0400 Received: from 172.30.72.59 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16869; Wed, 27 Sep 2017 21:35:21 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:35:14 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v8 4/5] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Wed, 27 Sep 2017 14:32:40 +0100 Message-ID: <20170927133241.21036-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59CBA919.0131, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a2e0ebeb286de661b7de6e2805547181 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org IOMMU drivers can use this to implement their .get_resv_regions callback for HW MSI specific reservations(e.g. ARM GICv3 ITS MSI region). Signed-off-by: Shameer Kolothum [John: added DT support] Signed-off-by: John Garry --- drivers/iommu/dma-iommu.c | 19 +++++++++++++++++++ include/linux/dma-iommu.h | 7 +++++++ 2 files changed, 26 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9d1cebe..f8709a2 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -198,6 +200,23 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(iommu_dma_get_resv_regions); +/** + * iommu_dma_get_msi_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * IOMMU drivers can use this to implement their .get_resv_regions + * callback for HW MSI specific reservations. + */ +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + if (is_of_node(dev->iommu_fwspec->iommu_fwnode)) + return of_iommu_msi_get_resv_regions(dev, list); + + return iort_iommu_msi_get_resv_regions(dev, list); +} +EXPORT_SYMBOL(iommu_dma_get_msi_resv_regions); + static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 92f2083..6062ef0 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -74,6 +74,8 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg); void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list); + #else struct iommu_domain; @@ -107,6 +109,11 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he { } +static inline int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + return -ENODEV; +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __KERNEL__ */ #endif /* __DMA_IOMMU_H */ From patchwork Wed Sep 27 13:32:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 114373 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5050691qgf; Wed, 27 Sep 2017 06:35:31 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDYT0hWWPcnhx29o1RfTE0iXPoqUb+Gyrqr924Jm5n6hUCnpkFT4/IPl0/SLPD0aatDyGwf X-Received: by 10.84.232.200 with SMTP id x8mr1288969plm.347.1506519331187; Wed, 27 Sep 2017 06:35:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506519331; cv=none; d=google.com; s=arc-20160816; b=A0mNY4bdPXaSv1g0zqXidsGq4Y/AHpeZX4Vmw7QWJsjBVDZAIJSdhShp2fbiGFpS8U udo48BMSE3glCFQuwjWKtD/0/eANByYksxzu6w0prAqxh3wn3w7/xNAIIG75BzOMpBKl Lb/SFSxRhhn0RJO8fRNArXkP0rVz4fb1fB5PRF8nDYKZ6oQ/cYTmrI7matWCNFrQmaQU 77d4+fq1WS0/yB8o5dXvZK/JI1tnwWfXBRyPKHQuIq0zBBae6PjGlSv22FD0muvk+moX Sh3jUBASdtTe3hrVvubuRrGvnNAspJEeGzpepmbUluO/pyt18eLEqn26vdIgEyartI5g h3hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=W+Tcl4cJrx8e9pLSh/CbEoTTOUTf/RWW0Usaydp5qhQ=; b=eq1Hi0TxSGvKcSVCIFG+UGkS6WXJWj9OQ3Fr69lcGK5GZt0AOCf7KY8O6xXwL9IQjv JwSlA7On3/haGVbvnA+w+Gs70keoDThl5ngZ2l5WXg+dz5TtCItQIM2xUUNm8SqMEW2o L6pU2sIATN5thDIsJMdiPyDObsdJ94BnqDT0EAhw4YCunbrqmoNEYrrdRAOfNWRvUGVl 1ckaD8C6jzLmZUudSEx7wvg7oie2X11Z+AS2Xs86XxUI+fVUUlQeySLoMkLa+Q68ceUm oZ+ryIJoSghHHhbem1AJXswUoTuz96d0R0ZIsrBeO43xp0RD74TQ7pXbdJifzpAMLqrU 4WcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u9si7660961pge.139.2017.09.27.06.35.31; Wed, 27 Sep 2017 06:35:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752694AbdI0Nf3 (ORCPT + 7 others); Wed, 27 Sep 2017 09:35:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7451 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752654AbdI0Nf2 (ORCPT ); Wed, 27 Sep 2017 09:35:28 -0400 Received: from 172.30.72.60 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16880; Wed, 27 Sep 2017 21:35:26 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:35:19 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v8 5/5] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 27 Sep 2017 14:32:41 +0100 Message-ID: <20170927133241.21036-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59CBA91E.014B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 13930aa6bc8fa600b0b18dc8ba8d5de5 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e67ba6c..fb7f08d 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -413,6 +413,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define SMMU_V3_GENERIC_ARM 0x0 +#define SMMU_V3_HISILICON_HI161X 0x1 + /* Until ACPICA headers cover IORT rev. C */ #ifndef ACPI_IORT_SMMU_HISILICON_HI161X #define ACPI_IORT_SMMU_HISILICON_HI161X 0x1 @@ -608,6 +611,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -696,6 +700,8 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) static void parse_driver_options(struct arm_smmu_device *smmu) { int i = 0; + const void *data = of_device_get_match_data(smmu->dev); + u32 model = *(u32 *)&data; do { if (of_property_read_bool(smmu->dev->of_node, @@ -705,6 +711,11 @@ static void parse_driver_options(struct arm_smmu_device *smmu) arm_smmu_options[i].prop); } } while (arm_smmu_options[++i].opt); + + if (model == SMMU_V3_HISILICON_HI161X) { + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; + dev_notice(smmu->dev, "\tenabling workaround for HiSilicon erratum 161010801\n"); + } } /* Low-level queue manipulation functions */ @@ -1934,14 +1945,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2693,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; } @@ -2862,7 +2889,9 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev) } static const struct of_device_id arm_smmu_of_match[] = { - { .compatible = "arm,smmu-v3", }, + { .compatible = "hisilicon,hi161x-smmu-v3", + .data = (void *)SMMU_V3_HISILICON_HI161X }, + { .compatible = "arm,smmu-v3", .data = (void *)SMMU_V3_GENERIC_ARM }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match);