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Fri, 7 Aug 2020 13:31:52 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20200807133152eusmtrp291df7c879e5fe91a3d49c385b6d697da~o-5vhtKoj2793327933eusmtrp2C; Fri, 7 Aug 2020 13:31:52 +0000 (GMT) X-AuditID: cbfec7f5-371ff700000018ae-2a-5f2d57c939e2 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id F6.41.06314.8C75D2F5; Fri, 7 Aug 2020 14:31:52 +0100 (BST) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20200807133152eusmtip156850caddd730172b857bff4c6efdf91~o-5vCOG_F0331303313eusmtip1C; Fri, 7 Aug 2020 13:31:52 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Lukasz Luba , Stephen Boyd Subject: [PATCH v2] clk: samsung: Keep top BPLL mux on Exynos542x enabled Date: Fri, 7 Aug 2020 15:31:43 +0200 Message-Id: <20200807133143.22748-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNIsWRmVeSWpSXmKPExsWy7djP87onw3XjDSZfE7bYOGM9q8X1L89Z Lc6f38Bu8bHnHqvF594jjBYzzu9jsljY1MJusfbIXXaLf9c2sli0P33J7MDlsWbeGkaPTas6 2Tz6tqxi9Pi8SS6AJYrLJiU1J7MstUjfLoEro2f3BbaCb5wVj87NZ2pg3MLRxcjJISFgIrHz 1hTGLkYuDiGBFYwSP64sg3K+MErs75nEBOF8ZpRoOP6fGaZl2vWDrBCJ5YwSGw51s8O13L23 gAmkik3AUKLrbRcbiC0iECOx6/oRsFHMAiuZJF6cug9WJCzgKfF4WwcriM0ioCqxoWMtC4jN K2ArsevgXEaIdfISqzccYAZplhB4zCaxbdFfVoiEi8S0P4+gbhKWeHV8CzuELSPxf+d8JoiG ZkaJh+fWskM4PYwSl5tmQI21lrhz7hfQfRxAN2lKrN+lDxF2lJh+bzYTSFhCgE/ixltBkDAz kDlp23RmiDCvREebEES1msSs4+vg1h68cAnqHA+JvYfOgNlCArESS9uOMk1glJuFsGsBI+Mq RvHU0uLc9NRi47zUcr3ixNzi0rx0veT83E2MwCRx+t/xrzsY9/1JOsQowMGoxMP7w1c3Xog1 say4MvcQowQHs5IIr9PZ03FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeY0XvYwVEkhPLEnNTk0t SC2CyTJxcEo1MAq9qlr8aGuQkmaSRJnbm18/7jR1ZL/8OfWrAEez8h+DGIVAIWmRGoUkgUDW G4dDpBt35wr37zhi6iJXdf5c1fbgsya/1m7WVz3YGzX9w9QdfJbzZs7simNbGD7tqi7r7qOb mfsf3M3YuWuh3yR1D9dfhbLmKe/m/pwiznxUYdOmAtU1ocHtC5RYijMSDbWYi4oTAZts6goO AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsVy+t/xu7onwnXjDd78NbLYOGM9q8X1L89Z Lc6f38Bu8bHnHqvF594jjBYzzu9jsljY1MJusfbIXXaLf9c2sli0P33J7MDlsWbeGkaPTas6 2Tz6tqxi9Pi8SS6AJUrPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1 J7MstUjfLkEvo2f3BbaCb5wVj87NZ2pg3MLRxcjJISFgIjHt+kHWLkYuDiGBpYwSDecaWCAS MhInpzWwQtjCEn+udbGB2EICnxglNv5kBLHZBAwlut5CxEUE4iSedN9nArGZBdYySdy5JQ9i Cwt4Sjze1gE2h0VAVWJDx1qw+bwCthK7Ds5lhJgvL7F6wwHmCYw8CxgZVjGKpJYW56bnFhvq FSfmFpfmpesl5+duYgSG5bZjPzfvYLy0MfgQowAHoxIP7wJv3Xgh1sSy4srcQ4wSHMxKIrxO Z0/HCfGmJFZWpRblxxeV5qQWH2I0BVo+kVlKNDkfGDN5JfGGpobmFpaG5sbmxmYWSuK8HQIH Y4QE0hNLUrNTUwtSi2D6mDg4pRoYrSerfjH0DAnjjhN6tjHqr7nHfb15Ho6udvLdZ233VNaf iZ9vteXGNDf3mUZHXBVNHRKkXGxcFwccOGN36+RtVuN+zSmfmPLkLljYMpgzfQn2+yv0bZ6b r88Z07j62sap3DsUbC+uXXb2O8v/jETm/dJOZgZz427VtRkvdKh/qiEpP0NkmqESS3FGoqEW c1FxIgA7QsgTYQIAAA== X-CMS-MailID: 20200807133152eucas1p1d83611a984f5c5d875192d08e2f5711f X-Msg-Generator: CA X-RootMTR: 20200807133152eucas1p1d83611a984f5c5d875192d08e2f5711f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200807133152eucas1p1d83611a984f5c5d875192d08e2f5711f References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org BPLL clock must not be disabled because it is needed for proper DRAM operation. This is normally handled by respective memory devfreq driver, but when that driver is not yet probed or its probe has been deferred the clock might got disabled what causes board hang. Fix this by calling clk_prepare_enable() directly from the clock provider driver. Signed-off-by: Marek Szyprowski Reviewed-by: Lukasz Luba Tested-by: Lukasz Luba Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5420.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 Acked-by: Chanwoo Choi diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index fea33399a632..521cbbfc0987 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(struct device_node *np, * main G3D clock enablement status. */ clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + /* + * Keep top BPLL mux enabled permanently to ensure that DRAM operates + * properly. + */ + clk_prepare_enable(__clk_lookup("mout_bpll")); samsung_clk_of_add_provider(np, ctx); }