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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Riku Voipio , qemu-devel@nongnu.org, Laurent Vivier , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- linux-user/main.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier diff --git a/linux-user/main.c b/linux-user/main.c index 829f974662..5072aa855b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3854,6 +3854,11 @@ static void handle_arg_log(const char *arg) qemu_set_log(mask); } +static void handle_arg_dfilter(const char *arg) +{ + qemu_set_dfilter_ranges(arg, NULL); +} + static void handle_arg_log_filename(const char *arg) { qemu_set_log_filename(arg, &error_fatal); @@ -4054,6 +4059,8 @@ static const struct qemu_argument arg_table[] = { {"d", "QEMU_LOG", true, handle_arg_log, "item[,...]", "enable logging of specified items " "(use '-d help' for a list of items)"}, + {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter, + "range[,...]","filter logging based on address range"}, {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, "logfile", "write logs to 'logfile' (default stderr)"}, {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, From patchwork Fri Oct 13 16:24:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115784 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp918111qgn; Fri, 13 Oct 2017 09:25:30 -0700 (PDT) X-Received: by 10.55.109.195 with SMTP id i186mr2824116qkc.147.1507911930370; Fri, 13 Oct 2017 09:25:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507911930; cv=none; d=google.com; s=arc-20160816; b=YjDlAd9QBgqxNnqcdkjyPB8O8ukukrgLs2HeyPX+JdgEcmMA1fx3lNHvkXqgOvmDG1 CksIroL2DhjPzXeljMa1yU1kEKUDZF2Eh3KPuNcXFN6n3hKv/bX3EwS19rd0onjAsS9n eGJMs8svDAoCZznQ2KvINDDbwxoFANyBpiMGFztzn7fxkb1Lt7mL8/kBEe3mXCy1JfIX dsykitXAsOHuJoh+gk6Tq+1BrRKoju3wEHgkrLlTtWxDaXaWqoKo6yiqWDUVnGLqKQZR lXgFOWQLQKlJZ+o9DrqUlPq00N2EeEE9/OvNOdagGzlliCv8NVKqqGmTTlA/hwCHi8uK ehPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=i94aSXWM8jvmZsWcCUdhzW0nGXo062r23fZ6DTOQKzM=; b=LZl1jrMQwgHFdaZ51n+CCIh47k+bD+rOVqeARdiSzDldtIb8DGXwmXO04nv6Wzju0W zhxJX+Nsl/j7hm8cHfABxVx27u/NaBqdVyuW2cApEcKOp4GmDyS8MSW1Tij5/CDC7zVz kcpEquGeVC7YdonZBL5i0wwvGs3f/mTGcP9UOWEXhudPhd1RWuNPWOzouv2aFBRwBzXq RL4GkUxhfeIlMR2nspwiw4TTtHja7FeMhukSzt+tjnGZ28iRH6+5f5DRE+26/VqYSOnI E9jXylnvtyhs7e3DzQICR6qGesqKGCKEsrzzYkS3i/ETeBQ+m7agcuU4IAtVUHkpZbmN UTgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SaZrodnc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cdcb2..3a0f27c782 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1340,6 +1340,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..973614dfc6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } From patchwork Fri Oct 13 16:24:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115787 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp921726qgn; Fri, 13 Oct 2017 09:29:25 -0700 (PDT) X-Received: by 10.237.36.88 with SMTP id s24mr3063344qtc.229.1507912165701; Fri, 13 Oct 2017 09:29:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912165; cv=none; d=google.com; s=arc-20160816; b=m+66QzyOtdUkc4KVeHQ/FKtDoM/Uoh+ZlTwymthcH8aOEpV2p41VrvrkXX0X2bKNpl UpzQESP3mZda3/ekGRLYi28KB+rHZ0e9Nlx3BQGgU0w9gyAQOLZ4uCbIew4ZMKF1vVVK 0UbJJ5PZNDiuML0mcbNbJL54eMGweJYpuR/QiUjRlPxv5DoDAVW9COjTUGmUyKaNJg4B qySK+KhU4qc5KdN1uCdWIjpOaVJnkmnu//syidqeRyjyyd1xzPRLPkWIwQXep0TdvOfp WZLKApoGISrnMjKqUwm7M0CIkC3Vu44zwQcfkL3kW1NCJzWY/OJO9DIDUKyV0WRAr1Cz 6fng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=V9B2d5WwG5cqQuLL/WdKgeSi62ZHgTXcGwcR4BXi8ts=; b=BDRryujLS4H9Cxj68H27vlho/D1X26XvGDVgmacDRMGBo7+d5AUA0FYBE412jmWtPJ eTQNRz1AJMG3shJYHLgfiDBytxdvTFljJBFFQB/bAwK3qfCwuCWCuA2eCTaRRd2mf8eM MzfFKhmf2SC/Q7x9fMtXvbIcAwBrZ/OfMUpO6QTppWVCuinyKVM0Va+Z57bP3Jn42QpQ YkbKW4LWT4TScrhevTp1WCoV017wUR0QAUlIcdUQPjLNDKHTYDWso3ZmMU+PaKX5PJPZ DfiIgafSRHh6QhsH4lwy9b5W4TBK2ZN07mjyL9JH6QZDnknNKmsKBBK43vUueRzZJLdW C64Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C2wZ45fE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Bennée --- include/exec/helper-head.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 1cfc43b9ff..fdb82151d3 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -30,6 +30,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr @@ -42,6 +43,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_f16 float16 #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * @@ -98,6 +100,7 @@ #define dh_is_signed_s32 1 #define dh_is_signed_i64 0 #define dh_is_signed_s64 1 +#define dh_is_signed_f16 0 #define dh_is_signed_f32 0 #define dh_is_signed_f64 0 #define dh_is_signed_tl 0 From patchwork Fri Oct 13 16:24:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115783 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp917906qgn; Fri, 13 Oct 2017 09:25:16 -0700 (PDT) X-Received: by 10.237.35.151 with SMTP id j23mr2927794qtc.96.1507911916073; Fri, 13 Oct 2017 09:25:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507911916; cv=none; d=google.com; s=arc-20160816; b=XQISW8d9YdrwSRPk2PqiDfi4rKnrYVhC3E62iELTTi+65RogQHT4BLc+WtJ6EZqNHH CqvKkMMxJHMcWU+dRdutZEhE4cHM6ndwjqMJTAz1/gEmfbXPtR1epNUDjmXA0t6vC6Ja NpnMaqiFlpK3p2fv58j7tqPVp/tLmD2Eg+Dw+oaGKmIn6FNCion3T0kCwFiGLdyt54Ug KhmS4hBdCSRsdTCtnkro05+nUWSw6a5YsI/nQrkgej9LK8CCe/Sr3RempmTNQ9pWjh/J skFvARws6iQjlKDYoea4IcdA5dDAwMERMuKUAHxHUN0OThLDRGg34c9JbF30bRENcTv4 Y21g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=U/1sagJWWnbpr+LHtke20CA0+z5ItCTw37KNEr04Ng8=; b=UVPLLEQTzHyrueqU6seKMqWSkHrBfpC8FYekVwRTAaXN73WHmVR7KbazrV8tNGHa5t Tgt6Wz/hxKiSTkN4MaD0GUot+EUjWTdAZgBz1tfLcIQ0fxCGEh8fgRH2YZhKWUBHOOBy vbu315BGpI00oL1A1EwnMSwbSeund1tVBrr2Jm3IJx5+mvRc8bXnuvZb5E3p3vVzcFwE ZrScN0b8Ojk29+t68J4N4HpJOVXbdkhr9nrmrRdcRxcMugPBj2FIUpz6INsuAxkOsOeI FLz1OFgZtStdbkec6hlFohtACkOEuJE3SqXTSTxgLeq3NND7V4os6jyOF2mBVWcauhOI rKOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SUqz/46b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::232 Subject: [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3a0f27c782..521b82d46e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -488,6 +488,7 @@ typedef struct CPUARMState { * Qn = regs[2n+1]:regs[2n] * Dn = regs[2n] * Sn = regs[2n] bits 31..0 + * Hn = regs[2n] bits 15..0 for even n, and bits 31..16 for odd n * This corresponds to the architecturally defined mapping between * the two execution states, and means we do not need to explicitly * map these registers when changing states. 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X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée --- fpu/softfloat-specialize.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index de2c5d5702..c8282b8bf7 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -685,6 +685,49 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, } #endif +/*---------------------------------------------------------------------------- +| Takes two half-precision floating-point values `a' and `b', one of which +| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status) +{ + flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; + flag aIsLargerSignificand; + uint16_t av, bv; + + aIsQuietNaN = float16_is_quiet_nan(a, status); + aIsSignalingNaN = float16_is_signaling_nan(a, status); + bIsQuietNaN = float16_is_quiet_nan(b, status); + bIsSignalingNaN = float16_is_signaling_nan(b, status); + av = float16_val(a); + bv = float16_val(b); + + if (aIsSignalingNaN | bIsSignalingNaN) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return float16_default_nan(status); + } + + if ((uint16_t)(av << 1) < (uint16_t)(bv << 1)) { + aIsLargerSignificand = 0; + } else if ((uint16_t)(bv << 1) < (uint16_t)(av << 1)) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (av < bv) ? 1 : 0; + } + + if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, + aIsLargerSignificand)) { + return float16_maybe_silence_nan(b, status); + } else { + return float16_maybe_silence_nan(a, status); + } +} + /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a From patchwork Fri Oct 13 16:24:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115788 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp921841qgn; Fri, 13 Oct 2017 09:29:33 -0700 (PDT) X-Received: by 10.200.50.230 with SMTP id a35mr2893794qtb.226.1507912173247; Fri, 13 Oct 2017 09:29:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912173; cv=none; d=google.com; s=arc-20160816; b=lHBiagSjLf52EEwoJeLyG1Ci8JjsgcK2vlCj1UKyV93O4hF94HcJqDC6HoEv7BG+S+ vFaddZ//N4JBjAbOMA5//WGt9ab/1MJHnvboz/P4bhVXrxiQa9Krbda+q1B45kGLupbj I8nDdy4M66lQH8QAcysNe7RpdkAHOVTjqxfjQbxW89DSq19LshQjf75UEP+p8rjdfMnv BJ6hFJX2O0lhOs8JJGje/v3h1wuNZY4tQ6+J1LygmlPVNaNziGK270zKXeNw/GDNOkYU gH3XF+Drrg92oTLk94js3Ss1iBSnYmAXDsby+k+iqwvxw+aiPyBTBXNpHC8eG4ezhHAX Q+ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/ILSMgJPmHL8NTcJ6LKg/3Dh7htBXoyvVG+Xzv5BpWM=; b=zL4XDdu2tpuMxBB+1DP2aHNi+Ma6fT/7uQj+I0e3cSz+UjMlkoAW+pWroYf55vqKIh SIfEfPg234aPllPwRyHJyRVTPSd5hVuWRbjJSEoWqNShTxHft1a/hTUnJCVdhcf57zb4 bZuGv7wQJ9565RLcJPoYGpDmNvPridy+0LgM41LozaImtAIA3rqOQbbTnkpSDWvkFO9w Y5ot7oXghjWkFt7/kErf/GQbR236OcC00xg2ib6aMJOYJGLd6dg0ExHS5V66qJvh0Dqp 8vbv8eLyj5HN3FjAv1kTL+SU6dUbZ0/DjQsrtCAN7emNvsrzrXcjp8LznSpUD8oArCW3 usRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RLPZZY0c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 15 +++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 16 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5dad2d..3a4ab1355f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,21 @@ static float16 roundAndPackFloat16(flag zSign, int zExp, return packFloat16(zSign, zExp, zSig >> 13); } +/*---------------------------------------------------------------------------- +| If `a' is denormal and we are in flush-to-zero mode then set the +| input-denormal exception and return zero. Otherwise just return the value. +*----------------------------------------------------------------------------*/ +float16 float16_squash_input_denormal(float16 a, float_status *status) +{ + if (status->flush_inputs_to_zero) { + if (extractFloat16Exp(a) == 0 && extractFloat16Frac(a) != 0) { + float_raise(float_flag_input_denormal, status); + return make_float16(float16_val(a) & 0x8000); + } + } + return a; +} + static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, uint32_t *zSigPtr) { diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 0f96a0edd1..d5e99667b6 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -277,6 +277,7 @@ void float_raise(uint8_t flags, float_status *status); | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. *----------------------------------------------------------------------------*/ +float16 float16_squash_input_denormal(float16 a, float_status *status); float32 float32_squash_input_denormal(float32 a, float_status *status); float64 float64_squash_input_denormal(float64 a, float_status *status); From patchwork Fri Oct 13 16:24:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115792 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp924707qgn; Fri, 13 Oct 2017 09:32:19 -0700 (PDT) X-Received: by 10.55.23.160 with SMTP id 32mr2566293qkx.20.1507912339151; Fri, 13 Oct 2017 09:32:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912339; cv=none; d=google.com; s=arc-20160816; b=a2+kZAvPFwcWY2cIYILfQ+Zgmg0bltAmPopejgmxw4bdMaGKiaIGTBoPsVpT3j9XLh amTn8PMPXzXi3g6+xlfUuhAf/jQ0lMeegnSuxTmNI1NZZee4+ybJUwPo55tzn6ginzUR V5FqDoex29CSbaM0AMjCDBxLBG6x31ZzQA1J0X3mKhCJOBiGgZ1qjFcEyexoX3kG/yY6 dQEJK8BHAStEODxaQZ2ZRL/SULx6Rpr6vo6M72O9cn1E1/5rQFWThZ3m3hzVZY5uWni6 3ZiE1gvpgCuDO+0saQwNO6olS8FAzgxC38xAgW3AROSPexe+1KQDOV+5nMJ592W1bHWH X4Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uzu0EfPAl6ZQEQsG6fFZRrif6loBpwApnK+pLYxHuaw=; b=Tq2FHot7lH1ldVHmAG/2rFQSQU5f+yf2whBaZMCj223sGQJvgyUdX5TnUaK4/U5LTF xJxUqCBaJcXcOzkZ5w6bQWDBzeKbrwzgjdYEMmzYX4EViD8rpYdbJhJnoscF/V2csdoN 6ccyqVMcr2jopjvAj0uDGfB5i5/3QVdM9xCT2RBH184gurglVIYTFeZfPmZMNhAHOlnP 0e9IJV8RgG7nArJOf9fH1tRal8aH1mzQUb+B1GGwYbU5gmCyLsCY4gMdbkWpz1YhJhA6 PxKJoAIaHtyzDR43HJ8R4f+QGJ+IpCTCDxkbRmlpkEkfuk62q9i5aDQkpGC5EuppeqdF oVYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PUWf2U92; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22c Subject: [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée --- include/fpu/softfloat.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d5e99667b6..edf402d422 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -374,6 +374,13 @@ static inline int float16_is_zero_or_denormal(float16 a) return (float16_val(a) & 0x7c00) == 0; } +static inline float16 float16_abs(float16 a) +{ + /* Note that abs does *not* handle NaN specially, nor does + * it flush denormal inputs to zero. + */ + return make_float16(float16_val(a) & 0x7fff); +} /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ From patchwork Fri Oct 13 16:24:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115789 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp922065qgn; Fri, 13 Oct 2017 09:29:48 -0700 (PDT) X-Received: by 10.200.38.194 with SMTP id 2mr2760533qtp.196.1507912188025; Fri, 13 Oct 2017 09:29:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912188; cv=none; d=google.com; s=arc-20160816; b=l2cjcCs6X/WNEJF3Jj+sGtvw0lfB2YbfHrQyIZ71d6rOo4sMeiUSW1tcSbWwTHZNp8 xqKx11MKlc412u45VBdwaAV+OgK4+OTK5SGJKilM1tPIL2j6NHsuqVBB+uyL1/nPwEAH 9DV7pNvhy6tjBC15RKtdWjNlm8RubEplb+SATxHszzMFZNT+OPRvuAFI8Sk3SzEyJSMu YoIqjeV9yhoAI4fOXyBW0v6q7zSiwhTXaCsTqDPmaICY92AVtFETVssAifUTvjIBWg+y 6u0EjAoRD/ULf4NdFKMKTkruDAWREj1RVtWJhGyHSD5eMIMXB1JksBL0BkYbhycvmWDH nTag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YNYltpURvYkc94gBhiDKkKFxSym98VonnTpWX1QJW2o=; b=RalJS5wGh3ryBOhqbYhLJxKuaiXBIarJfzXSx88WsHVgVyviw3KtA+W1jay5Zxv/lJ K2//KZ5IaGY20S5UiJkaEMmrltEnBIHBbdUqyQuol7jGdTs7e8ahcWcj7pmb9r+YS2aZ hd8nYk+R21m3DqlYJRQs6REEnoErMwLarj0mO9AeDq8RWFcp1LrXMAU6ToBAdmrecHZ4 60NVS/vuK0Hxa3/3vj/yMqAyBRDusk8bHfpQNgcWLELX1PS6oeSJZ4whY3VNeO2hoQhz N2XVhizDcx/bSv02rNmOFdUnzQ4TCnZgj3EV74/G/G5PbMyOy57G5rVqtlenHkBGaN7s +YhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AVq/h3pn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Expand the current helpers to include half-precision functions. The includes having f16 version of the compare functions. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 2 ++ include/fpu/softfloat.h | 11 +++++++++++ 2 files changed, 13 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3a4ab1355f..013b223947 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7579,6 +7579,7 @@ int float ## s ## _compare_quiet(float ## s a, float ## s b, \ return float ## s ## _compare_internal(a, b, 1, status); \ } +COMPARE(16, 0x1f) COMPARE(32, 0xff) COMPARE(64, 0x7ff) @@ -7779,6 +7780,7 @@ float ## s float ## s ## _maxnummag(float ## s a, float ## s b, \ return float ## s ## _minmax(a, b, 0, 1, 1, status); \ } +MINMAX(16) MINMAX(32) MINMAX(64) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index edf402d422..d89fdf7675 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -381,6 +381,17 @@ static inline float16 float16_abs(float16 a) */ return make_float16(float16_val(a) & 0x7fff); } + +/* Expanded by the MINMAX macro in softfloat.c */ +int float16_compare(float16, float16, float_status *status); +int float16_compare_quiet(float16, float16, float_status *status); +float16 float16_min(float16, float16, float_status *status); +float16 float16_max(float16, float16, float_status *status); +float16 float16_minnum(float16, float16, float_status *status); +float16 float16_maxnum(float16, float16, float_status *status); +float16 float16_minnummag(float16, float16, float_status *status); +float16 float16_maxnummag(float16, float16, float_status *status); + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ From patchwork Fri Oct 13 16:24:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115791 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp923162qgn; Fri, 13 Oct 2017 09:30:49 -0700 (PDT) X-Received: by 10.55.98.206 with SMTP id w197mr2632093qkb.292.1507912249162; Fri, 13 Oct 2017 09:30:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912249; cv=none; d=google.com; s=arc-20160816; b=aliO0h1LM5glqyOsRvYgAOHEFSieVrmDyD1eq43nxufWQKpBHnBDcqf7aIlYblvgjs BTuT8MjN2KJz3sPQcYsTuvKjmNRbwSYo75PNBKhl4OjXqCg/CTKmDH2wrR1qnDIOmpE0 amIuxwEbn0iD3rI8y8VN2PVHKhKqRv0mAgmMEAf0Ct0Q1vYYa4dysSQIpFH0B5OrQjCn 2j3nH4lutuaeDC9L/+REqr52KYAp8KVXsxoEqQkxaLOhXUDvJDWf3j8D50rKDPlhBc8g MwIV3z/ZHbhkn9YzBRoMlbi9TxEiFe/UMM1rHZJiRZFxukjDP58pg+i6aSfgf3m7KGgR b0BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HeMI3G4s0BPN1NotGhq0tBi6MXXSlwpVMAwWeGBeoTo=; b=QRGoE4sdKrt4ZCSwGfC9VbeyHfoAjklOKvzOqJKAff3v1MGohd6TsU6Ws8V7qdLUON nCUVhtTKCOgu1Jmr2jiF+1RIKRR9Rj/xCTcOpfiYpz4v5InXSN7G8A97veBLnP/SKs+G p7EoXcBLZ4k9tXjY1df2W8sf+vCkpF+RxIqjZud6BnA6GBiVLmwv2WAryJ4vofPe4BTF cvcVS2Uhwv4xc0/l88eYrlHlUOFy6t5+CMuEUj/hAnSfDOpQh+j6eB636GF2+kkgJZg3 d0S8eTbm3ZeM0XKToBswTjYe0qE5EBm0H+iD8UQ9NOcLVCOdAPkMUJN4nV4MKd2X4N3D pCzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QpslxyND; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While a comparison between a QNaN and a number will return the number it is not the same with a signaling NaN. In this case the SNaN will "win" and after potentially raising an exception it will be quietened. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.14.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 013b223947..6ab4b39c09 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7684,6 +7684,7 @@ int float128_compare_quiet(float128 a, float128 b, float_status *status) * minnum() and maxnum() functions. These are similar to the min() * and max() functions but if one of the arguments is a QNaN and * the other is numerical then the numerical argument is returned. + * SNaNs will get quietened before being returned. * minnum() and maxnum correspond to the IEEE 754-2008 minNum() * and maxNum() operations. min() and max() are the typical min/max * semantics provided by many CPUs which predate that specification. @@ -7704,11 +7705,14 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \ if (float ## s ## _is_any_nan(a) || \ float ## s ## _is_any_nan(b)) { \ if (isieee) { \ - if (float ## s ## _is_quiet_nan(a, status) && \ + if (float ## s ## _is_signaling_nan(a, status) || \ + float ## s ## _is_signaling_nan(b, status)) { \ + propagateFloat ## s ## NaN(a, b, status); \ + } else if (float ## s ## _is_quiet_nan(a, status) && \ !float ## s ##_is_any_nan(b)) { \ return b; \ } else if (float ## s ## _is_quiet_nan(b, status) && \ - !float ## s ## _is_any_nan(a)) { \ + !float ## s ## _is_any_nan(a)) { \ return a; \ } \ } \ From patchwork Fri Oct 13 16:24:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115790 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp922134qgn; Fri, 13 Oct 2017 09:29:52 -0700 (PDT) X-Received: by 10.55.24.73 with SMTP id j70mr2520501qkh.310.1507912192412; Fri, 13 Oct 2017 09:29:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912192; cv=none; d=google.com; s=arc-20160816; b=eG7waj5tljyAeiKwcYgGnh0288ZsPf10+cMOjG9gU8/cazSYnC7xTPpJNYgdJqmvmR cVEpS9vIxbbPF0z9yXIvWLboromsEGspCDBQtHk2kLCqt6RIDEBpYD/N7pKHRnf0pZck GjJyxh71cZnXTQ4XMVvJPFATm5ayDTgHOIM5ayw9r1b/8WcY6Ph8dwJGqT5LeYNfFIJ5 nicTbJQOLNPmUidRHA46w6evRq/aDzixv1yjebLzZb4iJ6U/IoJ48ClN8zPZW9T58Pmx TKtciGl4ck2rO3UTEo4zzt97jkcOfRgYzjGec+ejgKmlQ6pN5+J+dQV0FklCqUc/5Rz/ W7Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mOzMaLth9wCvMkVFiw3xeor0i6CYV3CwTGYP8bXsncg=; b=NR1OSCtRT+yVM15vruWad1zqegCmfe+EpHlYoooB7/GpaV806f8HqJpQXvRM0a3yl9 ZZFxeImxO7n9tZg9/HCcvjQjh9kUlNpYOAKogPJAOd9xcagNOklX0GE8O9ke17mezIIl U+z82Wbxo5/g+qrp5dLvyUNuCq/Iv051lwWT5tvPnyjQUdgF/UEPmMTpQz2GsCidZsl9 PWUdk+AEqMF2DQ+owM4qKyrguB+0Nt6UMZRODK725SHgyfPR3AjLx6MdDHO8CbssEVSA wp5pF5hTLxbOijppX2s88hg3FIEqjXUrUMnOzwzGqg/CJiU5SpMQl/d8PR85q9PEs3Vx KN7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CFp4wIid; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mention the pseudo-code fragment from which this is based and correct the spelling of signalling. Signed-off-by: Alex Bennée --- fpu/softfloat-specialize.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index c8282b8bf7..2ccd4abe11 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -445,14 +445,14 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) #if defined(TARGET_ARM) static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) + flag aIsLargerSignificand) { - /* ARM mandated NaN propagation rules: take the first of: - * 1. A if it is signaling - * 2. B if it is signaling + /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take the first of: + * 1. A if it is signalling + * 2. B if it is signalling * 3. A (quiet) * 4. B (quiet) - * A signaling NaN is always quietened before returning it. + * A signalling NaN is always quietened before returning it. */ if (aIsSNaN) { return 0; From patchwork Fri Oct 13 16:24:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115794 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp925192qgn; Fri, 13 Oct 2017 09:32:48 -0700 (PDT) X-Received: by 10.200.43.120 with SMTP id 53mr2994018qtv.127.1507912368824; Fri, 13 Oct 2017 09:32:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912368; cv=none; d=google.com; s=arc-20160816; b=fy9mKkJnCQz6dVxnc6C0Dzz9K0zzEW9EAfLQ5QS6o87SV3XH+1bu2cgJZ17Gk8XXGg 0fLKbRvcpnwfN/KioTUXUx4zRiA5fJ7H969dh+AbpFy4xxeVJoA4rEjQ2ODMZGF8e2xF m4Fmt9wcmodHEbkOkCqaokvTwCZ6LeJvip8IeTbbulk0Dkfoa072D+r6G1PGZg+m58oo 3HxgmGUC/k17GZj4dXqi/zRTFZbvY75AYvQDWgZVmi89+sdkx3KJIuC7Qj18d3Gsp0FA fhje3ecpiLkKQW/AWYvitcUXo5iRlUqLtooB5hubhmgy31lwaoSmBGnDCThzAEVnVjyI i+KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Bkb/DAK/MhmwL4UQX64YPV883SIsP4TZw8zxphtUdEw=; b=x+GAw4G8/oXnb0JLswyyrXosU32WcMtT9S58LNSA0561eSBAgSwL9TyXgbPMZwnv4o 8Ob3ix+t+NmyiRB/qMw0/L/W4IQAZSdZriCJ2Sn6l2weuVi5EIQI3GLYe6J2xeR+dRaC QoeN1gAy0k/izmmJh18dagGXRaAxg4rvotwBS8YxNRC+Bj0obGrO1oZMrgNPdm/rnv2Z eG+Oi19g7WK+Fk+LrWmViXarDlVW3n0TZImGMEB2vgrGsvpI8LY0gXB52dFViHuxaYU/ UzjC+04TTowLY9KjNr9rgZcSRuuc3cTa0uoMykJICyTFLRBNdfiVgTcLewxlHH0eJBzv ORqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dOFfXf0k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::233 Subject: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée -- v1 - dropped the advsimd_2a stuff --- target/arm/helper-a64.c | 18 ++++++ target/arm/helper-a64.h | 4 ++ target/arm/translate-a64.c | 147 ++++++++++++++++++++++++++++----------------- 3 files changed, 115 insertions(+), 54 deletions(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82cff5..a0c20faabc 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -537,3 +537,21 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, return !success; } + +/* + * AdvSIMD half-precision + */ + +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) + +#define ADVSIMD_HALFOP(name) \ +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ +{ \ + float_status *fpst = fpstp; \ + return float16_ ## name(a, b, fpst); \ +} + +ADVSIMD_HALFOP(min) +ADVSIMD_HALFOP(max) +ADVSIMD_HALFOP(minnum) +ADVSIMD_HALFOP(maxnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba533..b774431f1f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,3 +44,7 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a39b9d3633..1282d14c58 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5602,26 +5602,80 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resh); } -static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, - int opc, bool is_min, TCGv_ptr fpst) -{ - /* Helper function for disas_simd_across_lanes: do a single precision - * min/max operation on the specified two inputs, - * and return the result in tcg_elt1. - */ - if (opc == 0xc) { - if (is_min) { - gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } +/* + * do_reduction_op helper + * + * This mirrors the Reduce() pseudocode in the ARM ARM. It is + * important for correct NaN propagation that we do these + * operations in exactly the order specified by the pseudocode. + * + * This is a recursive function, TCG temps should be freed by the + * calling function once it is done with the values. + */ +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, + int esize, int size, int vmap, TCGv_ptr fpst) +{ + if (esize == size) { + int element; + TCGMemOp msize = esize == 16 ? MO_16 : MO_32; + TCGv_i32 tcg_elem; + + /* We should have one register left here */ + assert(ctpop8(vmap) == 1); + element = ctz32(vmap); + assert(element < 8); + + tcg_elem = tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, element, msize); + return tcg_elem; } else { - assert(opc == 0xf); - if (is_min) { - gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); + int bits = size / 2; + int shift = ctpop8(vmap) / 2; + int vmap_lo = (vmap >> shift) & vmap; + int vmap_hi = (vmap & ~vmap_lo); + TCGv_i32 tcg_hi, tcg_lo, tcg_res; + + tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); + tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); + tcg_res = tcg_temp_new_i32(); + + /* base fpopcode = 0x0c NMV, 0x0f V + 0x10 MIN, 0x00 MAX + 0x20 F32, 0x00 FP16 + */ + switch(fpopcode) { + case 0x0c: /* fmaxnmv half-precision */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x0f: /* fmaxv half-precision */ + gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1c: /* fminnmv half-precision */ + gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1f: /* fminv half-precision */ + gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2c: /* fmaxnmv */ + gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2f: /* fmaxv */ + gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3c: /* fminnmv */ + gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3f: /* fminv */ + gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); + break; + default: + fprintf(stderr, "%s: fpopcode %x not handled\n", __func__, fpopcode); + break; } + + tcg_temp_free_i32(tcg_hi); + tcg_temp_free_i32(tcg_lo); + return tcg_res; } } @@ -5663,16 +5717,21 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) break; case 0xc: /* FMAXNMV, FMINNMV */ case 0xf: /* FMAXV, FMINV */ - if (!is_u || !is_q || extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - /* Bit 1 of size field encodes min vs max, and actual size is always - * 32 bits: adjust the size variable so following code can rely on it + /* Bit 1 of size field encodes min vs max and the actual size + * depends on the encoding of the U bit. If not set (and FP16 + * enabled) then we do half-precision float instead of single + * precision. */ is_min = extract32(size, 1, 1); is_fp = true; - size = 2; + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + size = 1; + } else if (!is_u || !is_q || extract32(size, 0, 1)) { + unallocated_encoding(s); + return; + } else { + size = 2; + } break; default: unallocated_encoding(s); @@ -5729,38 +5788,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) } } else { - /* Floating point ops which work on 32 bit (single) intermediates. + /* Floating point vector reduction ops which work across 32 + * bit (single) or 16 bit (half-precision) intermediates. * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); TCGv_ptr fpst = get_fpstatus_ptr(); - - assert(esize == 32); - assert(elements == 4); - - read_vec_element(s, tcg_elt, rn, 0, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt); - read_vec_element(s, tcg_elt, rn, 1, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - read_vec_element(s, tcg_elt, rn, 2, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - read_vec_element(s, tcg_elt, rn, 3, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt); - - do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); - tcg_temp_free_i32(tcg_elt1); - tcg_temp_free_i32(tcg_elt2); - tcg_temp_free_i32(tcg_elt3); + int fpopcode = opcode | is_min << 4 | is_u << 5; + int vmap = (1 << elements) - 1; + TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, + (is_q ? 128 : 64), vmap, fpst); + tcg_gen_extu_i32_i64(tcg_res, tcg_res32); + tcg_temp_free_i32(tcg_res32); tcg_temp_free_ptr(fpst); } @@ -5882,7 +5921,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, { int size = ctz32(imm5); int esize = 8 << size; - int elements = (is_q ? 128 : 64)/esize; + int elements = (is_q ? 128 : 64) / esize; int i = 0; if (size > 3 || ((size == 3) && !is_q)) { From patchwork Fri Oct 13 16:24:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115798 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp931039qgn; Fri, 13 Oct 2017 09:38:26 -0700 (PDT) X-Received: by 10.55.122.135 with SMTP id v129mr2603605qkc.171.1507912706735; Fri, 13 Oct 2017 09:38:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912706; cv=none; d=google.com; s=arc-20160816; b=XzhQqjEepVqin0+YqwhtYlHcPE47bJAso+2GwyD9hHETSD96ta0ZbunvgZp8SCvFs/ t0pLeDRz1cK3EZWDkX78sQn2VtjCkgiJiNUhTZBHzMklYghEi8BsOrRYh9MKLwusGMP3 1/JVf/Ynu/pPqCtVOB6vlioyNcnsX+txXra5xSgVoSQYbNSIaCErLDR4Ukf5HwpYk+kv ex0wii94xmAv5+aWSim1BpQ/yVGVz/em/5879ZBHv/Qfd5OX6P1nZXyUEI/Xiis1zMpx w6UIPaKyhq3D5g+0RHQYdKdLaeNkTL3AbyW/0nWJGN52T5TJZpojvNyWoszOWCoLFR3o SlYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4bssyXsH/U9UMc4CIz9eLNvIqbTB2VIF8Y515Lq6qNg=; b=M4na7+vHtnZpsATU1qtyA0ELh7uTuI3sotDIb84XIcEbXu2mPpPn0SsUyRXx23C/sF AMXCMH40wImorFEXQzcSvO41SEDWfE01hhXgd9nISLfdq7TdXck4lcuJ+A0sacr+tgZk 0XI2e0uY7LdoIOAj/3y42EO1q4vC2zXDECx5m9wQf5TsUa5OqsP229S/Fxi2IXNgcru1 x9Rzqoz4R6+k3atA+TdZinFBnr04ESGd/niQOU2fo4rCMTVbIg5IlRZxN/2EErcXnaMO V21M0i+s+GHovXJIa5H3+MLRe46vBBPeNyCirojfp8CtCE4ZLWYGuoRUeTuDehsXr0gi ALXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Njkp3gUd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do implement all the opcodes. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1282d14c58..50e53bf8b0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7177,8 +7177,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, /* Handle 64x64->64 opcodes which are shared between the scalar * and vector 3-same groups. We cover every opcode where size == 3 * is valid in either the three-reg-same (integer, not pairwise) - * or scalar-three-reg-same groups. (Some opcodes are not yet - * implemented.) + * or scalar-three-reg-same groups. */ TCGCond cond; From patchwork Fri Oct 13 16:24:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115805 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp937060qgn; Fri, 13 Oct 2017 09:44:16 -0700 (PDT) X-Received: by 10.200.43.167 with SMTP id m36mr2769987qtm.174.1507913055994; Fri, 13 Oct 2017 09:44:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913055; cv=none; d=google.com; s=arc-20160816; b=HnMqckrJoisa4MjTtttAwWb1aJA4TgJ5aXs9EzEBVVlEuA0UyxZQdVX75UozPiXGLf MgihwoV+bZhmtaJ+CeuIQvhNc4uTu01DOFpJN78lYY0lznr0PTacfuHYfb0WypqkdzqM FMUeXPnxp5HTNAQT3fHliIPKUUM7HEM88FikRLuxDdtINB6NptTGHlBL94vEKxQo6CEF evNOnTi7fCp+26mcJApfkt2eu8mf/FBC8W/yGijcOXKsVpZx+idwz/OTNFBRzFToreu/ B8dsUhmhspk6KuKYYz/KbH80X/NbZQ51Q6VrzXBei19Ps6kxy4YaYqYsuidaDirHc7QO mKiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TKxk+a6SMfN5OFT+aCbP3LUxDsdDcUHvI4Ye9fChGlI=; b=ejgf9w7oEw5x8LvI/bTEh+41dDP8B2eKYlX73Fl/fMO+Mn7bP/nGiSKa8hRZ373Ctl hAAZ5P+f4LVA2e/YucQZstHlchQiHrJ1TWUEIfhR6d8UgOcXaTleVdjEfbeyFpFfFA4d 1e3ZQ/aNhsK/yqC6QfbiDUf8+xFfRAFl2PY8uOQGTgRmOJQZrgxqeBsfxeZz99B8Ti/r uOQdtbk2+TUYYZxWJ80pQ9Nma4Je4oGGr+LO9r09Yejgyf+7B1XSE0Bq43MypRH7KMVX NZj5SZcLD82BNBvFhojUQEhPLpRbcm5QK9Enw1pG1Tvk4qUTJWRrdk5ki9QQPAHQmBP7 sVDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PCoJH8J0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the initial decode skeleton for the Advanced SIMD scalar three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) -- 2.14.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 50e53bf8b0..5e531b3ae4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9751,6 +9751,81 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) } } +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode = extract32(insn, 11, 3); + u = extract32(insn, 29, 1); + a = extract32(insn, 23, 1); + is_q = extract32(insn, 30, 1); + rm = extract32(insn, 16, 5); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + + fpopcode = opcode | (a << 4) | (u << 5); + datasize = is_q ? 128 : 64; + elements = datasize / 16; + + fpst = get_fpstatus_ptr(); + + for (pass = 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 = tcg_temp_new_i32(); + TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + if (!is_q) { + /* non-quad vector op */ + clear_vec_high(s, rd); + } + +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11159,6 +11234,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Fri Oct 13 16:24:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115809 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp940487qgn; Fri, 13 Oct 2017 09:48:03 -0700 (PDT) X-Received: by 10.55.104.216 with SMTP id d207mr2859801qkc.142.1507913283432; Fri, 13 Oct 2017 09:48:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913283; cv=none; d=google.com; s=arc-20160816; b=loD49myh9H69oCq1Uqd7BJOwNji3oRo8zTO5MwRsYrm6OA843YYzn9ZgQFyV0D9hRL 7z9a7vOSvmkr9xD6bvRriCmInfd5SL+iZtV8ZQJYVScyah/NpOzTZ4XK0OunRrro9C8q 1w7JdCf4qGQWJOkkqgmLcEiNus/FPFwQujxwCr53rxlA5caOSh5QPCxLiV1t6m0xltMC wLEoSn8LwWN5O8gsUfQyh29SlJI619WdsFY2Awh904oU59XY28PFm3TUFRi+FFwIN3XQ jxjiBV3u4WrcxTgOWuuAvPF40EEE7yAwjkC7LuIPxo6zjYscU6nm84mOOKUJ9OBkm7Ah XMGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xs7O6Zy8N4Lzul7y2734QtKpGG+w/SMd3MT57cbaOYo=; b=y3g4XQtL0nbQ8KFfXSBZQ6KO5WtAyPgrkdabcMF43WyFi5ZK1Q6DONm4mkthzhAffr DFg7UCnCUCs6eRH9rvthXvUQ+t8J1zwLJAeiuprOme6EgH7GyaXkbu8A9D7qkTugDFR/ NeojrQD13bluevzyyo7Ty2t5zHKCEZmGt6ojMS1Bd7MSLTZf1AP+AzxIDpx6PdDi92Th LReNB1OwtHd4pif6tMtHO4rb4jh5kM7ORTZsgRN328Rni/5+EQHSFAJ95kpJk6JY0q1g A4B/nNzKHYA2wdQ85RZM84Fmcp4ink7/IXAeKMaW6+dT2B8RAi4/XuKtQDUR1maQfFpe n+ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eX28waQX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Half-precision helpers for float16 maths. I didn't bother hand-coding the count leading zeros as we could always fall-back to host-utils if we needed to. Signed-off-by: Alex Bennée --- fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 21 +++++++++++++++++++++ 2 files changed, 60 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h index 9cc6158cb4..73091a88a8 100644 --- a/fpu/softfloat-macros.h +++ b/fpu/softfloat-macros.h @@ -89,6 +89,31 @@ this code that are retained. # define SOFTFLOAT_GNUC_PREREQ(maj, min) 0 #endif +/*---------------------------------------------------------------------------- +| Shifts `a' right by the number of bits given in `count'. If any nonzero +| bits are shifted off, they are ``jammed'' into the least significant bit of +| the result by setting the least significant bit to 1. The value of `count' +| can be arbitrarily large; in particular, if `count' is greater than 16, the +| result will be either 0 or 1, depending on whether `a' is zero or nonzero. +| The result is stored in the location pointed to by `zPtr'. +*----------------------------------------------------------------------------*/ + +static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zPtr) +{ + uint16_t z; + + if ( count == 0 ) { + z = a; + } + else if ( count < 16 ) { + z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 ); + } + else { + z = ( a != 0 ); + } + *zPtr = z; + +} /*---------------------------------------------------------------------------- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -664,6 +689,20 @@ static uint32_t estimateSqrt32(int aExp, uint32_t a) } +/*---------------------------------------------------------------------------- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| `a'. If `a' is zero, 16 is returned. +*----------------------------------------------------------------------------*/ + +static int8_t countLeadingZeros16( uint16_t a ) +{ + if (a) { + return __builtin_clz(a); + } else { + return 16; + } +} + /*---------------------------------------------------------------------------- | Returns the number of leading 0 bits before the most-significant 1 bit of | `a'. If `a' is zero, 32 is returned. diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ab4b39c09..cf7bf6d4f4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,27 @@ static float16 roundAndPackFloat16(flag zSign, int zExp, return packFloat16(zSign, zExp, zSig >> 13); } +/*---------------------------------------------------------------------------- +| Takes an abstract floating-point value having sign `zSign', exponent `zExp', +| and significand `zSig', and returns the proper single-precision floating- +| point value corresponding to the abstract input. This routine is just like +| `roundAndPackFloat32' except that `zSig' does not have to be normalized. +| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' +| floating-point exponent. +*----------------------------------------------------------------------------*/ + +static float16 + normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig, + float_status *status) +{ + int8_t shiftCount; + + shiftCount = countLeadingZeros16( zSig ) - 1; + return roundAndPackFloat16(zSign, zExp - shiftCount, zSig< X-Patchwork-Id: 115796 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp927942qgn; Fri, 13 Oct 2017 09:35:31 -0700 (PDT) X-Received: by 10.55.41.139 with SMTP id p11mr2625059qkp.251.1507912531323; Fri, 13 Oct 2017 09:35:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912531; cv=none; d=google.com; s=arc-20160816; b=nSIVBBEs6t62aww4VVI1SQW1ag8oXLoERGMq5TxPuGFWEj1oitFdvsmi0pdZNDPIzi yTiZDFv98RKvNyncTIk19iUK5pv8DmIKWrwMIct0MRn+pJtsL9QrfL1SvF5b1nUDc6xr rM0M5855JiOIcBtSzMMQFJ6eSl9cYeGZwn4EaTDokxGKORuEUOxaKnluLb34FviJFvoi S5q8tqi1ECmvqXIF6Fv9iOrFFOCmb9nRwPyde0wb+DFk9mwmCbW5cecjZn/p5IkH3KHp sICBe4HWj7l/pSny5OjiHI+XNb79jUZ/DvfZb6YJftWnjUIimwLzvU9+GhA8QEwFt13U lw7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=fe3BMdKMEp8SD7k107xez1o/mOjZCJNEkZcsa6A7NcE=; b=1KoM/CUh4ZVtkfxPhfUe9A8N0N26FPU5JEucecVO58v6HDFYmcULtBT0Z5XGJZeQyV 8545Rclh0131jR4asMBCs3LWffdeYotpsmEJnQsjlbcXrvXz9FWQygoQkvZrWucFz8w3 ccWBfU8EW5ahslH5ubJe0TmX3phu1N6j/DYXI96rBOtV5YUMee3XGQt0ydhB5qc3luSh 51Ate6mc3lkom2GU4qPQi/Jy3F/RVjMDmBPjbJj5PPFiVOcXVNiF9lCs4MrbNX8CfIA0 UP8U8eX997id/DsC2aXWvfOCiA4nNjtH4t8fHT1y0vg5sn9cUaTOsaRqnpH6IBRKEK8f 1F2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UtUvA8aG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22b Subject: [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than following the SoftFloat3 implementation I've used the same basic template as the rest of our softfloat code. One minor difference is the 32bit intermediates end up with the binary point in the same place as the 32 bit version so the change isn't totally mechanical. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 352 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 6 + 2 files changed, 358 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cf7bf6d4f4..ff967f5525 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3532,6 +3532,358 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Returns the result of adding the absolute values of the half-precision +| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated +| before being returned. `zSign' is ignored if the result is a NaN. +| The addition is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +static float16 addFloat16Sigs(float16 a, float16 b, flag zSign, + float_status *status) +{ + int aExp, bExp, zExp; + uint16_t aSig, bSig, zSig; + int expDiff; + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + expDiff = aExp - bExp; + aSig <<= 3; + bSig <<= 3; + if ( 0 < expDiff ) { + if ( aExp == 0x1F ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + --expDiff; + } + else { + bSig |= 0x20000000; + } + shift16RightJamming( bSig, expDiff, &bSig ); + zExp = aExp; + } + else if ( expDiff < 0 ) { + if ( bExp == 0x1F ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( aExp == 0 ) { + ++expDiff; + } + else { + aSig |= 0x0400; + } + shift16RightJamming( aSig, - expDiff, &aSig ); + zExp = bExp; + } + else { + if ( aExp == 0x1F ) { + if (aSig | bSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( aExp == 0 ) { + if (status->flush_to_zero) { + if (aSig | bSig) { + float_raise(float_flag_output_denormal, status); + } + return packFloat16(zSign, 0, 0); + } + return packFloat16( zSign, 0, ( aSig + bSig )>>3 ); + } + zSig = 0x0400 + aSig + bSig; + zExp = aExp; + goto roundAndPack; + } + aSig |= 0x0400; + zSig = ( aSig + bSig )<<1; + --zExp; + if ( (int16_t) zSig < 0 ) { + zSig = aSig + bSig; + ++zExp; + } + roundAndPack: + return roundAndPackFloat16(zSign, zExp, zSig, true, status); + +} + +/*---------------------------------------------------------------------------- +| Returns the result of subtracting the absolute values of the half- +| precision floating-point values `a' and `b'. If `zSign' is 1, the +| difference is negated before being returned. `zSign' is ignored if the +| result is a NaN. The subtraction is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +static float16 subFloat16Sigs(float16 a, float16 b, flag zSign, + float_status *status) +{ + int aExp, bExp, zExp; + uint16_t aSig, bSig, zSig; + int expDiff; + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + expDiff = aExp - bExp; + aSig <<= 7; + bSig <<= 7; + if ( 0 < expDiff ) goto aExpBigger; + if ( expDiff < 0 ) goto bExpBigger; + if ( aExp == 0xFF ) { + if (aSig | bSig) { + return propagateFloat16NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + if ( aExp == 0 ) { + aExp = 1; + bExp = 1; + } + if ( bSig < aSig ) goto aBigger; + if ( aSig < bSig ) goto bBigger; + return packFloat16(status->float_rounding_mode == float_round_down, 0, 0); + bExpBigger: + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign ^ 1, 0xFF, 0 ); + } + if ( aExp == 0 ) { + ++expDiff; + } + else { + aSig |= 0x40000000; + } + shift16RightJamming( aSig, - expDiff, &aSig ); + bSig |= 0x40000000; + bBigger: + zSig = bSig - aSig; + zExp = bExp; + zSign ^= 1; + goto normalizeRoundAndPack; + aExpBigger: + if ( aExp == 0xFF ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + --expDiff; + } + else { + bSig |= 0x40000000; + } + shift16RightJamming( bSig, expDiff, &bSig ); + aSig |= 0x40000000; + aBigger: + zSig = aSig - bSig; + zExp = aExp; + normalizeRoundAndPack: + --zExp; + return normalizeRoundAndPackFloat16(zSign, zExp, zSig, status); + +} + +/*---------------------------------------------------------------------------- +| Returns the result of adding the half-precision floating-point values `a' +| and `b'. The operation is performed according to the IEC/IEEE Standard for +| Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_add(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + if ( aSign == bSign ) { + return addFloat16Sigs(a, b, aSign, status); + } + else { + return subFloat16Sigs(a, b, aSign, status); + } + +} + +/*---------------------------------------------------------------------------- +| Returns the result of subtracting the half-precision floating-point values +| `a' and `b'. The operation is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_sub(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + if ( aSign == bSign ) { + return subFloat16Sigs(a, b, aSign, status); + } + else { + return addFloat16Sigs(a, b, aSign, status); + } + +} + +/*---------------------------------------------------------------------------- +| Returns the result of multiplying the half-precision floating-point values +| `a' and `b'. The operation is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_mul(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign, zSign; + int aExp, bExp, zExp; + uint32_t aSig, bSig; + uint32_t zSig32; /* no zSig as zSig32 passed into rp&f */ + + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + bSign = extractFloat16Sign( b ); + zSign = aSign ^ bSign; + if ( aExp == 0x1F ) { + if ( aSig || ( ( bExp == 0x1F ) && bSig ) ) { + return propagateFloat16NaN(a, b, status); + } + if ( ( bExp | bSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( bExp == 0x1F ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + if ( ( aExp | aSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( aSig, &aExp, &aSig ); + } + if ( bExp == 0 ) { + if ( bSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( bSig, &bExp, &bSig ); + } + zExp = aExp + bExp - 0xF; + /* Add implicit bit */ + aSig = ( aSig | 0x0400 )<<4; + bSig = ( bSig | 0x0400 )<<5; + /* Max (format " => 0x%x" (* (lsh #x400 4) (lsh #x400 5))) => 0x20000000 + * So shift so binary point from 30/29 to 23/22 + */ + shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 ); + /* At this point the significand is at the same point as + * float32_mul, so we can do the same test */ + if ( 0 <= (int32_t) ( zSig32<<1 ) ) { + zSig32 <<= 1; + --zExp; + } + return roundAndPackFloat16(zSign, zExp, zSig32, true, status); +} + +/*---------------------------------------------------------------------------- +| Returns the result of dividing the half-precision floating-point value `a' +| by the corresponding value `b'. The operation is performed according to the +| IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_div(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign, zSign; + int aExp, bExp, zExp; + uint32_t aSig, bSig, zSig; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + bSign = extractFloat16Sign( b ); + zSign = aSign ^ bSign; + if ( aExp == 0xFF ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0xFF, 0 ); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign, 0, 0 ); + } + if ( bExp == 0 ) { + if ( bSig == 0 ) { + if ( ( aExp | aSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + float_raise(float_flag_divbyzero, status); + return packFloat16( zSign, 0xFF, 0 ); + } + normalizeFloat16Subnormal( bSig, &bExp, &bSig ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( aSig, &aExp, &aSig ); + } + zExp = aExp - bExp + 0x7D; + aSig = ( aSig | 0x00800000 )<<7; + bSig = ( bSig | 0x00800000 )<<8; + if ( bSig <= ( aSig + aSig ) ) { + aSig >>= 1; + ++zExp; + } + zSig = ( ( (uint64_t) aSig )<<16 ) / bSig; + if ( ( zSig & 0x3F ) == 0 ) { + zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 ); + } + return roundAndPackFloat16(zSign, zExp, zSig, true, status); + +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d89fdf7675..f1d79b6d03 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -345,6 +345,12 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status); /*---------------------------------------------------------------------------- | Software half-precision operations. *----------------------------------------------------------------------------*/ + +float16 float16_add(float16, float16, float_status *status); +float16 float16_sub(float16, float16, float_status *status); +float16 float16_mul(float16, float16, float_status *status); +float16 float16_div(float16, float16, float_status *status); + int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); From patchwork Fri Oct 13 16:24:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115811 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp943260qgn; Fri, 13 Oct 2017 09:51:15 -0700 (PDT) X-Received: by 10.55.162.73 with SMTP id l70mr2702631qke.29.1507913475784; Fri, 13 Oct 2017 09:51:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913475; cv=none; d=google.com; s=arc-20160816; b=LwZgtUyrrgaxBxlXiPR+uDqCVEQCpSMhpUZZBhlOz1/hfSlLtOAa+uDGVJVdY8yx6k JM5DcFQttAXqL9jPIrcB22es36qgF5QWZhHS9yJebUjmYaUS1AzxxcWqWeR/JLOExgiG fIOFWvr87VNF+crvKbVPePGU2rJpMqGeylJO258WhphX6E3BTN/gk7bGNWG9oCKAbPb2 HrmUTuKD+X2gYE3/S34HN7+e0jnusEgRC20OhZMc52Kf82YKP5leHcK3m47nkF1ac3zc sKOLeXvQuIBx5vgcvPyYHTHRjvwsjhuoF2MGJ4X9jjcOFZjxraCmJ/ClUxFTrguQsUGi 6kzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/h8XKayeoXJsQgrzKkClLe/QicmBHHpv4TzgELdjS3U=; b=klN/0ZL0XwnV6DxRmSCX+kCdt/eVbcE/rQ3EIueVy8/S1WNt7P9ky+LficD6JlFET1 PnS3KgYfECxmWvEiOIiDGj5yfmFzSJAbpElPojM3N6slna/YD5INq5aaeSaifaeeydcp Y0Q2RHl3DQE6glftjL1OEC3jP8TAQwd5QCZ1kfFyHQ1i1fwqoOuqRmayfZa9dkqCl0p5 J1snDOTEU/0PEpYj92+3r/mKWgtuyrc/eH2fVUeN/iCXOcGu80PswRrPWxftT1n+rm+l /uG3DCGr7HHaRqJ6ok80H9L3VkWtJsr/L8oPlBPxQOONa4qzBbg90zZ2iub27hwXm1/t LeYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W7JjesUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 4 ++++ target/arm/helper-a64.h | 4 ++++ target/arm/translate-a64.c | 12 +++++++++++- 3 files changed, 19 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index a0c20faabc..8ef15c4c45 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -551,6 +551,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ return float16_ ## name(a, b, fpst); \ } +ADVSIMD_HALFOP(add) +ADVSIMD_HALFOP(sub) +ADVSIMD_HALFOP(mul) +ADVSIMD_HALFOP(div) ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b774431f1f..a4ce87970e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,6 +44,10 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5e531b3ae4..f687bab214 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9806,8 +9806,18 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); switch (fpopcode) { + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x23: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x27: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: - fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode); + fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); g_assert_not_reached(); } From patchwork Fri Oct 13 16:24:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115793 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp925020qgn; Fri, 13 Oct 2017 09:32:37 -0700 (PDT) X-Received: by 10.200.36.50 with SMTP id c47mr2997415qtc.274.1507912357938; Fri, 13 Oct 2017 09:32:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912357; cv=none; d=google.com; s=arc-20160816; b=cOezX7j9sMS287h+8oduMeFJDjCJTyeaGpx+jhAYvKPM9B1BvJ/sVi/o3HlvepJanj /77tRQ0zN7TdSN/wquLQRUDjEG3Pr8XZxU7qEIvFbWa3vFnML7rudw2rjXhBOcjUUY1I rBf35+HU4j5I2Z53vyMJKY65NgLxNhK1+/SNDqW9OI2hjw0LPFpaaxV0tjIubJXDYfLm g3RNF2fo6PEflIQONRjZDRVIRCWTNy8wvRFSSlKcByfgfulNMGgz8IGvBTyhxHCpxa7g 6PEXe0d7IAvssPyoLw+nRK+rylFp6bRVbrNyARLhavP1kBYaoUATqa0/Ai2Z/9Wu1Kvt wrig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7hTdCXZLjy064puy8prIIR90bO7zbElDumYBjizMjRs=; b=T2D1asdbRCppLINUyLZbk7R1LhwsQ6lE8gkRrS+U1q93SLQAUsrG9hRe4or/1ICwab s0qkAUtH22lJoPCYIOW8W8AybWj8MCbsbhfyyASZRIO9zXE3NMienLF52Z/8593oKxVR vS01P+pW0P0tYr1h3i+hfm8lG4F6sV4KKVfKiCMAALoGjRUCnhN/YJSwzSzptyrcY1xq Rwudi61ZwZ9wq9CD9OU7G+83KQAyATCq07G5CFHof8QYc8RT4y9ltJcjfPF2Z1hKVh2l LOY1rwQvUBx1jeLndzbWcFSKzpAAu4muVHIFIf6wqSkkv5TKdWTK8RqSD/HKuClVVMgJ EpaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XxDT+8VX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 18 ++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 45 +++++++++++++++++++++++++++++++++++---------- 3 files changed, 54 insertions(+), 10 deletions(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 8ef15c4c45..dd26675d5c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -559,3 +559,21 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* Data processing - scalar floating-point and advanced SIMD */ + +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + if ((float16_is_zero(a) && float16_is_infinity(b)) || + (float16_is_infinity(a) && float16_is_zero(b))) { + /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ + return make_float16((1U << 14) | + ((float16_val(a) ^ float16_val(b)) & (1U << 15))); + } + return float16_mul(a, b, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a4ce87970e..0f97eb607f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -52,3 +52,4 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f687bab214..d12106695f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } /* fall through */ case 0x9: /* FMUL, FMULX */ - if (!extract32(size, 1, 1)) { + if (!extract32(size, 1, 1) && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } @@ -10660,18 +10660,30 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - /* low bit of size indicates single/double */ - size = extract32(size, 0, 1) ? 3 : 2; - if (size == 2) { + /* convert insn encoded size to TCGMemOp size */ + switch (size) { + case 0: /* half-precision */ + size = MO_16; + index = h << 2 | l << 1 | m; + break; + case 2: /* single precision */ + size = MO_32; index = h << 1 | l; - } else { + rm |= (m << 4); + break; + case 3: /* double precision */ + size = MO_64; if (l || !is_q) { unallocated_encoding(s); return; } index = h; + rm |= (m << 4); + break; + default: + g_assert_not_reached(); + break; } - rm |= (m << 4); } else { switch (size) { case 1: @@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); break; case 0x9: /* FMUL, FMULX */ - if (u) { - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + switch (size) { + case 1: + if (u) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst); + } else { + g_assert_not_reached(); + } + break; + case 2: + if (u) { + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); + } else { + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + } + break; + default: + g_assert_not_reached(); } break; case 0xc: /* SQDMULH */ From patchwork Fri Oct 13 16:24:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115804 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp937041qgn; Fri, 13 Oct 2017 09:44:14 -0700 (PDT) X-Received: by 10.200.36.24 with SMTP id c24mr3040864qtc.202.1507913054744; Fri, 13 Oct 2017 09:44:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913054; cv=none; d=google.com; s=arc-20160816; b=loc6XI3V5Qf8ZHCk0hx9rQ7WiZhfSEuehmev6YBUxfmJNaoo6+1CHk1LhMw+lH8IKU syToiKAPa4wYLXnTlLQY+WMasLHVYF24+a81b/dj/ZlnjnP8S6y17zbV5EPBNjxVqhk1 zE9BCUJuezjuQWXKqO+fk189gchxFt3iSxplvolEls0tRI0+YW4ohyf3n08o6GmaOUXo hLdWddGrp7KqsWbDNf22jeN55DO/2QD4coHxi5/i8NPhpYWf5OLfKao76BQsjhZFKYN6 pRwXTumDRUYvPrbVspOJilAfbCACREpIYH0UB+8qnE+mEhM5ES2F7RAQsfXh5Uruut6H nnHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=5d2wjGmQNminesQ3Qx8EtmxG4KhTgZyRAncKoxWcWxc=; b=T627+ZguBWP7viBE0e0lAJrSaQcRNflJzy5tK5Zhix6unapgLY1FomVNLpR48LqBiw NnGnyEwDHvjl/ifPPu2dXkalkaEp99kKfe/ggjaDsFzW+V7PRckg191k57wf7VArjfjI aDnY80yxli8Bco1q4oOZAmT5GbMNPq61h3tEMsme+FmGUKfOURd9nnynJujqK8+XmYeF JUfvMOF59akv3RtE2+ZJ16bCXjWBa2dpDcwUK/HU50VD2IfM+GdRGvgaBES3rtDbDYSY x+gdx83gw3lFyTylDr8ZlMvRQHPUFj2GZKB2n6/eCPCmBU+s5fs2hJa6RJxbyl/B4/Jg lf7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IEZgjabH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.14.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d12106695f..11990daff4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10568,6 +10568,40 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } +/* AdvSIMD two reg misc FP16 + * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 + * +---+---+---+-----------+---+-------------+--------+-----+------+------+ + * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * +---+---+---+-----------+---+-------------+--------+-----+------+------+ + * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00 + * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800 + * Half-precision variants of two-reg misc. + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode = extract32(insn, 12, 4); + a = extract32(insn, 23, 1); + fpop = deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ @@ -11270,6 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Fri Oct 13 16:24:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115813 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp944852qgn; Fri, 13 Oct 2017 09:53:14 -0700 (PDT) X-Received: by 10.233.239.140 with SMTP id d134mr2949427qkg.308.1507913594927; Fri, 13 Oct 2017 09:53:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913594; cv=none; d=google.com; s=arc-20160816; b=0Ydh5QTqKnq+V32lmJqjeufPPNYiMwvf39utnQtsJ7xkoZO2DQBQNR4NQQ/G9JGQoy bfgCPgFZ/2uht4zDVvyNHbthA+IGgFphJ509BND9qU3AqAnXJM1Q2x3oP95uyMcNJQ6p 5u912mS9zSdNr86hOamppM11pBiZxQrHtL754nwhQ97g0qRVn+BaH8t9oNz6gEA7yHfa yxbNxIfPXJbdThsqEmGd8cfW5YhaZwW0wfNoHx00iMFUmgGpVlo9fyHtop+ASKBorCos F8TK8B5bPXO4inGATL8TF5wxFMeHk2MH8NTGJWXyIqWgOjT/9rkggHIwhUGGkImecD+1 HtCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0pF7DYMlN5Y+H34UPoxCs3esXfc4X++Fqy9m50EgBrY=; b=tHbtNbBTtXWKkGcAavRlSt8nKn/BKpR0+A82CxfZ2rlebPkJAWCUCjt/AK+T+IUeNP MJBbz8FjYEPhM6LzxSUzYCaos27JIPG5sRifUQyecaSEo54jQq/wEIGE6FyqMjvdApZc CK2xyT97vLaRTFULRY4PdD5i/jINVWItgQp8EIs8cNRkLVJtAqopwk2V9/uS5Ly256sy 2kwON2jLIpiiefM48gpM8ud/CkOFVkogwczZ4PdDn85N09TzYnIE4KT6mSwsSvILvNPS yJo3MbMrRPDZuLW8mB1OrPf4+RLx4sP9akPVdM7BxLGeRVZVjAnX7wdIVx+57/GSVL7P xo8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fQeiw62p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While the group encoding declares bit 28 a zero it is set for FCMGT (zero) Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.14.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11990daff4..7792cea9f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10571,10 +10571,10 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* AdvSIMD two reg misc FP16 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * | 0 | Q | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00 - * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800 + * mask: 1001 1111 0111 1110 0000 1100 0000 0000 0x9f7e 0c00 + * val: 0001 1110 0111 1000 0000 1000 0000 0000 0x1e78 0800 * Half-precision variants of two-reg misc. */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) @@ -11304,7 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, - { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; @@ -11318,6 +11318,8 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn) if (fn) { fn(s, insn); } else { + fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", + __func__, insn, s->pc); unallocated_encoding(s); } } From patchwork Fri Oct 13 16:24:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115802 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp935080qgn; Fri, 13 Oct 2017 09:42:20 -0700 (PDT) X-Received: by 10.237.56.102 with SMTP id j93mr2868176qte.57.1507912940907; Fri, 13 Oct 2017 09:42:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912940; cv=none; d=google.com; s=arc-20160816; b=jM6OTe701pVwWx2IKH/ycB0h7gWxsuOahBNpZwg1Bohn6zG6hr0AdiLImUBrTKx4MG B/sPqJFDAaObkG9D9JEyyz43xA7Z0/lKxbNEWUYvsL2HVjvhWu/uSmLpwNTp8N+ghhbn w5/jl6/uzbJQtjpjQ/ZvCqmHQuGrK3vWWOaxXcAZstEGQ017Xa0E2iDqMc/Y7cw26q3Y pgKIRu+6Khem8GckstOKb0pVz9XI+gwLCk1osgwBlapoLdBU5IB28hseTP29GcNU1XGr ZQnwqzAl3pB0ZfzQzbUwGiuB5/ftwjvLvz5V/yZWzPNvnxBCHKLp7UPUNt8ugNU+cR4g DAkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+X5KKz60dQZzeRgkkxwZp9Au+zKYzQ0aoOzQpbeucaE=; b=MMkGcXS6wjX7cxm9fe8T6Y/7kyYoN0d65A9HvSX2HTKEkOYEkGV/IUQWOzMCFZ40oO qgPxDwNoyi3zcsxvJoAhrqel/wq1HehhtiTwLVUU94iVUQFg2W3aG7PfilADgW8V28dh xzE/nTucNk6Kh28Aimdf1PNoZqBG74l4XkOfDrUnJLA5i7bMi4M62K/+FmzEIuUUO83+ jwkKyUUK3THbKn830X58eF5lgWreqC3dZaUuMMbzqTfDMT8oi9Ap45dLjUEcjoSBVejN vWX74+rW/YO8LOqK5nO2MZI9XzFB0vH1hMSuDvyEzUTgRPcnXC/syHBkBZEVNA6YtM0Y lEeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dBGKdtCu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is mostly a mechanical conversion of the float32 variants of the same name with some judicious search/replace and some constants changed. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 216 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 ++ 2 files changed, 224 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ff967f5525..fdb2999c41 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3884,6 +3884,222 @@ float16 float16_div(float16 a, float16 b, float_status *status) } +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. Otherwise, the comparison is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_eq(float16 a, float16 b, float_status *status) +{ + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + av = float16_val(a); + bv = float16_val(b); + return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| or equal to the corresponding value `b', and 0 otherwise. The invalid +| exception is raised if either operand is a NaN. The comparison is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_le(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); + return ( av == bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. The comparison is performed according +| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_lt(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 ); + return ( av != bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. The invalid exception is raised if either +| operand is a NaN. The comparison is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_unordered(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 1; + } + return 0; +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. The comparison is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_eq_quiet(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + return ( float16_val(a) == float16_val(b) ) || + ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 ); +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than or +| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not +| cause an exception. Otherwise, the comparison is performed according to the +| IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_le_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); + return ( av == bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. Otherwise, the comparison is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_lt_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 ); + return ( av != bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The +| comparison is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_unordered_quiet(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 1; + } + return 0; +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f1d79b6d03..76a8310780 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -350,6 +350,14 @@ float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); float16 float16_div(float16, float16, float_status *status); +int float16_eq(float16, float16, float_status *status); +int float16_le(float16, float16, float_status *status); +int float16_lt(float16, float16, float_status *status); +int float16_unordered(float16, float16, float_status *status); +int float16_eq_quiet(float16, float16, float_status *status); +int float16_le_quiet(float16, float16, float_status *status); +int float16_lt_quiet(float16, float16, float_status *status); +int float16_unordered_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); From patchwork Fri Oct 13 16:24:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115800 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp932934qgn; Fri, 13 Oct 2017 09:40:15 -0700 (PDT) X-Received: by 10.55.15.42 with SMTP id z42mr2791440qkg.181.1507912815424; Fri, 13 Oct 2017 09:40:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912815; cv=none; d=google.com; s=arc-20160816; b=ouvXObL5QESYkaUZvzuSsAY7WVtfLdncwFBdHBc4kx9BS3vpbSp0xolhSUXzTMf7nh azuCHVQD+GkU/u+DFvOOujKpWhMd8Xwm0/nTp/y5unzo4qqFvOquPPiULKZjiVxB6azP DEWf78ShIfhdcByEJdfCsjQv+AEz6jmIIo4acS06lScvVs8wL5s3zK6y2AKBw2lJb4dY n6SwFn4seWGVsVz+GoE3McUOMaWFdtn9Y5cLv6YWSX81ahcf17c6uEp3YqGrxqi3kE1R HSse/UNf76g8AF3HCeIxh4R+oOHPwceA1E/AIyBmreSXxjNKEXHqEbQbX2m6o3MwOhbE 74YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=WgjrWBed7KjNuOQTB73y78RIIJBwnNFIlmGKPi/MoyY=; b=ZWK1mIdPz3dv2jdIiz41C6xd4nqtX06HZ18qZ9sFcfs9Ry4sLaXXVI42+eyKV+/VF2 uf14j5YTBLMe+p4zWvjkvtGc3LCwCTzLX2ODwxy2UjhwJ1Va7yUtvg1VuuyRbwHugnYy MpMJhuyzwCxfmvDDf6RJJEPSBRWOjIZ4/6LPLnlmAUJ3r4Ut1VfwgFyoU07RIzNi9SXf ryMIW9cNvK9oHUadafIdpQ81cBThXRV6KUJQ4qZZ69xz0slECvHoBF8Z4J0/VhaCffJy ONHMbhALgVdnvLhN7o7WihnN1IABxsSbogZTNLcRb+chdeMySJQ6BqsJDxwN+6zqeF4z yj6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SLf2DR4g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 39 +++++++++++++++++++++++++++++++++++++++ target/arm/helper-a64.h | 6 ++++++ target/arm/translate-a64.c | 25 ++++++++++++++++++------- 3 files changed, 63 insertions(+), 7 deletions(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index dd26675d5c..b62d77aec4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -577,3 +577,42 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) } return float16_mul(a, b, fpst); } + + +/* + * Floating point comparisons produce an integer result. + * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. + */ +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_eq_quiet(a, b, fpst); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_le(b, a, fpst); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_lt(b, a, fpst); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + return -float16_le(f1, f0, fpst); +} + +/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */ +/* { */ +/* float_status *fpst = fpstp; */ +/* float16 f0 = float16_abs(a); */ +/* float16 f1 = float16_abs(b); */ +/* return -float16_lt(f1, f0, fpst); */ +/* } */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 0f97eb607f..952869f43e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,3 +53,9 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) + +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7792cea9f5..623b0b3fab 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7785,6 +7785,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, TCGv_i32 tcg_res = tcg_temp_new_i32(); NeonGenTwoSingleOPFn *genfn; bool swap = false; + bool hp = (size == 1 ? true : false); int pass, maxpasses; switch (opcode) { @@ -7792,7 +7793,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, swap = true; /* fall through */ case 0x2c: /* FCMGT (zero) */ - genfn = gen_helper_neon_cgt_f32; + genfn = hp ? gen_helper_advsimd_cgt_f16 : gen_helper_neon_cgt_f32; break; case 0x2d: /* FCMEQ (zero) */ genfn = gen_helper_neon_ceq_f32; @@ -7814,7 +7815,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, } for (pass = 0; pass < maxpasses; pass++) { - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32); if (swap) { genfn(tcg_res, tcg_zero, tcg_op, fpst); } else { @@ -7823,7 +7824,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, hp ? MO_16 : MO_32); } } tcg_temp_free_i32(tcg_res); @@ -9809,6 +9810,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x23: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10580,21 +10584,28 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { int fpop, opcode, a; + int rn, rd; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } - if (!fp_access_check(s)) { - return; - } - opcode = extract32(insn, 12, 4); a = extract32(insn, 23, 1); fpop = deposit32(opcode, 5, 1, a); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + switch (fpop) { + case 0x2c: /* FCMGT (zero) */ + case 0x2d: /* FCMEQ (zero) */ + case 0x2e: /* FCMLT (zero) */ + case 0x6c: /* FCMGE (zero) */ + case 0x6d: /* FCMLE (zero) */ + handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd); + break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); From patchwork Fri Oct 13 16:24:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115797 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp928016qgn; Fri, 13 Oct 2017 09:35:36 -0700 (PDT) X-Received: by 10.55.217.203 with SMTP id q72mr2967135qkl.245.1507912536754; Fri, 13 Oct 2017 09:35:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912536; cv=none; d=google.com; s=arc-20160816; b=0UFRH44hw7qm+JbM2f9MvDO4F6w3aGdiGfrhPekPL0WoXi90UMp5OeMky7/dwiX/y1 XeLlMgbjmJ7FBDAzfL0dUrEyahI0TuMAEPkJfH9f4sIKGWsEWZKJ3Jkj9jOvlR1CjBzb ayr/gs20GZurHUFrxpvPSaZdNEuEOENdUUhzmfgQYQv1zxtOJz5mTYPLuI0hoTuzQFop 7qW9BfCxtjdGwZXvSwfnm+I8jnJfQIpLr8dnpgCXHH8GaIjVfbCJxpaLJcpMveFE/Thx MPze+prBmdb+a7NXKq3/HeoWuFm3w0VV1vwbyDiF8dRwj0BUcKuC7Q48OLKZdhRR5ZG+ u5cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qWTVUeorlcjJ1j/bX+0cRFs7MwNBmLiUOPv0JWsOg/o=; b=RfsTvJChFKnkUGPbL0+Xz5j7MM454BGF6iy52Z5goeokTwKuL3JrBr3kCmyzSnVVs0 TBc/3FzmGTYuHwRIGC6B+aT47MnoOTShsf4f9ObNgOG8sIHCKTQhQyRlexJkxOEbiMgf ST8KVWBTY2VdGVcd1fKO9DBCOXELRonKmsleB2jO0AT5tvT/EBVC2h1BkG1fJT5aptv/ lGXEikGlb+QmD8abgt5FSwkYVBKg4h5EiP2JBq0b/1OsBEWYQe8N5S0VmnlmnQLBu4Ym NBPCELd5PmNdfaA6rSB47VQNU3giZSvLw1A2iF3VN7lju/bMaGyYTtmBf6n6NW6jbFZi eh9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YzvH0shK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 14 +++++++------- target/arm/helper-a64.h | 1 - target/arm/translate-a64.c | 3 +++ 3 files changed, 10 insertions(+), 8 deletions(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b62d77aec4..137866732d 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -609,10 +609,10 @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) return -float16_le(f1, f0, fpst); } -/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */ -/* { */ -/* float_status *fpst = fpstp; */ -/* float16 f0 = float16_abs(a); */ -/* float16 f1 = float16_abs(b); */ -/* return -float16_lt(f1, f0, fpst); */ -/* } */ +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + return -float16_lt(f1, f0, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 952869f43e..66c4062ea5 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,7 +53,6 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) - DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 623b0b3fab..4ad470d9e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9819,6 +9819,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x27: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x35: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); From patchwork Fri Oct 13 16:24:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115801 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp934920qgn; Fri, 13 Oct 2017 09:42:11 -0700 (PDT) X-Received: by 10.200.52.235 with SMTP id x40mr2850887qtb.135.1507912931447; Fri, 13 Oct 2017 09:42:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912931; cv=none; d=google.com; s=arc-20160816; b=gTUhJgEccXYIt5gSQFAWffwKpgsTBIuUtBikzqLyc8mPUh7he+3UHeFvK2TGmtMuWh kwfST4ODtdM3Ly2ngvM5XtAnaiWmsZU8cQ3aHExbLyklycmxnSE56Fp34HReGL2WeVQ/ LWzq75MFUahi1c/c5oh6n1PNmMTqogtqjJ3+pPR2DtqHNdEIFG+MbqHzZiSXftKKvpXD Kjz8H90laGBmfbws2fuwQtGt4f5Ez7nRmgdPeCad+mEvdFd260s79GQQlIjxBgnAbLF4 I4af7A0pUADCfGfoDY1mw4Nju4PlZqZWtiGpTGgs7g9VcBrjSz11oVG85Ik5FbJh3n2Q tSuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=UO8/dqxLs3JexzFu1Zz6rU4lpXIYQJK7hAlRHClqK6U=; b=lvYKPfhSzbr7e/nZlcxUFSbqLT65FDjCZ1G+6xz0rGMMuwuTCS/d48715Uwv8v1vSF vH9SKOpgC3tebIwrZjZvm3acYae4xoMrmjGxN13X1QooeEi5eHR3sLPJui6yMH6LGaa+ RwxV3tx2sMyY2i6GMfhrdJ0FPN6l25lUd5TDCHNE34KroIM+phXQvGucXYKpiu+HBRK4 44AUxmeGlupwwkujTj2uxo8nXeJb9JHSbgFeDcOqUUoTxAOaLs+A3RxoEA8XA/6vGMCo QB2hwN5Cfu187tcZ6YdfTxADmOAmWjWKWugbpUG0Da7mtPWF4ogqjHkMLnVYYs9K+2OE JAeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OuxIJYlI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- fpu/softfloat-specialize.h | 52 +++++++ fpu/softfloat.c | 327 +++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 2 + 3 files changed, 381 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2ccd4abe11..33c4be1757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -728,6 +728,58 @@ static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status) } } +/*---------------------------------------------------------------------------- +| Takes three half-precision floating-point values `a', `b' and `c', one of +| which is a NaN, and returns the appropriate NaN result. If any of `a', +| `b' or `c' is a signaling NaN, the invalid exception is raised. +| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case +| obviously c is a NaN, and whether to propagate c or some other NaN is +| implementation defined). +*----------------------------------------------------------------------------*/ + +static float16 propagateFloat16MulAddNaN(float16 a, float16 b, + float16 c, flag infzero, + float_status *status) +{ + flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, + cIsQuietNaN, cIsSignalingNaN; + int which; + + aIsQuietNaN = float16_is_quiet_nan(a, status); + aIsSignalingNaN = float16_is_signaling_nan(a, status); + bIsQuietNaN = float16_is_quiet_nan(b, status); + bIsSignalingNaN = float16_is_signaling_nan(b, status); + cIsQuietNaN = float16_is_quiet_nan(c, status); + cIsSignalingNaN = float16_is_signaling_nan(c, status); + + if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) { + float_raise(float_flag_invalid, status); + } + + which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN, + bIsQuietNaN, bIsSignalingNaN, + cIsQuietNaN, cIsSignalingNaN, infzero, status); + + if (status->default_nan_mode) { + /* Note that this check is after pickNaNMulAdd so that function + * has an opportunity to set the Invalid flag. + */ + return float16_default_nan(status); + } + + switch (which) { + case 0: + return float16_maybe_silence_nan(a, status); + case 1: + return float16_maybe_silence_nan(b, status); + case 2: + return float16_maybe_silence_nan(c, status); + case 3: + default: + return float16_default_nan(status); + } +} + /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a diff --git a/fpu/softfloat.c b/fpu/softfloat.c index fdb2999c41..f7473f97e3 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3884,6 +3884,333 @@ float16 float16_div(float16 a, float16 b, float_status *status) } +/*---------------------------------------------------------------------------- +| Returns the remainder of the half-precision floating-point value `a' +| with respect to the corresponding value `b'. The operation is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_rem(float16 a, float16 b, float_status *status) +{ + flag aSign, zSign; + int aExp, bExp, expDiff; + uint32_t aSig, bSig; + uint32_t q; + uint64_t aSig64, bSig64, q64; + uint32_t alternateASig; + int32_t sigMean; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat32Frac( a ); + aExp = extractFloat32Exp( a ); + aSign = extractFloat32Sign( a ); + bSig = extractFloat32Frac( b ); + bExp = extractFloat32Exp( b ); + if ( aExp == 0xFF ) { + if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) { + return propagateFloat32NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat32NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + if ( bSig == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + normalizeFloat32Subnormal( bSig, &bExp, &bSig ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return a; + normalizeFloat32Subnormal( aSig, &aExp, &aSig ); + } + expDiff = aExp - bExp; + aSig |= 0x00800000; + bSig |= 0x00800000; + if ( expDiff < 32 ) { + aSig <<= 8; + bSig <<= 8; + if ( expDiff < 0 ) { + if ( expDiff < -1 ) return a; + aSig >>= 1; + } + q = ( bSig <= aSig ); + if ( q ) aSig -= bSig; + if ( 0 < expDiff ) { + q = ( ( (uint64_t) aSig )<<32 ) / bSig; + q >>= 32 - expDiff; + bSig >>= 2; + aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; + } + else { + aSig >>= 2; + bSig >>= 2; + } + } + else { + if ( bSig <= aSig ) aSig -= bSig; + aSig64 = ( (uint64_t) aSig )<<40; + bSig64 = ( (uint64_t) bSig )<<40; + expDiff -= 64; + while ( 0 < expDiff ) { + q64 = estimateDiv128To64( aSig64, 0, bSig64 ); + q64 = ( 2 < q64 ) ? q64 - 2 : 0; + aSig64 = - ( ( bSig * q64 )<<38 ); + expDiff -= 62; + } + expDiff += 64; + q64 = estimateDiv128To64( aSig64, 0, bSig64 ); + q64 = ( 2 < q64 ) ? q64 - 2 : 0; + q = q64>>( 64 - expDiff ); + bSig <<= 6; + aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; + } + do { + alternateASig = aSig; + ++q; + aSig -= bSig; + } while ( 0 <= (int32_t) aSig ); + sigMean = aSig + alternateASig; + if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { + aSig = alternateASig; + } + zSign = ( (int32_t) aSig < 0 ); + if ( zSign ) aSig = - aSig; + return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status); +} + +/*---------------------------------------------------------------------------- +| Returns the result of multiplying the half-precision floating-point values +| `a' and `b' then adding 'c', with no intermediate rounding step after the +| multiplication. The operation is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic 754-2008. +| The flags argument allows the caller to select negation of the +| addend, the intermediate product, or the final result. (The difference +| between this and having the caller do a separate negation is that negating +| externally will flip the sign bit on NaNs.) +*----------------------------------------------------------------------------*/ + +float16 float16_muladd(float16 a, float16 b, float16 c, int flags, + float_status *status) +{ + flag aSign, bSign, cSign, zSign; + int aExp, bExp, cExp, pExp, zExp, expDiff; + uint32_t aSig, bSig, cSig; + flag pInf, pZero, pSign; + uint64_t pSig64, cSig64, zSig64; + uint32_t pSig; + int shiftcount; + flag signflip, infzero; + + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + c = float16_squash_input_denormal(c, status); + aSig = extractFloat16Frac(a); + aExp = extractFloat16Exp(a); + aSign = extractFloat16Sign(a); + bSig = extractFloat16Frac(b); + bExp = extractFloat16Exp(b); + bSign = extractFloat16Sign(b); + cSig = extractFloat16Frac(c); + cExp = extractFloat16Exp(c); + cSign = extractFloat16Sign(c); + + infzero = ((aExp == 0 && aSig == 0 && bExp == 0x1f && bSig == 0) || + (aExp == 0x1f && aSig == 0 && bExp == 0 && bSig == 0)); + + /* It is implementation-defined whether the cases of (0,inf,qnan) + * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN + * they return if they do), so we have to hand this information + * off to the target-specific pick-a-NaN routine. + */ + if (((aExp == 0xff) && aSig) || + ((bExp == 0xff) && bSig) || + ((cExp == 0xff) && cSig)) { + return propagateFloat16MulAddNaN(a, b, c, infzero, status); + } + + if (infzero) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + + if (flags & float_muladd_negate_c) { + cSign ^= 1; + } + + signflip = (flags & float_muladd_negate_result) ? 1 : 0; + + /* Work out the sign and type of the product */ + pSign = aSign ^ bSign; + if (flags & float_muladd_negate_product) { + pSign ^= 1; + } + pInf = (aExp == 0xff) || (bExp == 0xff); + pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0); + + if (cExp == 0xff) { + if (pInf && (pSign ^ cSign)) { + /* addition of opposite-signed infinities => InvalidOperation */ + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + /* Otherwise generate an infinity of the same sign */ + return packFloat16(cSign ^ signflip, 0xff, 0); + } + + if (pInf) { + return packFloat16(pSign ^ signflip, 0xff, 0); + } + + if (pZero) { + if (cExp == 0) { + if (cSig == 0) { + /* Adding two exact zeroes */ + if (pSign == cSign) { + zSign = pSign; + } else if (status->float_rounding_mode == float_round_down) { + zSign = 1; + } else { + zSign = 0; + } + return packFloat16(zSign ^ signflip, 0, 0); + } + /* Exact zero plus a denorm */ + if (status->flush_to_zero) { + float_raise(float_flag_output_denormal, status); + return packFloat16(cSign ^ signflip, 0, 0); + } + } + /* Zero plus something non-zero : just return the something */ + if (flags & float_muladd_halve_result) { + if (cExp == 0) { + normalizeFloat16Subnormal(cSig, &cExp, &cSig); + } + /* Subtract one to halve, and one again because roundAndPackFloat16 + * wants one less than the true exponent. + */ + cExp -= 2; + cSig = (cSig | 0x00800000) << 7; + return roundAndPackFloat16(cSign ^ signflip, cExp, cSig, true, status); + } + return packFloat16(cSign ^ signflip, cExp, cSig); + } + + if (aExp == 0) { + normalizeFloat16Subnormal(aSig, &aExp, &aSig); + } + if (bExp == 0) { + normalizeFloat16Subnormal(bSig, &bExp, &bSig); + } + + /* Calculate the actual result a * b + c */ + + /* Multiply first; this is easy. */ + /* NB: we subtract 0x7e where float16_mul() subtracts 0x7f + * because we want the true exponent, not the "one-less-than" + * flavour that roundAndPackFloat16() takes. + */ + pExp = aExp + bExp - 0x7e; + aSig = (aSig | 0x00800000) << 7; + bSig = (bSig | 0x00800000) << 8; + pSig64 = (uint64_t)aSig * bSig; + if ((int64_t)(pSig64 << 1) >= 0) { + pSig64 <<= 1; + pExp--; + } + + zSign = pSign ^ signflip; + + /* Now pSig64 is the significand of the multiply, with the explicit bit in + * position 62. + */ + if (cExp == 0) { + if (!cSig) { + /* Throw out the special case of c being an exact zero now */ + shift64RightJamming(pSig64, 32, &pSig64); + pSig = pSig64; + if (flags & float_muladd_halve_result) { + pExp--; + } + return roundAndPackFloat16(zSign, pExp - 1, + pSig, true, status); + } + normalizeFloat16Subnormal(cSig, &cExp, &cSig); + } + + cSig64 = (uint64_t)cSig << (62 - 23); + cSig64 |= LIT64(0x4000000000000000); + expDiff = pExp - cExp; + + if (pSign == cSign) { + /* Addition */ + if (expDiff > 0) { + /* scale c to match p */ + shift64RightJamming(cSig64, expDiff, &cSig64); + zExp = pExp; + } else if (expDiff < 0) { + /* scale p to match c */ + shift64RightJamming(pSig64, -expDiff, &pSig64); + zExp = cExp; + } else { + /* no scaling needed */ + zExp = cExp; + } + /* Add significands and make sure explicit bit ends up in posn 62 */ + zSig64 = pSig64 + cSig64; + if ((int64_t)zSig64 < 0) { + shift64RightJamming(zSig64, 1, &zSig64); + } else { + zExp--; + } + } else { + /* Subtraction */ + if (expDiff > 0) { + shift64RightJamming(cSig64, expDiff, &cSig64); + zSig64 = pSig64 - cSig64; + zExp = pExp; + } else if (expDiff < 0) { + shift64RightJamming(pSig64, -expDiff, &pSig64); + zSig64 = cSig64 - pSig64; + zExp = cExp; + zSign ^= 1; + } else { + zExp = pExp; + if (cSig64 < pSig64) { + zSig64 = pSig64 - cSig64; + } else if (pSig64 < cSig64) { + zSig64 = cSig64 - pSig64; + zSign ^= 1; + } else { + /* Exact zero */ + zSign = signflip; + if (status->float_rounding_mode == float_round_down) { + zSign ^= 1; + } + return packFloat16(zSign, 0, 0); + } + } + --zExp; + /* Normalize to put the explicit bit back into bit 62. */ + shiftcount = countLeadingZeros64(zSig64) - 1; + zSig64 <<= shiftcount; + zExp -= shiftcount; + } + if (flags & float_muladd_halve_result) { + zExp--; + } + + shift64RightJamming(zSig64, 32, &zSig64); + return roundAndPackFloat16(zSign, zExp, zSig64, true, status); +} + /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is equal to | the corresponding value `b', and 0 otherwise. The invalid exception is diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 76a8310780..a7435e2a5b 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -350,6 +350,8 @@ float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); float16 float16_div(float16, float16, float_status *status); +float16 float16_rem(float16, float16, float_status *status); +float16 float16_muladd(float16, float16, float16, int, float_status *status); int float16_eq(float16, float16, float_status *status); int float16_le(float16, float16, float_status *status); int float16_lt(float16, float16, float_status *status); From patchwork Fri Oct 13 16:24:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115807 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp939165qgn; Fri, 13 Oct 2017 09:46:29 -0700 (PDT) X-Received: by 10.55.156.141 with SMTP id f135mr2893034qke.309.1507913189495; Fri, 13 Oct 2017 09:46:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913189; cv=none; d=google.com; s=arc-20160816; b=uqQTfjv9fCcLwbe7KE2xeDrxHVBFmv5ON5oNI6Pll+6UQSFer34eYXwb4klsX+VwzC XoAhSptXY3ceb/pMrQwTacJHoCzGCXt1RqtIVbHFCUcU/nyBzBW9qaL64QZZInQklDt+ O0HwWId+w+kl0thYd95AV4CRMdc+GrslQ3P0ns5JtSEJvwVRopEnz8htIMYQeQF6XPdn p3SxasEtdYQfVQYP2BqxwLbWc1WkyMVliXoDi6a03HfjaN4XJWD7jPT8vDwNiW8PiiYV OC6sG8tZZnJa15Ae3Shi34jHcTluCMv56dOGqryl+F6uXGuk742rLl3FNCEM5cEUKYIC kssw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eDKJf8QoZFlvtHit/EDPGrTfxs9RO/NiARjDvgLSZdE=; b=eDKamj2AcDw9jDarnLLcZ0MW1LftRvwIoiQxAyRU4PI6FTZBbL/nV1ZbUQK5Tq56um Tjd/Fx0oZXYKC3EH1U3uLxxjMkB1EyTWp3GgZg+NWKt+gngtdPJZlRGXoklaqbo423oA dQ+y2dXcm6vtPP+8Bd7PYRohCiM0pa6VacnHlzhIgt9+y0LOFCgVDbYVIKHAJLffc9n0 pEBosnseqkoqMjHbrukxJY7iOGCxSHjFMDtd2xCEQRu0J49KN4X+PoTyfH+8NzreQLSw 7mkSGaiaKHypNsjwNpHPwzevLB0KmQUGGT/O+45iHIZKn/DlkahHNIlgG3OzJiERy8lw /Wjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EemdC4eI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A mild re-factoring of the !is_double leg to gracefully handle both single and half-precision operations. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 6 ++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 19 +++++++++++++------ 3 files changed, 20 insertions(+), 6 deletions(-) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 137866732d..241fee9d93 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -578,6 +578,12 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) return float16_mul(a, b, fpst); } +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) +{ + float_status *fpst = fpstp; + return float16_muladd(a, b, c, 0, fpst); +} /* * Floating point comparisons produce an integer result. diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 66c4062ea5..444d046500 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,6 +53,7 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4ad470d9e8..142b23abb5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10757,7 +10757,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) TCGV_UNUSED_PTR(fpst); } - if (size == 3) { + if (size == MO_64) { TCGv_i64 tcg_idx = tcg_temp_new_i64(); int pass; @@ -10802,11 +10802,12 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_idx); } else if (!is_long) { - /* 32 bit floating point, or 16 or 32 bit integer. + /* 16 or 32 bit floating point, or 16 or 32 bit integer. * For the 16 bit scalar case we use the usual Neon helpers and * rely on the fact that 0 op 0 == 0 with no side effects. */ TCGv_i32 tcg_idx = tcg_temp_new_i32(); + bool hp = (size == MO_16 ? true : false); int pass, maxpasses; if (is_scalar) { @@ -10829,7 +10830,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) TCGv_i32 tcg_op = tcg_temp_new_i32(); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, size); switch (opcode) { case 0x0: /* MLA */ @@ -10861,8 +10862,14 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) gen_helper_vfp_negs(tcg_op, tcg_op); /* fall through */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_32); - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + read_vec_element_i32(s, tcg_res, rd, pass, size); + if (hp) { + gen_helper_advsimd_muladdh(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } else { + gen_helper_vfp_muladds(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } break; case 0x9: /* FMUL, FMULX */ switch (size) { @@ -10909,7 +10916,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, size); } tcg_temp_free_i32(tcg_op); From patchwork Fri Oct 13 16:24:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115810 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp941129qgn; Fri, 13 Oct 2017 09:48:45 -0700 (PDT) X-Received: by 10.200.37.61 with SMTP id 58mr3046588qtm.187.1507913325189; Fri, 13 Oct 2017 09:48:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913325; cv=none; d=google.com; s=arc-20160816; b=syl4os4QIVD865Mu0bBnX6ogaxL8ah1Otl8BzwSlwyFYoW+1xxf29pDCOfElTm110g LtXxN9aUU6dQVyA2f9zDQt7lZNfrAZyF/l00emCkoFWIKSvEAdbJwAsAc63Osq9U+76o J3XHCOHb66sqi5Ag8raYrYoAMOOfc8M0d8zJWvS2JZMrgeFQCgFscV8n60Wb7BbUOBCy GLL06Qp58CjxhSlme2LoV2/+GOy62JyyVYon1yRQ9uFU92HBEpeq6B7XOFAtRjZRKKfd 44u/D3LyFZJ3AEWVN3sEeO9PJxova2/0OMY7WcDzUj0m7FaRhQXPiiIll3LOnW3fmuNi BRVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8LOwz6//NJMXAgclJcDnSEFpDscUIyCSbJ44FRUXv0I=; b=cXE6UhD5a0HkiOnbMw6a/PbRxe1bySAqGBEYrZ555VnmT7dz+5a77jPMq9gdO3jsmr cFX4on5WtrXYdQTdgbAhuIlEGVeCWjgMFieILhnWZeRIXqscrJafclGBA7Jo5SqXhxYm CvmjP2s0u6+2T5X/QfHiC2ze0WBW2qSw4ZtpNiJVIJD9+Ez4rraovOQ0aGC80LZKvkAB Qz42kK4XaFGSHJqG8WFkfP9k6Ss532J3RCW1bE1v+RZy5TyjM00XF7gUWIZ1oEW2FxwE 2xqg3e59+fE2Cczlr8mOHaby0coEyiZJNoyMHE3nqAC3rYhl43cFF4ld62DSEos+qyzi enKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kaJjjkpT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22e Subject: [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Again a mechanical conversion. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 83 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f7473f97e3..dc7f5f6d88 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3532,6 +3532,88 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Rounds the half-precision floating-point value `a' to an integer, +| and returns the result as a half-precision floating-point value. The +| operation is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_round_to_int(float16 a, float_status *status) +{ + flag aSign; + int aExp; + uint16_t lastBitMask, roundBitsMask; + uint16_t z; + a = float16_squash_input_denormal(a, status); + + aExp = extractFloat16Exp( a ); + if ( 0x19 <= aExp ) { + if ( ( aExp == 0x1F ) && extractFloat16Frac( a ) ) { + return propagateFloat16NaN(a, a, status); + } + return a; + } + if ( aExp <= 0xE ) { + if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a; + status->float_exception_flags |= float_flag_inexact; + aSign = extractFloat16Sign( a ); + switch (status->float_rounding_mode) { + case float_round_nearest_even: + if ( ( aExp == 0xE ) && extractFloat16Frac( a ) ) { + return packFloat16( aSign, 0xF, 0 ); + } + break; + case float_round_ties_away: + if (aExp == 0xE) { + return packFloat16(aSign, 0xF, 0); + } + break; + case float_round_down: + return make_float16(aSign ? 0xBC00 : 0); + case float_round_up: + /* -0.0/1.0f */ + return make_float16(aSign ? 0x8000 : 0x3C00); + } + return packFloat16( aSign, 0, 0 ); + } + lastBitMask = 1; + lastBitMask <<= 0x19 - aExp; + roundBitsMask = lastBitMask - 1; + z = float16_val(a); + switch (status->float_rounding_mode) { + case float_round_nearest_even: + z += lastBitMask>>1; + if ((z & roundBitsMask) == 0) { + z &= ~lastBitMask; + } + break; + case float_round_ties_away: + z += lastBitMask >> 1; + break; + case float_round_to_zero: + break; + case float_round_up: + if (!extractFloat16Sign(make_float16(z))) { + z += roundBitsMask; + } + break; + case float_round_down: + if (extractFloat16Sign(make_float16(z))) { + z += roundBitsMask; + } + break; + default: + abort(); + } + z &= ~ roundBitsMask; + if (z != float16_val(a)) { + status->float_exception_flags |= float_flag_inexact; + } + return make_float16(z); + +} + /*---------------------------------------------------------------------------- | Returns the result of adding the absolute values of the half-precision | floating-point values `a' and `b'. If `zSign' is 1, the sum is negated diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a7435e2a5b..856f67cf12 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -346,6 +346,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status); | Software half-precision operations. *----------------------------------------------------------------------------*/ +float16 float16_round_to_int(float16, float_status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); From patchwork Fri Oct 13 16:24:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115799 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp932486qgn; Fri, 13 Oct 2017 09:39:50 -0700 (PDT) X-Received: by 10.55.33.203 with SMTP id f72mr2902220qki.176.1507912790488; Fri, 13 Oct 2017 09:39:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912790; cv=none; d=google.com; s=arc-20160816; b=m/e8Diq0Gwf6hI+1zuu7AqQfxUarans5bVwNVrCkd90Uuj1Sao1+4IHm5xKykrU3eH BQPOH7LQsRmDz2fdmJWSgDSVNDKiot25Vr2W0GisqV0orGg0O26D5fkmAyL40XFAPu1X lsHWwiV/wk5wk8Q5gWTyq8JGcubEXH4ZpeDCIHbc/kWp4sShfKsLn1PfhdGmo7gTYaVi czZRBzwq8kww0QtR7A16K3YWWn+jik9Uzh2jXAtLaCYkvrpUGDtdqSpqktz2YCRLOqcc XrhrBCXUGi/FMul1eQ+jQOIniOsQ0zwBOY7jj0jJyWwzCp0rj119xYJNl641ga8GY/m/ sOmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xj+jn6t73JlhKSswsXO8P/txoe4iBUWKkNZdRIQnS9k=; b=lABZglRnaMVmovBr555/FkfKJVpGc6Tx1/nObkzbVyLUcQnpDqdJCxqX5S6oC/6bMl blXg0Nd/gf4Sc5e6sAimzpoQFVXtP3grJeOYakkySoXt8JGTv5wHthE1aC53Hp6bYmy2 Sj30G6tJ7/EctlBTTCTj1HykPglsQUqXZEF5sASe7dXT5UI2SKtz2RaI0RMjwPSfRH8Y M2y7JrG/HlBkh+ZXPJmejCyqBjqgWgQxRUvRz71QqJFdx79KWH0Ux/r+9RVwtyNDALeN I1EJ4V9C5sLqhkoL4Mr2ou6ZyegWAgeOcNZePdZOh+0qcB9hjDUP4+Utq0F4EVr4keet lvew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MGKIdY1i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a simple pattern based framework for testing our softfloat implementation. It is easier to use while debugging softfloat itself than indirectly with a tool like risu. As the softfloat library is built against given targets we need a version per target architecture we build. Signed-off-by: Alex Bennée --- tests/Makefile.include | 8 ++++++- tests/test-softfloat.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 tests/test-softfloat.c -- 2.14.1 diff --git a/tests/Makefile.include b/tests/Makefile.include index 4ca15e6817..8bf1dfd19a 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -156,6 +156,10 @@ check-unit-y += tests/ptimer-test$(EXESUF) gcov-files-ptimer-test-y = hw/core/ptimer.c check-unit-y += tests/test-qapi-util$(EXESUF) gcov-files-test-qapi-util-y = qapi/qapi-util.c +check-unit-y += tests/test-softfloat$(EXESUF) +gcov-files-test-softfloat-y = fpu/softfloat.c +check-unit-y += tests/test-softfloat-aarch64$(EXESUF) +gcov-files-test-softfloat-aarch64-y = fpu/softfloat.c check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh @@ -555,7 +559,7 @@ test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \ tests/rcutorture.o tests/test-rcu-list.o \ tests/test-qdist.o tests/test-shift128.o \ tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \ - tests/atomic_add-bench.o + tests/atomic_add-bench.o tests/test-softfloat.o $(test-obj-y): QEMU_INCLUDES += -Itests QEMU_CFLAGS += -I$(SRC_PATH)/tests @@ -604,6 +608,8 @@ tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(tes tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y) tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) +tests/test-softfloat$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o +tests/test-softfloat-aarch64$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c new file mode 100644 index 0000000000..d7b740e1cb --- /dev/null +++ b/tests/test-softfloat.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017, Linaro + * Author: Alex Bennée + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "fpu/softfloat.h" + +typedef struct { + float_status initial_status; + float16 in; + float16 out; + uint8_t final_exception_flags; +} f16_test_data; + +static void test_f16_round_to_int(void) +{ + int i; + float16 out; + float_status flags, *fp = &flags; + f16_test_data test_data[] = { + { { /* defaults */ }, 0x87FF, 0x8000 }, + { { /* defaults */ }, 0xE850, 0xE850 }, + { { /* defaults */ }, 0x0000, 0x0000 }, + { { /* defaults */ }, 0x857F, 0x8000 }, + { { /* defaults */ }, 0x74FB, 0x74FB }, + /* from risu 3b4: 4ef98945 frintp v5.8h, v10.8h */ + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x06b1, 0x3c00, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x6966, 0x6966, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x83c0, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xa619, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x9cf4, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee11, 0xee11, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee5c, 0xee5c, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x8004, 0x8000, 0 } + }; + + for (i = 0; i < ARRAY_SIZE(test_data); ++i) { + flags = test_data[i].initial_status; + out = float16_round_to_int(test_data[i].in, fp); + + if (!(test_data[i].out == out)) { + fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n", + __func__, i, test_data[i].out, out); + g_test_fail(); + } + } +} + +int main(int argc, char *argv[]) +{ + g_test_init(&argc, &argv, NULL); + g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int); + return g_test_run(); +} From patchwork Fri Oct 13 16:24:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115806 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp937392qgn; Fri, 13 Oct 2017 09:44:35 -0700 (PDT) X-Received: by 10.55.74.194 with SMTP id x185mr2886597qka.32.1507913075190; Fri, 13 Oct 2017 09:44:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913075; cv=none; d=google.com; s=arc-20160816; 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X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 17 ++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 241fee9d93..63b2bbd4b2 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -585,6 +585,23 @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) return float16_muladd(a, b, c, 0, fpst); } +/* round to integral */ +float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) +{ + int old_flags = get_float_exception_flags(fp_status), new_flags; + float16 ret; + + ret = float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags = get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); + } + + return ret; +} + /* * Floating point comparisons produce an integer result. * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 444d046500..ce36d81091 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -59,3 +59,4 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 142b23abb5..bbc0d96f01 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10588,6 +10588,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { int fpop, opcode, a; int rn, rd; + int is_q; + int pass; + TCGv_i32 tcg_rmode; + TCGv_ptr tcg_fpstatus; + bool need_rmode = false; + int rmode; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); @@ -10608,12 +10614,62 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6c: /* FCMGE (zero) */ case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd); + return; + break; + case 0x28: /* FRINTP */ + need_rmode = true; + rmode = FPROUNDING_POSINF; break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); } + is_q = extract32(insn, 30, 1); + + if (!fp_access_check(s)) { + return; + } + + tcg_fpstatus = get_fpstatus_ptr(); + + if (need_rmode) { + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + } else { + TCGV_UNUSED_I32(tcg_rmode); + } + + for (pass = 0; pass < (is_q ? 8 : 4); pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_16); + + switch (fpop) { + case 0x28: /* FRINTP */ + gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + } + + if (!is_q) { + clear_vec_high(s, rd); + } + + if (need_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + } + + tcg_temp_free_ptr(tcg_fpstatus); } /* AdvSIMD scalar x indexed element From patchwork Fri Oct 13 16:24:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115808 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp939227qgn; Fri, 13 Oct 2017 09:46:33 -0700 (PDT) X-Received: by 10.200.3.87 with SMTP id w23mr2973561qtg.98.1507913193713; Fri, 13 Oct 2017 09:46:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913193; cv=none; d=google.com; s=arc-20160816; b=Uq9nS4RjQbMtMZudJBkQd0I74ecJVqgjbt8seHwrpJ51DdDbWe54iJs9rdjjA64Co6 /4aja3PnvggzUJmraXTNk8bMGqpkd9IzMUFTIXXe7XaqNWl4qAA/PChgRSIERJKLeAxF 0F6jjk5gmFFcA2iGj1fxn14fMFZe0zW7cerYB+6R6tsyYZ8uGH8CKZxsdGEJuyOGh0o7 46clagXp3JxVb8IJ0B0oH1DYGJqBTPVtTIBVjfFbh0+Mdi3kHHKxyzfPLNLF53jAjyre RGLjc42ToG+RvSnPTG3f8Yaxk7v2oUo1PoW1evilTxjHWez0lfqFIiGolLR2DusjfGuZ rcyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FnDwdoES4ku0h3pXwWjXAGZvZqvV94B8hZzSSyJtYDE=; b=KMOgzf2ZMNCbuWg7Ue9oowuud5nAPF2AhbrGop4fMLOXluTGqRSIkE/W+3n3uvAO6j XJqo9XwnkljC4iZ+4xAdCQ/UqM7N71Nha34WLow0a9SGH9NJBrAA6y/SMZklA0LI8olu VL1trKYdDbnFOVC/OP5bTe2VcOwYnxo76UOU6VpoU9eUaLvnt+R4kBLjleBBW6WxZs8a Hhn7D+2PVQxbP15DJXD7b0FLMeVhvfrCQkgttYPph5HKJ488WZjtVrNdNQP52vKpfDz3 B/7VelJv4I33LAkABEVl7xhgIEFMtzxvcvonAfadGMV4/JpHGQc/YMowsHK3J0FdiZMo MeIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QpCpnp+V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I didn't have another reference for this so I wrote it from first principles. The roundAndPackInt16 works with the same shifted input as roundAndPacknt32 but with different constants for invalid testing for overflow. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 99 insertions(+) -- 2.14.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index dc7f5f6d88..63f7cd1226 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,6 +132,62 @@ static inline flag extractFloat16Sign(float16 a) return float16_val(a)>>15; } +/*---------------------------------------------------------------------------- +| Takes a 32-bit fixed-point value `absZ' with binary point between bits 6 +| and 7, and returns the properly rounded 16-bit integer corresponding to the +| input. If `zSign' is 1, the input is negated before being converted to an +| integer. Bit 31 of `absZ' must be zero. Ordinarily, the fixed-point input +| is simply rounded to an integer, with the inexact exception raised if the +| input cannot be represented exactly as an integer. However, if the fixed- +| point input is too large, the invalid exception is raised and the largest +| positive or negative integer is returned. +*----------------------------------------------------------------------------*/ + +static int16_t roundAndPackInt16(flag zSign, uint32_t absZ, float_status *status) +{ + int8_t roundingMode; + flag roundNearestEven; + int8_t roundIncrement, roundBits; + int16_t z; + + roundingMode = status->float_rounding_mode; + roundNearestEven = ( roundingMode == float_round_nearest_even ); + + switch (roundingMode) { + case float_round_nearest_even: + case float_round_ties_away: + roundIncrement = 0x40; + break; + case float_round_to_zero: + roundIncrement = 0; + break; + case float_round_up: + roundIncrement = zSign ? 0 : 0x7f; + break; + case float_round_down: + roundIncrement = zSign ? 0x7f : 0; + break; + default: + abort(); + } + roundBits = absZ & 0x7F; + + absZ = ( absZ + roundIncrement )>>7; + absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven ); + z = absZ; + if ( zSign ) z = - z; + + if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { + float_raise(float_flag_invalid, status); + return zSign ? (int16_t) 0x8000 : 0x7FFF; + } + if (roundBits) { + status->float_exception_flags |= float_flag_inexact; + } + return z; + +} + /*---------------------------------------------------------------------------- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to the @@ -4509,6 +4565,48 @@ int float16_unordered_quiet(float16 a, float16 b, float_status *status) return 0; } +/*---------------------------------------------------------------------------- +| Returns the result of converting the half-precision floating-point value +| `a' to the 16-bit two's complement integer format. The conversion is +| performed according to the IEC/IEEE Standard for Binary Floating-Point +| Arithmetic---which means in particular that the conversion is rounded +| according to the current rounding mode. If `a' is a NaN, the largest +| positive integer is returned. Otherwise, if the conversion overflows, the +| largest integer with the same sign as `a' is returned. +*----------------------------------------------------------------------------*/ + +int16_t float16_to_int16(float32 a, float_status *status) +{ + flag aSign; + int aExp; + uint32_t aSig; + + a = float16_squash_input_denormal(a, status); + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + if ( ( aExp == 0x1F ) && aSig ) aSign = 0; + if ( aExp ) aSig |= 0x0400; /* implicit bit */ + + /* At this point the binary point is between 10:9, we need to + * shift the significand it up by the +ve exponent to get the + * integer and then move the binary point down to the 7:6 for + * the final roundAnPackInt16. + * + * Even with the maximum +ve shift everything happily fits in the + * 32 bit aSig. + */ + aExp -= 15; /* exp bias */ + if (aExp >= 3) { + aSig <<= aExp - 3; + } else { + /* ensure small numbers still get rounded */ + shift32RightJamming( aSig, 3 - aExp, &aSig ); + } + + return roundAndPackInt16(aSign, aSig, status); +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 856f67cf12..49517b19ea 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -338,6 +338,7 @@ static inline float64 uint16_to_float64(uint16_t v, float_status *status) | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ float16 float32_to_float16(float32, flag, float_status *status); +int16_t float16_to_int16(float32 a, float_status *status); float32 float16_to_float32(float16, flag, float_status *status); float16 float64_to_float16(float64 a, flag ieee, float_status *status); float64 float16_to_float64(float16 a, flag ieee, float_status *status); From patchwork Fri Oct 13 16:24:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115803 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp936058qgn; Fri, 13 Oct 2017 09:43:17 -0700 (PDT) X-Received: by 10.55.75.15 with SMTP id y15mr2608782qka.321.1507912997537; Fri, 13 Oct 2017 09:43:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507912997; cv=none; d=google.com; s=arc-20160816; b=bdfry9opBGHDmFdQo2SA/Umy51+TRDSaNewidZnfzysagjYzjJcTfrmmALDUwP2dxD qscZjM2cR0c0N3ouMjCmQu/V9NOhk7yILDdvUEZpATibMghwjpVolE0PhOCzzH7oXxHv 2/Xs2KKxPcqzn9qcuwMxLheWbsYYOzoVc6gg1ufupDYf9qKajsT/u+liXLGKeR3lYHXu lkw/QLmZN5eoZyPSIsPxZl/B16QtoH8JsbTXd4ABxD+I0c08c3iJpwjv4xlxzs7N5PVC qnx00qR+YRHt2Js4R1W8THEqBsaZ5mmanqaJRTHdqeClKrqCgWC+8NTeryeKkWfTyGjj oEpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=nMItd6ppJG4aBRKRJCZvCu1LGWnUChKl21uE6WyTYsM=; b=MMD2Rlb2Km4DwJDchTzinkAK6K+u25g+HC3XxWGOFRGPApqCUgKPRzvk61Nw4AWEcA uph1mqhOZEFeP/cmZXxXP7xrT56Z5swpS8jzajGuRSPqFt1cXM0lefKgHDb/jMN2QkMn BgevTFcNxyUdgUSEYhI2Lmrxz/877y6maHi2aTOTxPQAYY3ZvztvuZeK3Vripk/2FS33 hwXAQUxoKBrGuVnXn3EzepHbHahD+bkIU4ui+fN+1NLCmLh/te7I4chWeiJYtag1gv5/ +s2LybYEKMd91KR7jpfJAwONqFnuEJph1XHHaoG9WwEUwNQpuex1EQmypZ0I4GeHN9Vg EZFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ftQ3Yj/O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- tests/test-softfloat.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.14.1 diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c index d7b740e1cb..e1f356572d 100644 --- a/tests/test-softfloat.c +++ b/tests/test-softfloat.c @@ -16,6 +16,31 @@ typedef struct { uint8_t final_exception_flags; } f16_test_data; +static void test_f16_convert_to_int(void) +{ + int i; + float16 out; + float_status flags, *fp = &flags; + f16_test_data test_data[] = { + /* from risu fcvtps v23.4h, v16.4h */ + { { .float_rounding_mode = float_round_up}, 0xa619, 0xb860, 0 }, + { { .float_rounding_mode = float_round_up}, 0x83c0, 0xff91, 0 }, + { { .float_rounding_mode = float_round_up}, 0x6966, 0x0001, 0 }, + { { .float_rounding_mode = float_round_up}, 0x06b1, 0x0001, 0 }, + }; + + for (i = 0; i < ARRAY_SIZE(test_data); ++i) { + flags = test_data[i].initial_status; + out = float16_to_int16(test_data[i].in, fp); + + if (!(test_data[i].out == out)) { + fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n", + __func__, i, test_data[i].out, out); + g_test_fail(); + } + } +} + static void test_f16_round_to_int(void) { int i; @@ -54,5 +79,6 @@ int main(int argc, char *argv[]) { g_test_init(&argc, &argv, NULL); g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int); + g_test_add_func("/softfloat/f16/convert_to_int", test_f16_convert_to_int); return g_test_run(); } From patchwork Fri Oct 13 16:24:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 115812 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp943389qgn; Fri, 13 Oct 2017 09:51:25 -0700 (PDT) X-Received: by 10.237.55.66 with SMTP id i60mr2826771qtb.176.1507913485613; Fri, 13 Oct 2017 09:51:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507913485; cv=none; d=google.com; s=arc-20160816; b=JYeXcTBNMNV+x8LTiwgMr5ojeAWrZ5am8A/QnpolgS9iWBBa91czHEvTjhdLQZ4j7m zYq0SYFRScevEPPASqr4wkdzl8FQescd6WLXNhxM+rUuOeBdr/DG9EJvWY1QL+3sjH0P 7/BJCRPVneTbz3s3EPRbb4TRZiPFPGU17TNCBf9pgt+kiqmbUyfrxe2lrHS5QHNdbQ8p oI9NtH0WNdCX1qIIQ1Pp4aJpsHMXzIHlyLHNlQxis4xdI7+0ktsj09ZMWPbyJDdC3+dE ou3j1dYdHqWHtdgFdFIq6elrPszV8g/36DrF/WcjgDxR8PAZgptIpoYo2xfUdWomDmTW p0xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=87WPXtEq182CYCLMvUSkyQhzyZD3smXOGfqeGXUeGV8=; b=K/Af4wbsAH/ox30wtaCNgwig+ZdWiuGCAkr8zMDRk9M2KZG69ECjLRImn8PCOlEHte ipjNEj/alEr3XOPJYnm/lGTSnbjR2R/WxiY6r0W/3YOkmG/ucQJpdO1PmojpYVtJvxND QqHzkWzh5u1SvTyMh0ZUCubhkmR3BGD/te/brzV2dOS7PMEomYfgedi1xi0CRZTHVcff 43jCZ70lE9jlRXHxDh3loP2ljQDOpNkhSf6EU5hVg35zQfn3leBdEU7dJGcv9PtOE2fM /Nbq/0i37bKhBD2bQObB5jOIV9rJnBdW1yLa38JgW9IhVOJSY40x4u+QHBryxp8kU1Ly uyvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PLLyW+kY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 20 ++++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 7 +++++++ 3 files changed, 28 insertions(+) -- 2.14.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 63b2bbd4b2..1cc2758eac 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -639,3 +639,23 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) float16 f1 = float16_abs(b); return -float16_lt(f1, f0, fpst); } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst = fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ce36d81091..73a985d1a4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -60,3 +60,4 @@ DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bbc0d96f01..ac71911a1a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10620,6 +10620,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) need_rmode = true; rmode = FPROUNDING_POSINF; break; + case 0x2a: /* FCVTPS */ + need_rmode = true; + rmode = FPROUNDING_POSINF; + break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -10647,6 +10651,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); switch (fpop) { + case 0x2a: /* FCVTPS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x28: /* FRINTP */ gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); break;