From patchwork Fri Sep 11 07:44:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 295386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D002C43461 for ; Fri, 11 Sep 2020 07:45:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D14A920829 for ; Fri, 11 Sep 2020 07:45:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=aj.id.au header.i=@aj.id.au header.b="iS1elgHb"; dkim=temperror (0-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="TvMKmdw9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725795AbgIKHpo (ORCPT ); Fri, 11 Sep 2020 03:45:44 -0400 Received: from wout3-smtp.messagingengine.com ([64.147.123.19]:42671 "EHLO wout3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725535AbgIKHpd (ORCPT ); Fri, 11 Sep 2020 03:45:33 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id C29E1C38; Fri, 11 Sep 2020 03:45:32 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Fri, 11 Sep 2020 03:45:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=wCrir7Nj5a6Sf jiU7ykDZoyQRg2FmImk7NG1eiROHdc=; b=iS1elgHbtQSPnOb33kz9zoK+IaPsq UCE2uaZnMVrKLnayOH4az+rcut4AO7S4jCewIwt0f1Ng4mZTlVNJRXIdxPKQ9PYQ pQ9GeVjDld2ergKtlGSgpYs52JXObYv0kHMe3bvCZjivugoEX5ATZxEK0SCs8WuD blUeQ1UZZPA0ZsLG/HxYQj1i0p4OXWTyeuRe0F3HOX2EFOzc2O7zXXMeyHsWYqju mniSv6d6Ycp01dS2FqYW3YdC1l5ZKcU1cUnFgrAoipm5m/Omh0HKo7t0tCfGy3wt PpkEGhBklJeBXm4dQmRxzFBIx9US53HlX9zcNBh4XLjKrSf8LveFWUVHw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=wCrir7Nj5a6SfjiU7ykDZoyQRg2FmImk7NG1eiROHdc=; b=TvMKmdw9 DVeVOIGMluHTvnEZSqDjcmgxs1wlp3p5okgKRnA47slWJddjIzDLCO87JxT07zNl DdNgZHi+zPJsXVDUoPBsCwCA9XIDd6qNkqgmQvF/hJDtcSDLAiRd7MckCQt86nVC 48R96nUF+6KBMdjXdyQGTmTeaog/5GTtAoOVIhwf/ri5dPvm7WVtIsEPsuOquIdR IlfQaPT77Q1M1rwngI2589HsAKMNbFWS8QTIvut4drtSw0aPpCC+PU1eftUPNJWN ZuOoPGdZUiZmPY4e4fUQSIG9Wq5MX8GGI/tftMSQh5Xj2eeSmJ1uIOyu5/4w+6v0 Kgt1czQxRnc6eg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrudehkedguddvgecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfies rghjrdhiugdrrghuqeenucggtffrrghtthgvrhhnpeejgfdvveehteekveeggeellefgle etteejffelffdvudduveeiffegteelvefhteenucfkphepudegrddvrddutdelrdekheen ucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnhgurh gvfiesrghjrdhiugdrrghu X-ME-Proxy: Received: from mistburn.lan (ppp14-2-109-85.adl-apt-pir-bras32.tpg.internode.on.net [14.2.109.85]) by mail.messagingengine.com (Postfix) with ESMTPA id 7725B3064685; Fri, 11 Sep 2020 03:45:29 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org, joel@jms.id.au, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt: bindings: mmc: Add phase control properties for the Aspeed SDHCI Date: Fri, 11 Sep 2020 17:14:50 +0930 Message-Id: <20200911074452.3148259-2-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add properties to control the phase delay for input and output data. Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml index 987b287f3bff..d7b605968c8a 100644 --- a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml @@ -61,6 +61,14 @@ patternProperties: sdhci,auto-cmd12: type: boolean description: Specifies that controller should use auto CMD12 + "aspeed,input-phase": + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + The input phase delay value. + "aspeed,output-phase": + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + The output phase delay value. required: - compatible - reg From patchwork Fri Sep 11 07:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 256327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD011C43461 for ; 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Fri, 11 Sep 2020 03:45:32 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org, joel@jms.id.au, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] mmc: sdhci-of-aspeed: Expose phase delay tuning Date: Fri, 11 Sep 2020 17:14:51 +0930 Message-Id: <20200911074452.3148259-3-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The Aspeed SD/eMMC controllers feature up to two SDHCIs alongside a a set of "global" configuration registers. The global configuration registers house controller-specific settings that aren't exposed by the SDHCI, one example being a register for phase tuning. The phase tuning feature is new in the AST2600 design. It's exposed as a single register in the global register set and controls both the input and output phase adjustment for each slot. As the settings are slot-specific, the values to program are extracted from properties in the SDHCI devicetree nodes. Signed-off-by: Andrew Jeffery --- In v2: * Rework devicetree parsing to minimise state disruption * Switch some log statements from dev_info() to dev_dbg() --- drivers/mmc/host/sdhci-of-aspeed.c | 126 +++++++++++++++++++++++++++-- 1 file changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 4f008ba3280e..c61eb42e1ebb 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -16,9 +16,19 @@ #include "sdhci-pltfm.h" -#define ASPEED_SDC_INFO 0x00 -#define ASPEED_SDC_S1MMC8 BIT(25) -#define ASPEED_SDC_S0MMC8 BIT(24) +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1_MMC8 BIT(25) +#define ASPEED_SDC_S0_MMC8 BIT(24) +#define ASPEED_SDC_PHASE 0xf4 +#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) +#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) +#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) +#define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) +#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) +#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3) +#define ASPEED_SDC_S0_PHASE_IN_EN BIT(2) +#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) +#define ASPEED_SDC_PHASE_MAX 31 struct aspeed_sdc { struct clk *clk; @@ -28,9 +38,21 @@ struct aspeed_sdc { void __iomem *regs; }; +struct aspeed_sdhci_phase_desc { + u32 value_mask; + u32 enable_mask; + u8 enable_value; +}; + +struct aspeed_sdhci_phase { + struct aspeed_sdhci_phase_desc in; + struct aspeed_sdhci_phase_desc out; +}; + struct aspeed_sdhci { struct aspeed_sdc *parent; u32 width_mask; + const struct aspeed_sdhci_phase *phase; }; static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, @@ -50,6 +72,22 @@ static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, spin_unlock(&sdc->lock); } +static void +aspeed_sdc_configure_phase(struct aspeed_sdc *sdc, + const struct aspeed_sdhci_phase_desc *phase, + uint8_t value) +{ + u32 reg; + + spin_lock(&sdc->lock); + reg = readl(sdc->regs + ASPEED_SDC_PHASE); + reg &= ~(phase->enable_mask | phase->value_mask); + reg |= value << __ffs(phase->value_mask); + reg |= phase->enable_value << __ffs(phase->enable_mask); + writel(reg, sdc->regs + ASPEED_SDC_PHASE); + spin_unlock(&sdc->lock); +} + static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host; @@ -155,8 +193,49 @@ static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, return (delta / 0x100) - 1; } +static int aspeed_sdhci_configure_of(struct platform_device *pdev, + struct aspeed_sdhci *sdhci) +{ + struct device_node *np; + struct device *dev; + u32 phase; + + if (!sdhci->phase) + return 0; + + dev = &pdev->dev; + np = dev->of_node; + + if (!of_property_read_u32(np, "aspeed,input-phase", &phase)) { + if (phase <= ASPEED_SDC_PHASE_MAX) { + aspeed_sdc_configure_phase(sdhci->parent, + &sdhci->phase->in, + phase); + dev_dbg(dev, "Input phase adjustment: %u", phase); + } else { + dev_err(dev, "Invalid input phase value: %u", phase); + return -EINVAL; + } + } + + if (!of_property_read_u32(np, "aspeed,output-phase", &phase)) { + if (phase <= ASPEED_SDC_PHASE_MAX) { + aspeed_sdc_configure_phase(sdhci->parent, + &sdhci->phase->out, + phase); + dev_dbg(dev, "Output phase adjustment: %u", phase); + } else { + dev_err(dev, "Invalid output phase value: %u", phase); + return -EINVAL; + } + } + + return 0; +} + static int aspeed_sdhci_probe(struct platform_device *pdev) { + const struct aspeed_sdhci_phase *phase; struct sdhci_pltfm_host *pltfm_host; struct aspeed_sdhci *dev; struct sdhci_host *host; @@ -181,7 +260,10 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) return -EINVAL; dev_info(&pdev->dev, "Configuring for slot %d\n", slot); - dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; + phase = of_device_get_match_data(&pdev->dev); + if (phase) + dev->phase = &phase[slot]; sdhci_get_of_property(pdev); @@ -195,6 +277,10 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) goto err_pltfm_free; } + ret = aspeed_sdhci_configure_of(pdev, dev); + if (ret) + goto err_sdhci_add; + ret = mmc_of_parse(host->mmc); if (ret) goto err_sdhci_add; @@ -230,10 +316,40 @@ static int aspeed_sdhci_remove(struct platform_device *pdev) return 0; } +static const struct aspeed_sdhci_phase ast2600_sdhci_phase[] = { + /* SDHCI/Slot 0 */ + [0] = { + .in = { + .value_mask = ASPEED_SDC_S0_PHASE_IN, + .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .value_mask = ASPEED_SDC_S0_PHASE_OUT, + .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, + .enable_value = 3, + }, + }, + /* SDHCI/Slot 1 */ + [1] = { + .in = { + .value_mask = ASPEED_SDC_S1_PHASE_IN, + .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .value_mask = ASPEED_SDC_S1_PHASE_OUT, + .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, + .enable_value = 3, + }, + }, +}; + +/* If supported, phase adjustment fields are stored in the data pointer */ static const struct of_device_id aspeed_sdhci_of_match[] = { { .compatible = "aspeed,ast2400-sdhci", }, { .compatible = "aspeed,ast2500-sdhci", }, - { .compatible = "aspeed,ast2600-sdhci", }, + { .compatible = "aspeed,ast2600-sdhci", .data = ast2600_sdhci_phase }, { } }; From patchwork Fri Sep 11 07:44:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 295385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EA1DC43461 for ; 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Fri, 11 Sep 2020 03:45:35 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org, joel@jms.id.au, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] ARM: dts: tacoma: Add phase delay for eMMC Date: Fri, 11 Sep 2020 17:14:52 +0930 Message-Id: <20200911074452.3148259-4-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Adjust the phase delay to avoid data timeout splats like the following: [ 731.368601] mmc0: Timeout waiting for hardware interrupt. [ 731.374644] mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== [ 731.381828] mmc0: sdhci: Sys addr: 0x00000020 | Version: 0x00000002 [ 731.389012] mmc0: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000020 [ 731.396194] mmc0: sdhci: Argument: 0x00462a18 | Trn mode: 0x0000002b [ 731.403377] mmc0: sdhci: Present: 0x01f70106 | Host ctl: 0x00000017 [ 731.410559] mmc0: sdhci: Power: 0x0000000f | Blk gap: 0x00000000 [ 731.417733] mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000107 [ 731.424915] mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000 [ 731.432098] mmc0: sdhci: Int enab: 0x03ff008b | Sig enab: 0x03ff008b [ 731.439282] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 731.446464] mmc0: sdhci: Caps: 0x01f80080 | Caps_1: 0x00000007 [ 731.453647] mmc0: sdhci: Cmd: 0x0000193a | Max curr: 0x001f0f08 [ 731.460829] mmc0: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff [ 731.468013] mmc0: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00000900 [ 731.475195] mmc0: sdhci: Host ctl2: 0x0000008b [ 731.480139] mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xbe040200 [ 731.487321] mmc0: sdhci: ============================================ Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 5f4ee67ac787..94ec301ceb73 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -179,6 +179,8 @@ &emmc_controller { &emmc { status = "okay"; + aspeed,input-phase = <0x7>; + aspeed,output-phase = <0x1f>; }; &fsim0 {