From patchwork Fri Sep 18 14:48:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 257177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ECF3C43464 for ; Fri, 18 Sep 2020 14:48:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 175A62311A for ; Fri, 18 Sep 2020 14:48:57 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 18 Sep 2020 14:48:53 +0000 (GMT) X-AuditID: cbfec7f4-65dff7000000176d-53-5f64c8d549a4 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 98.2E.06314.5D8C46F5; Fri, 18 Sep 2020 15:48:53 +0100 (BST) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20200918144852eusmtip15af5d2da0fd731f0d3933141779eef8c~16C9eRFtd1497714977eusmtip1h; Fri, 18 Sep 2020 14:48:52 +0000 (GMT) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Robin Murphy , Bartlomiej Zolnierkiewicz , Mauro Carvalho Chehab , Tomasz Figa Subject: [PATCH v2 2/4] media: platform: exynos4-is: add support for generic IOMMU-DMA glue code Date: Fri, 18 Sep 2020 16:48:31 +0200 Message-Id: <20200918144833.14618-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918144833.14618-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjleLIzCtJLcpLzFFi42LZduzned2rJ1LiDZ7NUrfYOGM9q8X58xvY LXo2bGW1mHF+H5PF2iN32S2WbfrDZHHwwxNWi/anL5ktPrf+Y3Pg9Fgzbw2jx+yGiywem1Z1 snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXRsf3hUwFC3Qrem42szQwXlLtYuTkkBAwkVhy 5Q5rFyMXh5DACkaJfftOsUM4Xxgldsy4zQLhfGaUaP9ynBGmZU7nOUaIxHJGic5Tc1nhWibt /8oKUsUmYCjR9baLDcQWEXCSWDjrL9hcZoFNTBK73nxg6mLk4BAWSJKYdMEcpIZFQFVi6qU7 YPW8ArYS8y4dZIbYJi+xesMBZpByTgE7iatNliBjJAT+s0lc3X0f6iIXiWX7NkHVC0u8Or6F HcKWkTg9uYcFoqGZUeLhubXsEE4Po8TlphlQ3dYSd879YgPZwCygKbF+lz5E2FHi1415LCBh CQE+iRtvBUHCzEDmpG3TmSHCvBIdbUIQ1WoSs46vg1t78MIlqHM8JOYdnswGCZ+JjBI3dq1n mcAoPwth2QJGxlWM4qmlxbnpqcVGeanlesWJucWleel6yfm5mxiBqeP0v+NfdjDu+pN0iFGA g1GJh/fFvJR4IdbEsuLK3EOMEhzMSiK8TmdPxwnxpiRWVqUW5ccXleakFh9ilOZgURLnNV70 MlZIID2xJDU7NbUgtQgmy8TBKdXAKM8h+XYLT8NrwfI3Z1b9Z5Jfs/V4Y8+0+KYHGXmscvmx Zl4vd16r5rb1WJg9NXC5gEL8dkn3PsvsrfaZpdtm3PM1105YliCT83fXfTdB594sg2iRhkXf mBImPnv9ucs/Wz6fdfrcFQsL/z0XmDqr7Mecx3yGeesEY4o/qUyclsRn4Fg78+YKJZbijERD Leai4kQANlKKShkDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGLMWRmVeSWpSXmKPExsVy+t/xu7pXT6TEG/Qe5rTYOGM9q8X58xvY LXo2bGW1mHF+H5PF2iN32S2WbfrDZHHwwxNWi/anL5ktPrf+Y3Pg9Fgzbw2jx+yGiywem1Z1 snn0bVnF6PF5k1wAa5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJpZ6hsXmslZGpkr6dTUpq TmZZapG+XYJeRsf3hUwFC3Qrem42szQwXlLtYuTkkBAwkZjTeY6xi5GLQ0hgKaNE84mtrBAJ GYmT0xqgbGGJP9e62CCKPjFKvN13FyzBJmAo0fUWJMHJISLgIrF/z1NmkCJmgW1MEr+2LmLq YuTgEBZIkDjxzgekhkVAVWLqpTtg9bwCthLzLh1khlggL7F6wwFmkHJOATuJq02WIGEhoJLW JUvYJjDyLWBkWMUoklpanJueW2yoV5yYW1yal66XnJ+7iREYxtuO/dy8g/HSxuBDjAIcjEo8 vC/mpcQLsSaWFVfmHmKU4GBWEuF1Ons6Tog3JbGyKrUoP76oNCe1+BCjKdBNE5mlRJPzgTGW VxJvaGpobmFpaG5sbmxmoSTO2yFwMEZIID2xJDU7NbUgtQimj4mDU6qBUfGt4Y2zLy7MUp8S vyrYuc9e0Vxy/cfySyfdQjod/n4WErPr8LbL9pz9ZW+4TXuo59aSkAmz0ueLuglzt0q/sr3K YrAn5LfZta6fmdODbuRkZDMflUt5LSmnvkfoSa7vvJN3vtxWW6u894vLoi1L49cflPwb1SjX mlLaFnv03sSN0/6vr7mYrMRSnJFoqMVcVJwIAC5MSwx5AgAA X-CMS-MailID: 20200918144853eucas1p1b04a96d33c66052f845b3979a3105f9f X-Msg-Generator: CA X-RootMTR: 20200918144853eucas1p1b04a96d33c66052f845b3979a3105f9f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200918144853eucas1p1b04a96d33c66052f845b3979a3105f9f References: <20200918144833.14618-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4-IS driver relied on the was the ARM DMA-IOMMU glue code worked - mainly it relied on the fact that the allocator used first-fit algorithm and the first allocated buffer were at 0x0 DMA/IOVA address. This is not true for the generic IOMMU-DMA glue code that will be used for ARM architecture soon, so add the needed code to support such case. Signed-off-by: Marek Szyprowski --- drivers/media/platform/exynos4-is/fimc-is.c | 72 +++++++++++++++++---- drivers/media/platform/exynos4-is/fimc-is.h | 4 +- 2 files changed, 63 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c index 69510a700798..98fb242b6ac7 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.c +++ b/drivers/media/platform/exynos4-is/fimc-is.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -269,7 +270,7 @@ int fimc_is_cpu_set_power(struct fimc_is *is, int on) mcuctl_write(0, is, REG_WDT_ISP); /* Cortex-A5 start address setting */ - mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR); + mcuctl_write(is->memory.base, is, MCUCTL_REG_BBOAR); /* Enable and start Cortex-A5 */ pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION); @@ -330,37 +331,82 @@ int fimc_is_start_firmware(struct fimc_is *is) return ret; } +#ifdef CONFIG_IOMMU_DMA +#define FIMC_IS_CPU_MEM_BASE (0) +static int fimc_iommu_remap_cpu_memory(struct fimc_is *is) +{ + struct device *dev = &is->pdev->dev; + struct sg_table sgt; + int ret; + + if (!dev_iommu_priv_get(dev)) + return 0; + + ret = dma_get_sgtable(dev, &sgt, is->memory.vaddr, + is->memory.alloc_addr, FIMC_IS_CPU_MEM_SIZE); + if (ret) + return ret; + + ret = iommu_map_sgtable(iommu_get_domain_for_dev(dev), + FIMC_IS_CPU_MEM_BASE, &sgt, + IOMMU_READ | IOMMU_WRITE); + sg_free_table(&sgt); + if (ret != FIMC_IS_CPU_MEM_SIZE) + return -EINVAL; + + is->memory.base = FIMC_IS_CPU_MEM_BASE; + return 0; +} + +static void fimc_iommu_unmap_cpu_memory(struct fimc_is *is) +{ + struct device *dev = &is->pdev->dev; + + iommu_unmap(iommu_get_domain_for_dev(dev), FIMC_IS_CPU_MEM_BASE, + FIMC_IS_CPU_MEM_SIZE); +} +#else +static inline int fimc_iommu_remap_cpu_memory(struct fimc_is *is) { return 0; } +static void fimc_iommu_unmap_cpu_memory(struct fimc_is *is) { } +#endif + /* Allocate working memory for the FIMC-IS CPU. */ static int fimc_is_alloc_cpu_memory(struct fimc_is *is) { struct device *dev = &is->pdev->dev; is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE, - &is->memory.addr, GFP_KERNEL); + &is->memory.alloc_addr, GFP_KERNEL); if (is->memory.vaddr == NULL) return -ENOMEM; + is->memory.base = is->memory.alloc_addr; is->memory.size = FIMC_IS_CPU_MEM_SIZE; - dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr); + if (fimc_iommu_remap_cpu_memory(is)) + goto err; + + dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.base); - if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) { + if (((u32)is->memory.base) & FIMC_IS_FW_ADDR_MASK) { dev_err(dev, "invalid firmware memory alignment: %#x\n", - (u32)is->memory.addr); - dma_free_coherent(dev, is->memory.size, is->memory.vaddr, - is->memory.addr); - return -EIO; + (u32)is->memory.base); + goto err; } is->is_p_region = (struct is_region *)(is->memory.vaddr + FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE); - is->is_dma_p_region = is->memory.addr + + is->is_dma_p_region = is->memory.base + FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE; is->is_shared_region = (struct is_share_region *)(is->memory.vaddr + FIMC_IS_SHARED_REGION_OFFSET); return 0; +err: + dma_free_coherent(dev, is->memory.size, is->memory.vaddr, + is->memory.alloc_addr); + return -EIO; } static void fimc_is_free_cpu_memory(struct fimc_is *is) @@ -370,8 +416,9 @@ static void fimc_is_free_cpu_memory(struct fimc_is *is) if (is->memory.vaddr == NULL) return; + fimc_iommu_unmap_cpu_memory(is); dma_free_coherent(dev, is->memory.size, is->memory.vaddr, - is->memory.addr); + is->memory.alloc_addr); } static void fimc_is_load_firmware(const struct firmware *fw, void *context) @@ -416,7 +463,8 @@ static void fimc_is_load_firmware(const struct firmware *fw, void *context) dev_info(dev, "loaded firmware: %s, rev. %s\n", is->fw.info, is->fw.version); - dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr); + dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, + &is->memory.base); is->is_shared_region->chip_id = 0xe4412; is->is_shared_region->chip_rev_no = 1; @@ -699,7 +747,7 @@ int fimc_is_hw_initialize(struct fimc_is *is) } pr_debug("shared region: %pad, parameter region: %pad\n", - &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET, + &is->memory.base + FIMC_IS_SHARED_REGION_OFFSET, &is->is_dma_p_region); is->setfile.sub_index = 0; diff --git a/drivers/media/platform/exynos4-is/fimc-is.h b/drivers/media/platform/exynos4-is/fimc-is.h index ce30b007bc55..d44729839310 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.h +++ b/drivers/media/platform/exynos4-is/fimc-is.h @@ -186,7 +186,9 @@ struct fimc_is_firmware { struct fimc_is_memory { /* DMA base address */ - dma_addr_t addr; + dma_addr_t base; + /* DMA address from allocator */ + dma_addr_t alloc_addr; /* virtual base address */ void *vaddr; /* total length */ From patchwork Fri Sep 18 14:48:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 313200 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1400211ilg; Fri, 18 Sep 2020 07:48:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+0OQKJdoHIjNen8CedFHwEP40F8d9XwlLP3ZCskNH/KPIbtHb9KGml+2JA8Ihw7X9Sty5 X-Received: by 2002:a50:cc9a:: with SMTP id q26mr40326792edi.64.1600440537726; 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Signed-off-by: Marek Szyprowski --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index eba2b9f040df..4e50c342b322 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -844,6 +844,7 @@ static int s5p_mfc_open(struct file *file) q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; q->drv_priv = &ctx->fh; q->lock = &dev->mfc_mutex; + q->dev = &dev->plat_dev->dev; if (vdev == dev->vfd_dec) { q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); @@ -871,6 +872,7 @@ static int s5p_mfc_open(struct file *file) q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; q->drv_priv = &ctx->fh; q->lock = &dev->mfc_mutex; + q->dev = &dev->plat_dev->dev; if (vdev == dev->vfd_dec) { q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); From patchwork Fri Sep 18 14:48:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 257176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6935C43469 for ; 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Fri, 18 Sep 2020 14:48:54 +0000 (GMT) X-AuditID: cbfec7f4-65dff7000000176d-57-5f64c8d63011 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id F9.2E.06314.6D8C46F5; Fri, 18 Sep 2020 15:48:54 +0100 (BST) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20200918144853eusmtip111e745941de67270c021f9ae5210ac18~16C_UYDIz1497714977eusmtip1i; Fri, 18 Sep 2020 14:48:53 +0000 (GMT) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Robin Murphy , Bartlomiej Zolnierkiewicz , Mauro Carvalho Chehab , Tomasz Figa Subject: [PATCH v2 4/4] media: platform: s5p-mfc: add support for generic DMA-IOMMU glue code Date: Fri, 18 Sep 2020 16:48:33 +0200 Message-Id: <20200918144833.14618-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918144833.14618-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjleLIzCtJLcpLzFFi42LZduznOd1rJ1LiDRb2GltsnLGe1eL8+Q3s Fj0btrJazDi/j8li7ZG77BbLNv1hsjj44QmrRfvTl8wWn1v/sTlweqyZt4bRY3bDRRaPTas6 2Tz6tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoEro/fAQuaC6XIV006eZW5gnCfZxcjJISFgIvFn 8y82EFtIYAWjxJM9yl2MXED2F0aJ183T2SCcz4wSlxbvZ4TpOL5vIhNEYjmjxOeNs9nhWg5t +8QKUsUmYCjR9bYLbK6IgJPEwll/wYqYBTYxSex684EJJCEsEC/x8fdsFhCbRUBVoufRLHYQ m1fAVuLS86csEOvkJVZvOMDcxcjBwSlgJ3G1yRJkjoRAM7vElBnfWCFqXCQObOplgrCFJV4d 38IOYctInJ7cwwLVwCjx8Nxadginh1HictMMqIesJe6cAwUBB9B5mhLrd+lDhB0lfi5fBLZY QoBP4sZbQZAwM5A5adt0qDCvREebEES1msSs4+vg1h68cIkZwvaQmPPhByskgCYySsyec5p9 AqP8LIRlCxgZVzGKp5YW56anFhvlpZbrFSfmFpfmpesl5+duYgSmjtP/jn/ZwbjrT9IhRgEO RiUe3hfzUuKFWBPLiitzDzFKcDArifA6nT0dJ8SbklhZlVqUH19UmpNafIhRmoNFSZzXeNHL WCGB9MSS1OzU1ILUIpgsEwenVAOjpOKuXwvda7fGcM40qn5W2+XX8fewyXaRnIIXXV/fl0y2 DtKzzqlS3+dge3haPZdTc32/YcvrefMuv/ezyftsZ7XPQa3DPWV1glpyttmVdU0TuaI6V1n/ upMgmLtHRqs2yuVWglecuIfphyN3Jj5ZZ7/8ikTzvpqJMzNi+O+fURfdWWl4epcSS3FGoqEW c1FxIgBmwhzKGQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsVy+t/xu7rXTqTEG+z/xmyxccZ6Vovz5zew W/Rs2MpqMeP8PiaLtUfuslss2/SHyeLghyesFu1PXzJbfG79x+bA6bFm3hpGj9kNF1k8Nq3q ZPPo27KK0ePzJrkA1ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TU nMyy1CJ9uwS9jN4DC5kLpstVTDt5lrmBcZ5kFyMnh4SAicTxfROZuhi5OIQEljJKXNl+iBki ISNxcloDK4QtLPHnWhcbRNEnRomlz66xgCTYBAwlut6CJDg5RARcJPbvecoMUsQssI1J4tfW RUwgCWGBWIn+F2vBGlgEVCV6Hs1iB7F5BWwlLj1/ygKxQV5i9YYDQM0cHJwCdhJXmyxBwkJA Ja1LlrBNYORbwMiwilEktbQ4Nz232FCvODG3uDQvXS85P3cTIzCQtx37uXkH46WNwYcYBTgY lXh4X8xLiRdiTSwrrsw9xCjBwawkwut09nScEG9KYmVValF+fFFpTmrxIUZToJsmMkuJJucD oyyvJN7Q1NDcwtLQ3Njc2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVANjyXax2bwtn0s9 Vk75t//UhaMHb8+WlJ/NI/Bgu8f/i2alCg/WO2x+e0J5ktW8M+45zszGxp0OtXOZDzuzLzMu v2n0Qvav4RTvmCUJ4hkXg87auYR6JG36sK7v3SGZpbFmIle8Jla9Ff97xICtdY7CqnfXClln XX/zbJ6ZlkwV+5m/jXYb94kHK7EUZyQaajEXFScCAIlTWCV6AgAA X-CMS-MailID: 20200918144854eucas1p2ad33e726e1e3caa04ab4145f86b05486 X-Msg-Generator: CA X-RootMTR: 20200918144854eucas1p2ad33e726e1e3caa04ab4145f86b05486 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200918144854eucas1p2ad33e726e1e3caa04ab4145f86b05486 References: <20200918144833.14618-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org S5P-MFC driver relies on the way the ARM DMA-IOMMU glue code works: the IOVA allocator uses first-fit algorithm, so the first allocated buffer is at 0x0 DMA/IOVA address. This is not true for the generic IOMMU-DMA glue code that will be used for ARM architecture soon, so add the needed code to support it too. Signed-off-by: Marek Szyprowski --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 35 ++++++++++++++++++- .../media/platform/s5p-mfc/s5p_mfc_common.h | 2 ++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 4e50c342b322..63cbf1d29c43 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1201,6 +1202,10 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) if (!mfc_dev->mem_bitmap) return -ENOMEM; + /* MFC v5 can access memory only via the 128M window */ + if (exynos_is_iommu_available(dev) && !IS_MFCV6_PLUS(mfc_dev)) + dma_set_mask_and_coherent(dev, SZ_128M - 1); + mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size, &mfc_dev->mem_base, GFP_KERNEL); if (!mfc_dev->mem_virt) { @@ -1218,13 +1223,37 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) * as used (to keep required base alignment) and adjust base address */ if (mfc_dev->mem_base == (dma_addr_t)0) { - unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER; + unsigned int offset = MFC_MIN_VALID_BASE; bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT); mfc_dev->dma_base[BANK_L_CTX] += offset; mfc_dev->dma_base[BANK_R_CTX] += offset; } + /* + * Generic DMA-IOMMU use last-fit memory allocation algorithm, so + * remap the firmware to the lowest supported address for MFC v5 to + * let HW properly address buffers as an offset from the firmware. + */ + if (IS_ENABLED(CONFIG_IOMMU_DMA) && exynos_is_iommu_available(dev) && + !IS_MFCV6_PLUS(mfc_dev)) { + struct sg_table sgt; + int size; + + if (dma_get_sgtable(dev, &sgt, mfc_dev->mem_virt, + mfc_dev->mem_base, mfc_dev->mem_size) != 0) + return -ENOMEM; + size = iommu_map_sgtable(iommu_get_domain_for_dev(dev), + MFC_MIN_VALID_BASE, &sgt, + IOMMU_READ | IOMMU_WRITE); + sg_free_table(&sgt); + if (size != mem_size) + return -ENOMEM; + + mfc_dev->dma_base[BANK_L_CTX] = MFC_MIN_VALID_BASE; + mfc_dev->dma_base[BANK_R_CTX] = MFC_MIN_VALID_BASE; + } + /* Firmware allocation cannot fail in this case */ s5p_mfc_alloc_firmware(mfc_dev); @@ -1241,6 +1270,10 @@ static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev) { struct device *dev = &mfc_dev->plat_dev->dev; + if (IS_ENABLED(CONFIG_IOMMU_DMA) && exynos_is_iommu_available(dev) && + !IS_MFCV6_PLUS(mfc_dev)) + iommu_unmap(iommu_get_domain_for_dev(dev), MFC_MIN_VALID_BASE, + mfc_dev->mem_size); dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt, mfc_dev->mem_base); kfree(mfc_dev->mem_bitmap); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index 96d1ecd1521b..f28c943b8426 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -37,6 +37,8 @@ #define MFC_BANK2_ALIGN_ORDER 13 #define MFC_BASE_ALIGN_ORDER 17 +#define MFC_MIN_VALID_BASE (1 << MFC_BASE_ALIGN_ORDER) + #define MFC_FW_MAX_VERSIONS 2 #include