From patchwork Mon Oct 12 20:59:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA438C433DF for ; Mon, 12 Oct 2020 20:59:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7969F21D7F for ; Mon, 12 Oct 2020 20:59:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731627AbgJLU64 (ORCPT ); Mon, 12 Oct 2020 16:58:56 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:49772 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729460AbgJLU64 (ORCPT ); Mon, 12 Oct 2020 16:58:56 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 6294E1F44C2A From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/18] media: hantro: document all int reg bits up to vc8000 Date: Mon, 12 Oct 2020 23:59:40 +0300 Message-Id: <20201012205957.889185-2-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org These do not all strictly belong to the g1 core and even the majority of previously documented bits were not used (yet) by the driver irq handlers, but it's still very useful to have an overview of all IRQs, especially since starting with core versions vc8000 and later the irq bits previously used by G1 and G2 have been merged at the same address. Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/hantro_g1_regs.h | 39 +++++++++++++------ 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h b/drivers/staging/media/hantro/hantro_g1_regs.h index c1756e3d5391..80ff297f6f68 100644 --- a/drivers/staging/media/hantro/hantro_g1_regs.h +++ b/drivers/staging/media/hantro/hantro_g1_regs.h @@ -13,17 +13,34 @@ /* Decoder registers. */ #define G1_REG_INTERRUPT 0x004 -#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) -#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) -#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) -#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) -#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) -#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) -#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) -#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) -#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) -#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) -#define G1_REG_INTERRUPT_DEC_E BIT(0) +/* Interrupt bits. Some are present in: + * - all core versions (">= g1") + * - g1, missing in g2, but added back starting with vc8000d ("not in g2") + * - vc8000d and later (">= vc8000d") + */ +#define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT BIT(23) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LINE_CNT_INT BIT(22) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_EXT_TIMEOUT_INT BIT(21) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_NO_SLICE_INT BIT(20) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_LAST_SLICE_INT BIT(19) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15) /* not in g2 */ +#define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_ABORT_INT BIT(11) /* >= g2 */ +#define G1_REG_INTERRUPT_DEC_IRQ BIT(8) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TILE_INT_E BIT(7) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_SELF_RESET_DIS BIT(6) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_ABORT_E BIT(5) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) /* >= g1 */ +#define G1_REG_INTERRUPT_DEC_TIMEOUT_SOURCE BIT(3) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >= vc8000d */ +#define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */ #define G1_REG_CONFIG 0x008 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23) From patchwork Mon Oct 12 20:59:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A1BDC433E7 for ; Mon, 12 Oct 2020 20:59:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBAD3218AC for ; Mon, 12 Oct 2020 20:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731783AbgJLU7G (ORCPT ); Mon, 12 Oct 2020 16:59:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731618AbgJLU64 (ORCPT ); Mon, 12 Oct 2020 16:58:56 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45C62C0613D0; Mon, 12 Oct 2020 13:58:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 083EE1F44C2B From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/18] media: hantro: make consistent use of decimal register notation Date: Mon, 12 Oct 2020 23:59:41 +0300 Message-Id: <20201012205957.889185-3-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This header used a combination of direct hex offsets and decimal register notation - via the G1_SWREG() macro - which is annoying when comparing with the ref manuals which always use the equivalent of G1_SWREG(), so convert the entire file to G1_SWREG() notation. Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/hantro_g1_regs.h | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_regs.h b/drivers/staging/media/hantro/hantro_g1_regs.h index 80ff297f6f68..073b64cbe295 100644 --- a/drivers/staging/media/hantro/hantro_g1_regs.h +++ b/drivers/staging/media/hantro/hantro_g1_regs.h @@ -9,10 +9,10 @@ #ifndef HANTRO_G1_REGS_H_ #define HANTRO_G1_REGS_H_ -#define G1_SWREG(nr) ((nr) * 4) +#define G1_SWREG(nr) ((nr) * 4) /* Decoder registers. */ -#define G1_REG_INTERRUPT 0x004 +#define G1_REG_INTERRUPT G1_SWREG(1) /* Interrupt bits. Some are present in: * - all core versions (">= g1") * - g1, missing in g2, but added back starting with vc8000d ("not in g2") @@ -41,7 +41,7 @@ #define G1_REG_INTERRUPT_DEC_BUS_INT_DIS BIT(2) /* >= vc8000d */ #define G1_REG_INTERRUPT_DEC_STRM_CORRUPTED BIT(1) /* >= vc8000d */ #define G1_REG_INTERRUPT_DEC_E BIT(0) /* >= g1 */ -#define G1_REG_CONFIG 0x008 +#define G1_REG_CONFIG G1_SWREG(2) #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23) #define G1_REG_CONFIG_DEC_STRSWAP32_E BIT(22) @@ -60,7 +60,7 @@ #define G1_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6) #define G1_REG_CONFIG_DEC_SCMD_DIS BIT(5) #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) -#define G1_REG_DEC_CTRL0 0x00c +#define G1_REG_DEC_CTRL0 G1_SWREG(3) #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) #define G1_REG_DEC_CTRL0_RLC_MODE_E BIT(27) #define G1_REG_DEC_CTRL0_SKIP_MODE BIT(26) @@ -85,7 +85,7 @@ #define G1_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9) #define G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8) #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0) -#define G1_REG_DEC_CTRL1 0x010 +#define G1_REG_DEC_CTRL1 G1_SWREG(4) #define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) #define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) @@ -96,7 +96,7 @@ #define G1_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) #define G1_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) #define G1_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0) -#define G1_REG_DEC_CTRL2 0x014 +#define G1_REG_DEC_CTRL2 G1_SWREG(5) #define G1_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) #define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25) #define G1_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24) @@ -139,13 +139,13 @@ #define G1_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) #define G1_REG_DEC_CTRL2_ALPHA_OFFSET(x) (((x) & 0x1f) << 5) #define G1_REG_DEC_CTRL2_BETA_OFFSET(x) (((x) & 0x1f) << 0) -#define G1_REG_DEC_CTRL3 0x018 +#define G1_REG_DEC_CTRL3 G1_SWREG(6) #define G1_REG_DEC_CTRL3_START_CODE_E BIT(31) #define G1_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) #define G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24) #define G1_REG_DEC_CTRL3_STREAM_LEN_EXT(x) (((x) & 0xff) << 24) #define G1_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) -#define G1_REG_DEC_CTRL4 0x01c +#define G1_REG_DEC_CTRL4 G1_SWREG(7) #define G1_REG_DEC_CTRL4_CABAC_E BIT(31) #define G1_REG_DEC_CTRL4_BLACKWHITE_E BIT(30) #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29) @@ -182,7 +182,7 @@ #define G1_REG_DEC_CTRL4_INIT_DC_MATCH0(x) (((x) & 0x7) << 9) #define G1_REG_DEC_CTRL4_INIT_DC_MATCH1(x) (((x) & 0x7) << 6) #define G1_REG_DEC_CTRL4_VP7_VERSION BIT(5) -#define G1_REG_DEC_CTRL5 0x020 +#define G1_REG_DEC_CTRL5 G1_SWREG(8) #define G1_REG_DEC_CTRL5_CONST_INTRA_E BIT(31) #define G1_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30) #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29) @@ -206,7 +206,7 @@ #define G1_REG_DEC_CTRL5_RV_BWD_SCALE(x) (((x) & 0x3fff) << 0) #define G1_REG_DEC_CTRL5_INIT_DC_COMP0(x) (((x) & 0xffff) << 16) #define G1_REG_DEC_CTRL5_INIT_DC_COMP1(x) (((x) & 0xffff) << 0) -#define G1_REG_DEC_CTRL6 0x024 +#define G1_REG_DEC_CTRL6 G1_SWREG(9) #define G1_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) #define G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) #define G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) @@ -217,7 +217,7 @@ #define G1_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) #define G1_REG_DEC_CTRL6_PIC_SLICE_AM(x) (((x) & 0x1fff) << 0) #define G1_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) -#define G1_REG_FWD_PIC(i) (0x028 + ((i) * 0x4)) +#define G1_REG_FWD_PIC(i) (G1_SWREG(10) + ((i) * 0x4)) #define G1_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) #define G1_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) #define G1_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) @@ -230,7 +230,7 @@ #define G1_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) #define G1_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) #define G1_REG_FWD_PIC1_SEGMENT_E BIT(0) -#define G1_REG_DEC_CTRL7 0x02c +#define G1_REG_DEC_CTRL7 G1_SWREG(11) #define G1_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25) #define G1_REG_DEC_CTRL7_PINIT_RLIST_F14(x) (((x) & 0x1f) << 20) #define G1_REG_DEC_CTRL7_PINIT_RLIST_F13(x) (((x) & 0x1f) << 15) @@ -245,12 +245,12 @@ #define G1_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) #define G1_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) #define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) -#define G1_REG_ADDR_STR 0x030 -#define G1_REG_ADDR_DST 0x034 -#define G1_REG_ADDR_REF(i) (0x038 + ((i) * 0x4)) +#define G1_REG_ADDR_STR G1_SWREG(12) +#define G1_REG_ADDR_DST G1_SWREG(13) +#define G1_REG_ADDR_REF(i) (G1_SWREG(14) + ((i) * 0x4)) #define G1_REG_ADDR_REF_FIELD_E BIT(1) #define G1_REG_ADDR_REF_TOPC_E BIT(0) -#define G1_REG_REF_PIC(i) (0x078 + ((i) * 0x4)) +#define G1_REG_REF_PIC(i) (G1_SWREG(30) + ((i) * 0x4)) #define G1_REG_REF_PIC_FILT_TYPE_E BIT(31) #define G1_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) #define G1_REG_REF_PIC_MB_ADJ_0(x) (((x) & 0x7f) << 21) @@ -267,11 +267,11 @@ #define G1_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) #define G1_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) #define G1_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) -#define G1_REG_LT_REF 0x098 -#define G1_REG_VALID_REF 0x09c -#define G1_REG_ADDR_QTABLE 0x0a0 -#define G1_REG_ADDR_DIR_MV 0x0a4 -#define G1_REG_BD_REF_PIC(i) (0x0a8 + ((i) * 0x4)) +#define G1_REG_LT_REF G1_SWREG(38) +#define G1_REG_VALID_REF G1_SWREG(39) +#define G1_REG_ADDR_QTABLE G1_SWREG(40) +#define G1_REG_ADDR_DIR_MV G1_SWREG(41) +#define G1_REG_BD_REF_PIC(i) (G1_SWREG(42) + ((i) * 0x4)) #define G1_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25) #define G1_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 20) #define G1_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 15) @@ -288,7 +288,7 @@ #define G1_REG_BD_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) #define G1_REG_BD_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) #define G1_REG_BD_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) -#define G1_REG_BD_P_REF_PIC 0x0bc +#define G1_REG_BD_P_REF_PIC G1_SWREG(47) #define G1_REG_BD_P_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25) #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 20) @@ -296,21 +296,21 @@ #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 10) #define G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 5) #define G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 0) -#define G1_REG_ERR_CONC 0x0c0 +#define G1_REG_ERR_CONC G1_SWREG(48) #define G1_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 23) #define G1_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 15) -#define G1_REG_PRED_FLT 0x0c4 +#define G1_REG_PRED_FLT G1_SWREG(49) #define G1_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) #define G1_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) #define G1_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) -#define G1_REG_REF_BUF_CTRL 0x0cc +#define G1_REG_REF_BUF_CTRL G1_SWREG(51) #define G1_REG_REF_BUF_CTRL_REFBU_E BIT(31) #define G1_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19) #define G1_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14) #define G1_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13) #define G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12) #define G1_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x) (((x) & 0x1ff) << 0) -#define G1_REG_REF_BUF_CTRL2 0x0dc +#define G1_REG_REF_BUF_CTRL2 G1_SWREG(55) #define G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31) #define G1_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19) #define G1_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 14) From patchwork Mon Oct 12 20:59:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C24AFC433E7 for ; Mon, 12 Oct 2020 21:00:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96CE220797 for ; Mon, 12 Oct 2020 21:00:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731995AbgJLVAD (ORCPT ); Mon, 12 Oct 2020 17:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729460AbgJLU66 (ORCPT ); Mon, 12 Oct 2020 16:58:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF2DDC0613D0; Mon, 12 Oct 2020 13:58:57 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 693811F44C37 From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/18] media: hantro: imx8mq: simplify ctrlblk reset logic Date: Mon, 12 Oct 2020 23:59:45 +0300 Message-Id: <20201012205957.889185-7-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The G1 and G2 cores on imx8mq share a common "control block" used to reset and enable the core clocks as well as enable functioning via ctrl FUSE registers (these are not the FUSEs on the VPU cores, they are just used to enable/disable the cores and allow the real VPU FUSE regs to become available). The problem is that, while the cores can be operated independently from one another (different config reg mem regions, separate IRQs), they can not be reset or powered down independently as the current code implies. This has been a source for many bugs and frustration when trying to enable G2 which this driver does not support yet. So we simplify the ctrlblk reset logic to always reset both cores, exactly like the vendor linux-imx provided driver "hantrodec" does for this SoC. Going forward, this simplified code should be moved in the future to its own reset controller driver as the reset framework also supports shared reset resources so the runtime PM logic can disable both cores when none of them are in use (this is not done yet because only G1 is supported in the driver so there is no need to account for G2). Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/hantro.h | 2 - drivers/staging/media/hantro/imx8m_vpu_hw.c | 74 +++++++-------------- 2 files changed, 24 insertions(+), 52 deletions(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index bb442eb1974e..2dd4362d4080 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -167,7 +167,6 @@ hantro_vdev_to_func(struct video_device *vdev) * @reg_bases: Mapped addresses of VPU registers. * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. - * @ctrl_base: Mapped address of VPU control block. * @vpu_mutex: Mutex to synchronize V4L2 calls. * @irqlock: Spinlock to synchronize access to data structures * shared with interrupt handlers. @@ -187,7 +186,6 @@ struct hantro_dev { void __iomem **reg_bases; void __iomem *enc_base; void __iomem *dec_base; - void __iomem *ctrl_base; struct mutex vpu_mutex; /* video_device lock */ spinlock_t irqlock; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index c222de075ef4..b2a401a33992 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -24,34 +24,13 @@ #define CTRL_G1_PP_FUSE 0x0c #define CTRL_G2_DEC_FUSE 0x10 -static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) -{ - u32 val; - - /* Assert */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val &= ~reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); - - udelay(2); - - /* Release */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val |= reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); -} - -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) -{ - u32 val; - - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); - val |= clock_bits; - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); -} - -static int imx8mq_runtime_resume(struct hantro_dev *vpu) +/* + * Due to a HW limitation, both G1 and G2 VPU cores on imx8mq need to be reset + * together via their unified ctrl block. + */ +static int imx8mq_ctrlblk_reset(struct hantro_dev *vpu) { + void __iomem *ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; int ret; ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); @@ -60,13 +39,18 @@ static int imx8mq_runtime_resume(struct hantro_dev *vpu) return ret; } - imx8m_soft_reset(vpu, RESET_G1 | RESET_G2); - imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); + /* reset HW and ungate clocks via ctrl block */ + writel(RESET_G1 | RESET_G2, ctrl_base + CTRL_SOFT_RESET); + writel(CLOCK_G1 | CLOCK_G2, ctrl_base + CTRL_CLOCK_ENABLE); - /* Set values of the fuse registers */ - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); + /* + * enable fuse functionalities for each core, these are not real fuses + * but registers which enable the cores and makes accesible their real + * read-only fuse registers describing supported features. + */ + writel(0xffffffff, ctrl_base + CTRL_G1_DEC_FUSE); + writel(0xffffffff, ctrl_base + CTRL_G1_PP_FUSE); + writel(0xffffffff, ctrl_base + CTRL_G2_DEC_FUSE); clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); @@ -148,19 +132,9 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) +static void imx8m_vpu_reset(struct hantro_ctx *ctx) { - vpu->dec_base = vpu->reg_bases[0]; - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; - - return 0; -} - -static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G1); + imx8mq_ctrlblk_reset(ctx->dev); } /* @@ -170,19 +144,19 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { [HANTRO_MODE_MPEG2_DEC] = { .run = hantro_g1_mpeg2_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8m_vpu_reset, .init = hantro_mpeg2_dec_init, .exit = hantro_mpeg2_dec_exit, }, [HANTRO_MODE_VP8_DEC] = { .run = hantro_g1_vp8_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8m_vpu_reset, .init = hantro_vp8_dec_init, .exit = hantro_vp8_dec_exit, }, [HANTRO_MODE_H264_DEC] = { .run = hantro_g1_h264_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8m_vpu_reset, .init = hantro_h264_dec_init, .exit = hantro_h264_dec_exit, }, @@ -209,8 +183,8 @@ const struct hantro_variant imx8mq_vpu_variant = { .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | HANTRO_H264_DECODER, .codec_ops = imx8mq_vpu_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, + .init = imx8mq_ctrlblk_reset, + .runtime_resume = imx8mq_ctrlblk_reset, .irqs = imx8mq_irqs, .num_irqs = ARRAY_SIZE(imx8mq_irqs), .clk_names = imx8mq_clk_names, From patchwork Mon Oct 12 20:59:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BCA1C433E7 for ; Mon, 12 Oct 2020 21:00:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 044F820797 for ; Mon, 12 Oct 2020 21:00:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732012AbgJLVAE (ORCPT ); Mon, 12 Oct 2020 17:00:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731693AbgJLU66 (ORCPT ); Mon, 12 Oct 2020 16:58:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85667C0613D2; Mon, 12 Oct 2020 13:58:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 046F91F44C3A From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/18] regmap: mmio: add config option to allow relaxed MMIO accesses Date: Mon, 12 Oct 2020 23:59:46 +0300 Message-Id: <20201012205957.889185-8-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On some platforms (eg armv7 due to the CONFIG_ARM_DMA_MEM_BUFFERABLE) MMIO R/W operations always add memory barriers which can increase load, decrease battery life or in general reduce performance unnecessarily on devices which access a lot of configuration registers and where ordering does not matter (eg. media accelerators like the Verisilicon / Hantro video decoders). Drivers used to call the relaxed MMIO variants directly but since they are now accessing the MMIO registers via regmaps (to compensate for for different VPU HW reg layouts via regmap fields), there is a need for a relaxed API / config to preserve their existing behaviour. Signed-off-by: Adrian Ratiu --- drivers/base/regmap/regmap-mmio.c | 34 +++++++++++++++++++++++++++---- include/linux/regmap.h | 5 +++++ 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c index af967d8f975e..21193ef2a923 100644 --- a/drivers/base/regmap/regmap-mmio.c +++ b/drivers/base/regmap/regmap-mmio.c @@ -16,6 +16,7 @@ struct regmap_mmio_context { void __iomem *regs; unsigned val_bytes; + bool relaxed_mmio; bool attached_clk; struct clk *clk; @@ -72,14 +73,20 @@ static void regmap_mmio_write8(struct regmap_mmio_context *ctx, unsigned int reg, unsigned int val) { - writeb(val, ctx->regs + reg); + if (ctx->relaxed_mmio) + writeb_relaxed(val, ctx->regs + reg); + else + writeb(val, ctx->regs + reg); } static void regmap_mmio_write16le(struct regmap_mmio_context *ctx, unsigned int reg, unsigned int val) { - writew(val, ctx->regs + reg); + if (ctx->relaxed_mmio) + writew_relaxed(val, ctx->regs + reg); + else + writew(val, ctx->regs + reg); } static void regmap_mmio_write16be(struct regmap_mmio_context *ctx, @@ -93,7 +100,10 @@ static void regmap_mmio_write32le(struct regmap_mmio_context *ctx, unsigned int reg, unsigned int val) { - writel(val, ctx->regs + reg); + if (ctx->relaxed_mmio) + writel_relaxed(val, ctx->regs + reg); + else + writel(val, ctx->regs + reg); } static void regmap_mmio_write32be(struct regmap_mmio_context *ctx, @@ -108,7 +118,10 @@ static void regmap_mmio_write64le(struct regmap_mmio_context *ctx, unsigned int reg, unsigned int val) { - writeq(val, ctx->regs + reg); + if (ctx->relaxed_mmio) + writeq_relaxed(val, ctx->regs + reg); + else + writeq(val, ctx->regs + reg); } #endif @@ -134,12 +147,18 @@ static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val) static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx, unsigned int reg) { + if (ctx->relaxed_mmio) + return readb_relaxed(ctx->regs + reg); + return readb(ctx->regs + reg); } static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx, unsigned int reg) { + if (ctx->relaxed_mmio) + return readw_relaxed(ctx->regs + reg); + return readw(ctx->regs + reg); } @@ -152,6 +171,9 @@ static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx, static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx, unsigned int reg) { + if (ctx->relaxed_mmio) + return readl_relaxed(ctx->regs + reg); + return readl(ctx->regs + reg); } @@ -165,6 +187,9 @@ static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx, static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx, unsigned int reg) { + if (ctx->relaxed_mmio) + return readq_relaxed(ctx->regs + reg); + return readq(ctx->regs + reg); } #endif @@ -237,6 +262,7 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev, ctx->regs = regs; ctx->val_bytes = config->val_bits / 8; + ctx->relaxed_mmio = config->use_relaxed_mmio; ctx->clk = ERR_PTR(-ENODEV); switch (regmap_get_val_endian(dev, ®map_mmio, config)) { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index e7834d98207f..126fe700d1d8 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -315,6 +315,10 @@ typedef void (*regmap_unlock)(void *); * masks are used. * @zero_flag_mask: If set, read_flag_mask and write_flag_mask are used even * if they are both empty. + * @use_relaxed_mmio: If set, MMIO R/W operations will not use memory barriers. + * This can avoid load on devices which don't require strict + * orderings, but drivers should carefully add any explicit + * memory barriers when they may require them. * @use_single_read: If set, converts the bulk read operation into a series of * single read operations. This is useful for a device that * does not support bulk read. @@ -388,6 +392,7 @@ struct regmap_config { bool use_single_read; bool use_single_write; + bool use_relaxed_mmio; bool can_multi_write; enum regmap_endian reg_format_endian; From patchwork Mon Oct 12 20:59:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 974C8C433DF for ; Mon, 12 Oct 2020 20:59:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F3BD20790 for ; Mon, 12 Oct 2020 20:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731870AbgJLU7S (ORCPT ); Mon, 12 Oct 2020 16:59:18 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:49884 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731696AbgJLU7A (ORCPT ); Mon, 12 Oct 2020 16:59:00 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 2C9261F44C44 From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/18] media: hantro: default regmap to relaxed MMIO Date: Mon, 12 Oct 2020 23:59:48 +0300 Message-Id: <20201012205957.889185-10-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This is done to match the pre-regmap membarrier behaviour, ensuring default regmap_write calls in _relaxed() are indeed relaxed while the non-relaxed versions include an explicit mem-barrier call. Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/hantro.h | 4 ++++ drivers/staging/media/hantro/hantro_regmap.c | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index c5425cd5ac84..5b7fbdc3779d 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -346,6 +346,7 @@ static inline void vepu_write_relaxed(struct hantro_dev *vpu, static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) { vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); + wmb(); /* flush encoder previous relaxed writes */ regmap_write(vpu->regs_enc, reg, val); } @@ -354,6 +355,7 @@ static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) u32 val; regmap_read(vpu->regs_enc, reg, &val); + rmb(); /* read encoder swreg data in order */ vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); return val; @@ -369,6 +371,7 @@ static inline void vdpu_write_relaxed(struct hantro_dev *vpu, static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) { vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); + wmb();/* flush decoder previous relaxed writes */ regmap_write(vpu->regs_dec, reg, val); } @@ -377,6 +380,7 @@ static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) u32 val; regmap_read(vpu->regs_dec, reg, &val); + rmb(); /* read decoder swreg data in order */ vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); return val; diff --git a/drivers/staging/media/hantro/hantro_regmap.c b/drivers/staging/media/hantro/hantro_regmap.c index 890e443688e2..2fc409cbd797 100644 --- a/drivers/staging/media/hantro/hantro_regmap.c +++ b/drivers/staging/media/hantro/hantro_regmap.c @@ -21,6 +21,7 @@ struct regmap_config hantro_regmap_dec = { .reg_stride = 4, /* all hantro accesses are sequential, even with respect to irq ctx */ .disable_locking = true, + .use_relaxed_mmio = true, .name = "hantro_regmap_dec", }; From patchwork Mon Oct 12 20:59:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCE4AC433E7 for ; Mon, 12 Oct 2020 20:59:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9457C20797 for ; Mon, 12 Oct 2020 20:59:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731862AbgJLU7R (ORCPT ); Mon, 12 Oct 2020 16:59:17 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:49908 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731706AbgJLU7B (ORCPT ); Mon, 12 Oct 2020 16:59:01 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id BE02C1F44C2F From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/18] media: hantro: convert G1 h264 decoder to regmap fields Date: Mon, 12 Oct 2020 23:59:49 +0300 Message-Id: <20201012205957.889185-11-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Populate the regmap field API for G1 h264 decoding and convert the G1 h264 decoder source to use the new API. This is done because we will add support for the newer VC8000D core which will configure the regmap API fields differently to match its own hwreg layout. Signed-off-by: Adrian Ratiu --- .../staging/media/hantro/hantro_g1_h264_dec.c | 71 ++++++++++------- drivers/staging/media/hantro/hantro_regmap.c | 79 ++++++++++++++++++- drivers/staging/media/hantro/hantro_regmap.h | 26 +++++- 3 files changed, 145 insertions(+), 31 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index 845bef73d218..8592dfabbc5e 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -18,6 +18,9 @@ #include "hantro_g1_regs.h" #include "hantro_hw.h" #include "hantro_v4l2.h" +#include "hantro_regmap.h" + +extern struct regmap_config hantro_regmap_dec; static void set_params(struct hantro_ctx *ctx) { @@ -27,10 +30,15 @@ static void set_params(struct hantro_ctx *ctx) const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); struct hantro_dev *vpu = ctx->dev; + struct hantro_regmap_fields_dec *fields = vpu->reg_fields_dec; + u32 width = MB_WIDTH(ctx->src_fmt.width); + u32 height = MB_HEIGHT(ctx->src_fmt.height); u32 reg; + regmap_field_write(fields->dec_axi_wr_id, 0x0); + /* Decoder control register 0. */ - reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0); + reg = 0; if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E; if (sps->profile_idc > 66) { @@ -50,10 +58,11 @@ static void set_params(struct hantro_ctx *ctx) vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); /* Decoder control register 1. */ - reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) | - G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) | - G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames); - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); + regmap_field_write(fields->dec_pic_width, width); + regmap_field_write(fields->dec_pic_height, height); + + regmap_field_write(fields->dec_num_ref_frames, + sps->max_num_ref_frames); /* Decoder control register 2. */ reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | @@ -66,10 +75,11 @@ static void set_params(struct hantro_ctx *ctx) vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); /* Decoder control register 3. */ - reg = G1_REG_DEC_CTRL3_START_CODE_E | - G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | - G1_REG_DEC_CTRL3_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); + regmap_field_write(fields->dec_start_code_e, 1); + regmap_field_write(fields->dec_init_qp, + pps->pic_init_qp_minus26 + 26); + regmap_field_write(fields->dec_stream_len, + vb2_get_plane_payload(&src_buf->vb2_buf, 0)); /* Decoder control register 4. */ reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | @@ -121,8 +131,7 @@ static void set_params(struct hantro_ctx *ctx) vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL); /* Reference picture buffer control register 2. */ - vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8), - G1_REG_REF_BUF_CTRL2); + regmap_field_write(fields->dec_apf_threshold, 8); } static void set_ref(struct hantro_ctx *ctx) @@ -221,7 +230,6 @@ static void set_ref(struct hantro_ctx *ctx) /* Set up addresses of DPB buffers. */ for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i); - vdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i)); } } @@ -231,6 +239,7 @@ static void set_buffers(struct hantro_ctx *ctx) const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; struct vb2_v4l2_buffer *src_buf, *dst_buf; struct hantro_dev *vpu = ctx->dev; + struct hantro_regmap_fields_dec *fields = vpu->reg_fields_dec; dma_addr_t src_dma, dst_dma; size_t offset = 0; @@ -239,14 +248,14 @@ static void set_buffers(struct hantro_ctx *ctx) /* Source (stream) buffer. */ src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); + regmap_field_write(fields->dec_addr_str, src_dma); /* Destination (decoded frame) buffer. */ dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); /* Adjust dma addr to start at second line for bottom field */ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) offset = ALIGN(ctx->src_fmt.width, MB_DIM); - vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DST); + regmap_field_write(fields->dec_addr_dst, dst_dma + offset); /* Higher profiles require DMV buffer appended to reference frames. */ if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) { @@ -266,16 +275,18 @@ static void set_buffers(struct hantro_ctx *ctx) if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) offset += 32 * MB_WIDTH(ctx->src_fmt.width) * MB_HEIGHT(ctx->src_fmt.height); - vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV); + regmap_field_write(fields->dec_addr_dir_mv, dst_dma + offset); } /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ - vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE); + regmap_field_write(fields->dec_addr_qtable, ctx->h264_dec.priv.dma); } void hantro_g1_h264_dec_run(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; + struct hantro_regmap_fields_dec *fields = vpu->reg_fields_dec; + int reg; /* Prepare the H264 decoder context. */ if (hantro_h264_dec_prepare_run(ctx)) @@ -288,17 +299,23 @@ void hantro_g1_h264_dec_run(struct hantro_ctx *ctx) hantro_end_prepare_run(ctx); + switch (vpu->core_hw_dec_rev) { + case HANTRO_G1_REV: + reg = G1_REG_CONFIG_DEC_TIMEOUT_E | + G1_REG_CONFIG_DEC_OUT_ENDIAN | + G1_REG_CONFIG_DEC_STRENDIAN_E | + G1_REG_CONFIG_DEC_OUTSWAP32_E | + G1_REG_CONFIG_DEC_INSWAP32_E | + G1_REG_CONFIG_DEC_STRSWAP32_E; + vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG); + break; + /* TODO: add VC8000 support */ + } + + regmap_field_write(fields->dec_clk_gate_e, 1); + regmap_field_write(fields->dec_max_burst, 16); + regmap_field_write(fields->dec_axi_rd_id, 16); + /* Start decoding! */ - vdpu_write_relaxed(vpu, - G1_REG_CONFIG_DEC_AXI_RD_ID(0xffu) | - G1_REG_CONFIG_DEC_TIMEOUT_E | - G1_REG_CONFIG_DEC_OUT_ENDIAN | - G1_REG_CONFIG_DEC_STRENDIAN_E | - G1_REG_CONFIG_DEC_MAX_BURST(16) | - G1_REG_CONFIG_DEC_OUTSWAP32_E | - G1_REG_CONFIG_DEC_INSWAP32_E | - G1_REG_CONFIG_DEC_STRSWAP32_E | - G1_REG_CONFIG_DEC_CLK_GATE_E, - G1_REG_CONFIG); vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); } diff --git a/drivers/staging/media/hantro/hantro_regmap.c b/drivers/staging/media/hantro/hantro_regmap.c index 2fc409cbd797..fbc39abedc7d 100644 --- a/drivers/staging/media/hantro/hantro_regmap.c +++ b/drivers/staging/media/hantro/hantro_regmap.c @@ -33,12 +33,54 @@ struct regmap_config hantro_regmap_enc = { .name = "hantro_regmap_enc", }; +struct hantro_field_dec { + struct reg_field cfg_dec_axi_rd_id; + struct reg_field cfg_dec_axi_wr_id; + struct reg_field cfg_dec_rlc_mode_e; + struct reg_field cfg_dec_mode; + struct reg_field cfg_dec_max_burst; + struct reg_field cfg_dec_apf_threshold; + struct reg_field cfg_dec_stream_len; + struct reg_field cfg_dec_init_qp; + struct reg_field cfg_dec_start_code_e; + struct reg_field cfg_dec_pic_width; + struct reg_field cfg_dec_pic_height; + struct reg_field cfg_dec_num_ref_frames; + struct reg_field cfg_dec_scaling_list_e; + struct reg_field cfg_dec_addr_str; + struct reg_field cfg_dec_addr_dst; + struct reg_field cfg_dec_ilace_mode; + struct reg_field cfg_dec_addr_qtable; + struct reg_field cfg_dec_addr_dir_mv; + struct reg_field cfg_dec_tiled_mode_lsb; + struct reg_field cfg_dec_clk_gate_e; +}; + struct hantro_field_enc { /* TODO: populate encoder fields */ }; -struct hantro_field_dec { - /* TODO: populate decoder fields */ +static const struct hantro_field_dec g1_field = { + .cfg_dec_tiled_mode_lsb = REG_FIELD(SWREG(2), 7, 7), + .cfg_dec_clk_gate_e = REG_FIELD(SWREG(2), 10, 10), + .cfg_dec_axi_rd_id = REG_FIELD(SWREG(2), 24, 31), + .cfg_dec_axi_wr_id = REG_FIELD(SWREG(3), 0, 7), + .cfg_dec_rlc_mode_e = REG_FIELD(SWREG(3), 27, 27), + .cfg_dec_mode = REG_FIELD(SWREG(3), 28, 31), + .cfg_dec_max_burst = REG_FIELD(SWREG(2), 0, 4), + .cfg_dec_apf_threshold = REG_FIELD(SWREG(55), 0, 13), + .cfg_dec_stream_len = REG_FIELD(SWREG(6), 0, 23), + .cfg_dec_init_qp = REG_FIELD(SWREG(6), 25, 30), + .cfg_dec_start_code_e = REG_FIELD(SWREG(6), 31, 31), + .cfg_dec_pic_width = REG_FIELD(SWREG(4), 23, 31), + .cfg_dec_pic_height = REG_FIELD(SWREG(4), 11, 18), + .cfg_dec_num_ref_frames = REG_FIELD(SWREG(4), 0, 4), + .cfg_dec_scaling_list_e = REG_FIELD(SWREG(5), 24, 24), + .cfg_dec_addr_str = REG_FIELD(SWREG(12), 0, 31), + .cfg_dec_addr_dst = REG_FIELD(SWREG(13), 0, 31), + .cfg_dec_ilace_mode = REG_FIELD(SWREG(13), 1, 1), + .cfg_dec_addr_qtable = REG_FIELD(SWREG(40), 0, 31), + .cfg_dec_addr_dir_mv = REG_FIELD(SWREG(41), 0, 31), }; #define INIT_FIELD_CFG(f, codec, conf) ({ \ @@ -61,7 +103,27 @@ static int hantro_regmap_fields_init_dec(struct hantro_dev *vpu, if (!vpu->reg_fields_dec) return -ENOMEM; - /* TODO: add decoder fields */ + /* Decoder */ + INIT_DEC_FIELD(dec_axi_wr_id); + INIT_DEC_FIELD(dec_axi_rd_id); + INIT_DEC_FIELD(dec_rlc_mode_e); + INIT_DEC_FIELD(dec_mode); + INIT_DEC_FIELD(dec_max_burst); + INIT_DEC_FIELD(dec_apf_threshold); + INIT_DEC_FIELD(dec_stream_len); + INIT_DEC_FIELD(dec_init_qp); + INIT_DEC_FIELD(dec_start_code_e); + INIT_DEC_FIELD(dec_pic_width); + INIT_DEC_FIELD(dec_pic_height); + INIT_DEC_FIELD(dec_num_ref_frames); + INIT_DEC_FIELD(dec_scaling_list_e); + INIT_DEC_FIELD(dec_addr_str); + INIT_DEC_FIELD(dec_addr_dst); + INIT_DEC_FIELD(dec_ilace_mode); + INIT_DEC_FIELD(dec_addr_qtable); + INIT_DEC_FIELD(dec_addr_dir_mv); + INIT_DEC_FIELD(dec_tiled_mode_lsb); + INIT_DEC_FIELD(dec_clk_gate_e); return 0; } @@ -133,6 +195,17 @@ int hantro_regmap_init_dec(struct hantro_dev *vpu) clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); + switch (vpu->core_hw_dec_rev) { + case HANTRO_G1_REV: + hantro_regmap_dec.max_register = 0x1D8; + field = &g1_field; + break; + default: + dev_err(vpu->dev, "Decoder revision 0x%x not supported by driver.\n", + vpu->core_hw_dec_rev); + return -ENODEV; + } + vpu->regs_dec = devm_regmap_init_mmio(vpu->dev, dec_base, &hantro_regmap_dec); if (IS_ERR(vpu->regs_dec)) { diff --git a/drivers/staging/media/hantro/hantro_regmap.h b/drivers/staging/media/hantro/hantro_regmap.h index 52668a8bafb9..e94fdc055784 100644 --- a/drivers/staging/media/hantro/hantro_regmap.h +++ b/drivers/staging/media/hantro/hantro_regmap.h @@ -9,8 +9,32 @@ #ifndef HANTRO_REGMAP_H_ #define HANTRO_REGMAP_H_ +#define HANTRO_G1_REV 0x6731 + +#define SWREG(nr) ((nr) << 2) + struct hantro_regmap_fields_dec { - /* TODO: populate decoder fields */ + /* Decoder */ + struct regmap_field *dec_axi_rd_id; + struct regmap_field *dec_axi_wr_id; + struct regmap_field *dec_max_burst; + struct regmap_field *dec_rlc_mode_e; + struct regmap_field *dec_mode; + struct regmap_field *dec_apf_threshold; + struct regmap_field *dec_stream_len; + struct regmap_field *dec_init_qp; + struct regmap_field *dec_start_code_e; + struct regmap_field *dec_pic_width; + struct regmap_field *dec_pic_height; + struct regmap_field *dec_num_ref_frames; + struct regmap_field *dec_scaling_list_e; + struct regmap_field *dec_addr_str; + struct regmap_field *dec_addr_dst; + struct regmap_field *dec_ilace_mode; + struct regmap_field *dec_addr_qtable; + struct regmap_field *dec_addr_dir_mv; + struct regmap_field *dec_tiled_mode_lsb; + struct regmap_field *dec_clk_gate_e; }; struct hantro_regmap_fields_enc { From patchwork Mon Oct 12 20:59:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7460C433DF for ; Mon, 12 Oct 2020 20:59:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B96C20797 for ; Mon, 12 Oct 2020 20:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731829AbgJLU7Q (ORCPT ); Mon, 12 Oct 2020 16:59:16 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:49956 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731734AbgJLU7D (ORCPT ); Mon, 12 Oct 2020 16:59:03 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 88D491F44C50 From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/18] media: hantro: add VC8000D postproc support Date: Mon, 12 Oct 2020 23:59:52 +0300 Message-Id: <20201012205957.889185-14-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org VC8000D decodes only to 4x4 tiled NV12 format and the attached PP can be used to de-tile its output. This can bo done in two modes: 1. Pipeline mode, using the same decoder "done" irq 2. External mode, with a separate irq and input setup. This adds the relevant postprocessor fields and support for pipeline mode de-tiling. Signed-off-by: Adrian Ratiu Signed-off-by: Ezequiel Garcia --- .../staging/media/hantro/hantro_postproc.c | 58 ++++++++++++++++--- drivers/staging/media/hantro/hantro_regmap.c | 41 +++++++++++++ drivers/staging/media/hantro/hantro_regmap.h | 8 +++ 3 files changed, 98 insertions(+), 9 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c index 6d1705a60d36..a6b3e243dc39 100644 --- a/drivers/staging/media/hantro/hantro_postproc.c +++ b/drivers/staging/media/hantro/hantro_postproc.c @@ -20,22 +20,35 @@ #define VPU_PP_OUT_RGB 0x0 #define VPU_PP_OUT_YUYV 0x3 +#define VC8000D_PP_OUT_NV12 0x0 + void hantro_postproc_enable(struct hantro_ctx *ctx) { struct hantro_regmap_fields_dec *fields = ctx->dev->reg_fields_dec; struct vb2_v4l2_buffer *dst_buf; - u32 src_pp_fmt, dst_pp_fmt; + u32 src_pp_fmt, dst_pp_fmt, in_width, in_height; dma_addr_t dst_dma; /* Turn on pipeline mode. Must be done first. */ regmap_field_write(fields->pp_pipeline_en, 1); + /* + * use NV12 as input format for pipeline mode as that's what decoder + * outputs, on VC8000D it is 4x4 tiled NV12. + */ src_pp_fmt = VPU_PP_IN_NV12; switch (ctx->vpu_dst_fmt->fourcc) { case V4L2_PIX_FMT_YUYV: dst_pp_fmt = VPU_PP_OUT_YUYV; break; + case V4L2_PIX_FMT_NV12: + /* src == dst == NV12 only makes sense to de-tile on VC8000D */ + if (ctx->dev->core_hw_dec_rev == HANTRO_VC8000_REV) { + dst_pp_fmt = VC8000D_PP_OUT_NV12; + break; + } + fallthrough; default: WARN(1, "output format %d not supported by the post-processor, this wasn't expected.", ctx->vpu_dst_fmt->fourcc); @@ -46,19 +59,46 @@ void hantro_postproc_enable(struct hantro_ctx *ctx) dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); - regmap_field_write(fields->pp_clk_gate, 1); - regmap_field_write(fields->pp_out_endian, 1); - regmap_field_write(fields->pp_out_swap32, 1); - regmap_field_write(fields->pp_max_burst, 16); + switch (ctx->dev->core_hw_dec_rev) { + case HANTRO_G1_REV: + regmap_field_write(fields->pp_clk_gate, 1); + regmap_field_write(fields->pp_out_endian, 1); + regmap_field_write(fields->pp_out_swap32, 1); + regmap_field_write(fields->pp_max_burst, 16); + regmap_field_write(fields->pp_orig_width, MB_WIDTH(ctx->dst_fmt.width)); + regmap_field_write(fields->pp_display_width, ctx->dst_fmt.width); + in_width = MB_WIDTH(ctx->src_fmt.width); + in_height = MB_WIDTH(ctx->src_fmt.height); + break; + case HANTRO_VC8000_REV: + /* on VC8000D the PP is used to de-tile decoder output */ + regmap_field_write(fields->pp_out_tile_e, 0); + + regmap_field_write(fields->pp_out_y_stride, ctx->dst_fmt.width); + regmap_field_write(fields->pp_out_c_stride, ctx->dst_fmt.width); + + regmap_field_write(fields->pp_out_chroma_base, dst_dma + + ctx->dst_fmt.width * ctx->dst_fmt.height); + + /* VC8000D input resolution is a 2-pixels length. */ + in_width = ctx->src_fmt.width / 2; + in_height = ctx->src_fmt.height / 2; + + break; + default: + vpu_err("PP does not recognize HW revision: %x, disabling\n", + ctx->dev->core_hw_dec_rev); + hantro_postproc_disable(ctx); + return; + } + regmap_field_write(fields->pp_out_luma_base, dst_dma); - regmap_field_write(fields->pp_input_width, MB_WIDTH(ctx->dst_fmt.width)); - regmap_field_write(fields->pp_input_height, MB_HEIGHT(ctx->dst_fmt.height)); + regmap_field_write(fields->pp_input_width, in_width); + regmap_field_write(fields->pp_input_height, in_height); regmap_field_write(fields->pp_input_fmt, src_pp_fmt); regmap_field_write(fields->pp_output_fmt, dst_pp_fmt); regmap_field_write(fields->pp_output_width, ctx->dst_fmt.width); regmap_field_write(fields->pp_output_height, ctx->dst_fmt.height); - regmap_field_write(fields->pp_orig_width, MB_WIDTH(ctx->dst_fmt.width)); - regmap_field_write(fields->pp_display_width, ctx->dst_fmt.width); } void hantro_postproc_free(struct hantro_ctx *ctx) diff --git a/drivers/staging/media/hantro/hantro_regmap.c b/drivers/staging/media/hantro/hantro_regmap.c index 0e74ba69034f..b87fe809f2f7 100644 --- a/drivers/staging/media/hantro/hantro_regmap.c +++ b/drivers/staging/media/hantro/hantro_regmap.c @@ -75,6 +75,10 @@ struct hantro_field_dec { struct reg_field cfg_pp_out_swap32; struct reg_field cfg_pp_out_endian; struct reg_field cfg_pp_out_luma_base; + struct reg_field cfg_pp_out_chroma_base; + struct reg_field cfg_pp_in_luma_base; + struct reg_field cfg_pp_in_chroma_base; + struct reg_field cfg_pp_out_tile_e; struct reg_field cfg_pp_input_width; struct reg_field cfg_pp_input_height; struct reg_field cfg_pp_output_width; @@ -93,6 +97,10 @@ struct hantro_field_dec { struct reg_field cfg_pp_scale_hratio; struct reg_field cfg_pp_scale_inv_wratio; struct reg_field cfg_pp_scale_inv_hratio; + struct reg_field cfg_pp_out_c_stride; + struct reg_field cfg_pp_out_y_stride; + struct reg_field cfg_pp_in_c_stride; + struct reg_field cfg_pp_in_y_stride; }; struct hantro_field_enc { @@ -181,6 +189,31 @@ static const struct hantro_field_dec vc8000d_field = { .cfg_dec_ext_timeout_e = REG_FIELD(SWREG(318), 31, 31), .cfg_dec_timeout_cycles = REG_FIELD(SWREG(319), 0, 30), .cfg_dec_timeout_e = REG_FIELD(SWREG(319), 31, 31), + .cfg_pp_pipeline_en = REG_FIELD(SWREG(320), 0, 0), + .cfg_pp_out_tile_e = REG_FIELD(SWREG(320), 3, 3), + .cfg_pp_output_fmt = REG_FIELD(SWREG(322), 18, 22), + .cfg_pp_input_fmt = REG_FIELD(SWREG(322), 27, 31), + .cfg_pp_out_luma_base = REG_FIELD(SWREG(326), 0, 31), + .cfg_pp_out_chroma_base = REG_FIELD(SWREG(328), 0, 31), + .cfg_pp_in_luma_base = REG_FIELD(SWREG(339), 0, 31), + .cfg_pp_in_chroma_base = REG_FIELD(SWREG(341), 0, 31), + .cfg_pp_input_height = REG_FIELD(SWREG(331), 0, 15), + .cfg_pp_input_width = REG_FIELD(SWREG(331), 16, 31), + .cfg_pp_output_height = REG_FIELD(SWREG(332), 0, 15), + .cfg_pp_output_width = REG_FIELD(SWREG(332), 16, 31), + .cfg_pp_crop_starty = REG_FIELD(SWREG(330), 0, 12), + .cfg_pp_rotation_mode = REG_FIELD(SWREG(330), 13, 14), + .cfg_pp_crop_startx = REG_FIELD(SWREG(330), 16, 28), + .cfg_pp_vscale_mode = REG_FIELD(SWREG(322), 23, 24), + .cfg_pp_hscale_mode = REG_FIELD(SWREG(322), 25, 26), + .cfg_pp_scale_wratio = REG_FIELD(SWREG(323), 0, 17), + .cfg_pp_scale_hratio = REG_FIELD(SWREG(322), 0, 17), + .cfg_pp_scale_inv_wratio = REG_FIELD(SWREG(324), 16, 31), + .cfg_pp_scale_inv_hratio = REG_FIELD(SWREG(324), 0, 15), + .cfg_pp_out_c_stride = REG_FIELD(SWREG(329), 0, 15), + .cfg_pp_out_y_stride = REG_FIELD(SWREG(329), 16, 31), + .cfg_pp_in_c_stride = REG_FIELD(SWREG(337), 0, 15), + .cfg_pp_in_y_stride = REG_FIELD(SWREG(337), 16, 31), }; #define INIT_FIELD_CFG(f, codec, conf) ({ \ @@ -246,6 +279,14 @@ static int hantro_regmap_fields_init_dec(struct hantro_dev *vpu, INIT_DEC_FIELD(pp_out_swap32); INIT_DEC_FIELD(pp_out_endian); INIT_DEC_FIELD(pp_out_luma_base); + INIT_DEC_FIELD(pp_out_chroma_base); + INIT_DEC_FIELD(pp_out_tile_e); + INIT_DEC_FIELD(pp_out_c_stride); + INIT_DEC_FIELD(pp_out_y_stride); + INIT_DEC_FIELD(pp_in_c_stride); + INIT_DEC_FIELD(pp_in_y_stride); + INIT_DEC_FIELD(pp_in_luma_base); + INIT_DEC_FIELD(pp_in_chroma_base); INIT_DEC_FIELD(pp_input_width); INIT_DEC_FIELD(pp_input_height); INIT_DEC_FIELD(pp_output_width); diff --git a/drivers/staging/media/hantro/hantro_regmap.h b/drivers/staging/media/hantro/hantro_regmap.h index 8ec0020f40c3..0a39bae83f85 100644 --- a/drivers/staging/media/hantro/hantro_regmap.h +++ b/drivers/staging/media/hantro/hantro_regmap.h @@ -65,6 +65,10 @@ struct hantro_regmap_fields_dec { struct regmap_field *pp_out_swap32; struct regmap_field *pp_out_endian; struct regmap_field *pp_out_luma_base; + struct regmap_field *pp_out_chroma_base; + struct regmap_field *pp_in_luma_base; + struct regmap_field *pp_in_chroma_base; + struct regmap_field *pp_out_tile_e; struct regmap_field *pp_input_width; struct regmap_field *pp_input_height; struct regmap_field *pp_output_width; @@ -83,6 +87,10 @@ struct hantro_regmap_fields_dec { struct regmap_field *pp_scale_hratio; struct regmap_field *pp_scale_inv_wratio; struct regmap_field *pp_scale_inv_hratio; + struct regmap_field *pp_out_y_stride; + struct regmap_field *pp_out_c_stride; + struct regmap_field *pp_in_y_stride; + struct regmap_field *pp_in_c_stride; }; struct hantro_regmap_fields_enc { From patchwork Mon Oct 12 20:59:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF297C433E7 for ; Mon, 12 Oct 2020 21:00:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F21120797 for ; Mon, 12 Oct 2020 21:00:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731710AbgJLU7v (ORCPT ); Mon, 12 Oct 2020 16:59:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730339AbgJLU7E (ORCPT ); Mon, 12 Oct 2020 16:59:04 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8CCCC0613D8; Mon, 12 Oct 2020 13:59:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 62D071F44C56 From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/18] media: hantro: rename h264_dec as it's not G1 specific anymore Date: Mon, 12 Oct 2020 23:59:55 +0300 Message-Id: <20201012205957.889185-17-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The h264 decoder is now capable of decoding on both G1 and VC8000 and other HW revisions can be added in the future by extending the hantro regmap config, so we rename it to reflect the new status. All other core-specific files like "hantro_g1_mpeg2_dec.c" should be renamed as well after they have been ported to the new regmap API. Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/Makefile | 2 +- .../media/hantro/{hantro_g1_h264_dec.c => hantro_h264_dec.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/staging/media/hantro/{hantro_g1_h264_dec.c => hantro_h264_dec.c} (100%) diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 52bc0ee73569..94f1e454c495 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -7,7 +7,7 @@ hantro-vpu-y += \ hantro_v4l2.o \ hantro_postproc.o \ hantro_h1_jpeg_enc.o \ - hantro_g1_h264_dec.o \ + hantro_h264_dec.o \ hantro_g1_mpeg2_dec.o \ hantro_regmap.o \ hantro_g1_vp8_dec.o \ diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_h264_dec.c similarity index 100% rename from drivers/staging/media/hantro/hantro_g1_h264_dec.c rename to drivers/staging/media/hantro/hantro_h264_dec.c From patchwork Mon Oct 12 20:59:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 269701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B37C433E7 for ; Mon, 12 Oct 2020 20:59:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A1AE20790 for ; Mon, 12 Oct 2020 20:59:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731876AbgJLU7m (ORCPT ); Mon, 12 Oct 2020 16:59:42 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:50028 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731756AbgJLU7J (ORCPT ); Mon, 12 Oct 2020 16:59:09 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 8D0221F44C5E From: Adrian Ratiu To: Ezequiel Garcia , Philipp Zabel Cc: Mark Brown , Mauro Carvalho Chehab , Fruehberger Peter , kuhanh.murugasen.krishnan@intel.com, Daniel Vetter , kernel@collabora.com, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/18] media: hantro: document encoder reg fields Date: Mon, 12 Oct 2020 23:59:57 +0300 Message-Id: <20201012205957.889185-19-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012205957.889185-1-adrian.ratiu@collabora.com> References: <20201012205957.889185-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Even though these fields are currently unused it is still a good idea to have them documented for future encoder implementations. Signed-off-by: Ezequiel Garcia Signed-off-by: Adrian Ratiu --- drivers/staging/media/hantro/hantro_regmap.c | 580 ++++++++++++++++++- drivers/staging/media/hantro/hantro_regmap.h | 177 +++++- 2 files changed, 754 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_regmap.c b/drivers/staging/media/hantro/hantro_regmap.c index 62280b873859..f15884f29ed6 100644 --- a/drivers/staging/media/hantro/hantro_regmap.c +++ b/drivers/staging/media/hantro/hantro_regmap.c @@ -115,7 +115,394 @@ struct hantro_field_dec { }; struct hantro_field_enc { - /* TODO: populate encoder fields */ + struct reg_field cfg_enc_timeout_e; + struct reg_field cfg_enc_timeout_cycles; + struct reg_field cfg_enc_mode; + struct reg_field cfg_enc_stream_mode; + struct reg_field cfg_enc_enable; + struct reg_field cfg_enc_pic_type; + struct reg_field cfg_enc_pic_width; + struct reg_field cfg_enc_pic_height; + struct reg_field cfg_enc_burst_len; + struct reg_field cfg_enc_clk_gate_en; + struct reg_field cfg_enc_TODO_swap; + struct reg_field cfg_enc_stream_buf_limit; + struct reg_field cfg_enc_row_len; + struct reg_field cfg_enc_overfill_r; + struct reg_field cfg_enc_overfill_b; + struct reg_field cfg_enc_src_format; + struct reg_field cfg_enc_init_qp; + struct reg_field cfg_enc_chroma_qp_offset; + struct reg_field cfg_enc_idr_pic_id; + struct reg_field cfg_enc_nal_ref_idc; + struct reg_field cfg_enc_pps_id; + struct reg_field cfg_enc_nal_unit_type; + struct reg_field cfg_enc_frame_num; + struct reg_field cfg_enc_min_cb_size; + struct reg_field cfg_enc_max_cb_size; + struct reg_field cfg_enc_max_trb_size; + struct reg_field cfg_enc_min_trb_size; + struct reg_field cfg_enc_deblocking_filter_dis; + struct reg_field cfg_enc_slice_deblocking_filter_override; + struct reg_field cfg_enc_slice_deblocking_filter_dis; + struct reg_field cfg_enc_pps_deblocking_filter_override; + struct reg_field cfg_enc_slice_alpha_div2; + struct reg_field cfg_enc_slice_beta_div2; + struct reg_field cfg_enc_slice_size; + struct reg_field cfg_enc_nal_size_write; + struct reg_field cfg_enc_cabac_init_idc; + struct reg_field cfg_enc_pic_qp; + struct reg_field cfg_enc_qp_frac; + struct reg_field cfg_enc_entropy_coding_mode; + struct reg_field cfg_enc_axi_r_outstanding_num; + struct reg_field cfg_enc_axi_w_outstanding_num; + struct reg_field cfg_enc_trans8x8_mode_en; + struct reg_field cfg_enc_inter4x4_mode; + struct reg_field cfg_enc_quarter_pixmv_dis; + struct reg_field cfg_enc_addr_cabac; + struct reg_field cfg_enc_addr_str; + struct reg_field cfg_enc_addr_size_table; + struct reg_field cfg_enc_addr_rec_luma; + struct reg_field cfg_enc_addr_rec_luma_4n; + struct reg_field cfg_enc_addr_ref_luma_l0_4n0; + struct reg_field cfg_enc_addr_rec_chroma; + struct reg_field cfg_enc_addr_ref_luma; + struct reg_field cfg_enc_addr_ref_chroma; + struct reg_field cfg_enc_addr_src_y; + struct reg_field cfg_enc_addr_src_cb; + struct reg_field cfg_enc_addr_src_cr; + struct reg_field cfg_enc_log2_max_pic_order_cnt_lsb; + struct reg_field cfg_enc_log2_max_frame_num; + struct reg_field cfg_enc_pic_order_cnt_type; + struct reg_field cfg_enc_l0_delta_framenum0; + struct reg_field cfg_enc_l0_used_by_next_pic0; + struct reg_field cfg_enc_l0_used_by_next_pic1; + + struct reg_field cfg_enc_lu_stride; + struct reg_field cfg_enc_cr_stride; + struct reg_field cfg_enc_ref_lu_stride; + struct reg_field cfg_enc_ref_ds_lu_stride; + struct reg_field cfg_enc_ref_cr_stride; + struct reg_field cfg_enc_ipcm2_left; + struct reg_field cfg_enc_ipcm2_right; + struct reg_field cfg_enc_ipcm2_top; + struct reg_field cfg_enc_ipcm2_bottom; + + struct reg_field cfg_enc_slice_qp_offset; + struct reg_field cfg_enc_qp_min; + struct reg_field cfg_enc_qp_max; + + struct reg_field cfg_enc_lambda_satd_me_0; + struct reg_field cfg_enc_lambda_satd_me_1; + struct reg_field cfg_enc_lambda_satd_me_2; + struct reg_field cfg_enc_lambda_satd_me_3; + struct reg_field cfg_enc_lambda_satd_me_4; + struct reg_field cfg_enc_lambda_satd_me_5; + struct reg_field cfg_enc_lambda_satd_me_6; + struct reg_field cfg_enc_lambda_satd_me_7; + struct reg_field cfg_enc_lambda_satd_me_8; + struct reg_field cfg_enc_lambda_satd_me_9; + struct reg_field cfg_enc_lambda_satd_me_10; + struct reg_field cfg_enc_lambda_satd_me_11; + struct reg_field cfg_enc_lambda_satd_me_12; + struct reg_field cfg_enc_lambda_satd_me_13; + struct reg_field cfg_enc_lambda_satd_me_14; + struct reg_field cfg_enc_lambda_satd_me_15; + struct reg_field cfg_enc_lambda_satd_me_16; + struct reg_field cfg_enc_lambda_satd_me_17; + struct reg_field cfg_enc_lambda_satd_me_18; + struct reg_field cfg_enc_lambda_satd_me_19; + struct reg_field cfg_enc_lambda_satd_me_20; + struct reg_field cfg_enc_lambda_satd_me_21; + struct reg_field cfg_enc_lambda_satd_me_22; + struct reg_field cfg_enc_lambda_satd_me_23; + struct reg_field cfg_enc_lambda_satd_me_24; + struct reg_field cfg_enc_lambda_satd_me_25; + struct reg_field cfg_enc_lambda_satd_me_26; + struct reg_field cfg_enc_lambda_satd_me_27; + struct reg_field cfg_enc_lambda_satd_me_28; + struct reg_field cfg_enc_lambda_satd_me_29; + struct reg_field cfg_enc_lambda_satd_me_30; + struct reg_field cfg_enc_lambda_satd_me_31; + + struct reg_field cfg_enc_lambda_satd_0; + struct reg_field cfg_enc_lambda_satd_1; + struct reg_field cfg_enc_lambda_satd_2; + struct reg_field cfg_enc_lambda_satd_3; + struct reg_field cfg_enc_lambda_satd_4; + struct reg_field cfg_enc_lambda_satd_5; + struct reg_field cfg_enc_lambda_satd_6; + struct reg_field cfg_enc_lambda_satd_7; + struct reg_field cfg_enc_lambda_satd_8; + struct reg_field cfg_enc_lambda_satd_9; + struct reg_field cfg_enc_lambda_satd_10; + struct reg_field cfg_enc_lambda_satd_11; + struct reg_field cfg_enc_lambda_satd_12; + struct reg_field cfg_enc_lambda_satd_13; + struct reg_field cfg_enc_lambda_satd_14; + struct reg_field cfg_enc_lambda_satd_15; + struct reg_field cfg_enc_lambda_satd_16; + struct reg_field cfg_enc_lambda_satd_17; + struct reg_field cfg_enc_lambda_satd_18; + struct reg_field cfg_enc_lambda_satd_19; + struct reg_field cfg_enc_lambda_satd_20; + struct reg_field cfg_enc_lambda_satd_21; + struct reg_field cfg_enc_lambda_satd_22; + struct reg_field cfg_enc_lambda_satd_23; + struct reg_field cfg_enc_lambda_satd_24; + struct reg_field cfg_enc_lambda_satd_25; + struct reg_field cfg_enc_lambda_satd_26; + struct reg_field cfg_enc_lambda_satd_27; + struct reg_field cfg_enc_lambda_satd_28; + struct reg_field cfg_enc_lambda_satd_29; + struct reg_field cfg_enc_lambda_satd_30; + struct reg_field cfg_enc_lambda_satd_31; + + struct reg_field cfg_enc_lambda_sse_me_0; + struct reg_field cfg_enc_lambda_sse_me_1; + struct reg_field cfg_enc_lambda_sse_me_2; + struct reg_field cfg_enc_lambda_sse_me_3; + struct reg_field cfg_enc_lambda_sse_me_4; + struct reg_field cfg_enc_lambda_sse_me_5; + struct reg_field cfg_enc_lambda_sse_me_6; + struct reg_field cfg_enc_lambda_sse_me_7; + struct reg_field cfg_enc_lambda_sse_me_8; + struct reg_field cfg_enc_lambda_sse_me_9; + struct reg_field cfg_enc_lambda_sse_me_10; + struct reg_field cfg_enc_lambda_sse_me_11; + struct reg_field cfg_enc_lambda_sse_me_12; + struct reg_field cfg_enc_lambda_sse_me_13; + struct reg_field cfg_enc_lambda_sse_me_14; + struct reg_field cfg_enc_lambda_sse_me_15; + struct reg_field cfg_enc_lambda_sse_me_16; + struct reg_field cfg_enc_lambda_sse_me_17; + struct reg_field cfg_enc_lambda_sse_me_18; + struct reg_field cfg_enc_lambda_sse_me_19; + struct reg_field cfg_enc_lambda_sse_me_20; + struct reg_field cfg_enc_lambda_sse_me_21; + struct reg_field cfg_enc_lambda_sse_me_22; + struct reg_field cfg_enc_lambda_sse_me_23; + struct reg_field cfg_enc_lambda_sse_me_24; + struct reg_field cfg_enc_lambda_sse_me_25; + struct reg_field cfg_enc_lambda_sse_me_26; + struct reg_field cfg_enc_lambda_sse_me_27; + struct reg_field cfg_enc_lambda_sse_me_28; + struct reg_field cfg_enc_lambda_sse_me_29; + struct reg_field cfg_enc_lambda_sse_me_30; + struct reg_field cfg_enc_lambda_sse_me_31; +}; + +static const struct hantro_field_enc h1_field = { + .cfg_enc_mode = REG_FIELD(SWREG(14), 1, 2), + .cfg_enc_enable = REG_FIELD(SWREG(14), 0, 0), + .cfg_enc_pic_type = REG_FIELD(SWREG(14), 3, 4), + .cfg_enc_pic_width = REG_FIELD(SWREG(14), 19, 27), + .cfg_enc_pic_height = REG_FIELD(SWREG(14), 10, 18), + .cfg_enc_nal_size_write = REG_FIELD(SWREG(14), 29, 29), + .cfg_enc_stream_mode = REG_FIELD(SWREG(18), 16, 16), + .cfg_enc_burst_len = REG_FIELD(SWREG(2), 8, 13), + .cfg_enc_clk_gate_en = REG_FIELD(SWREG(2), 4, 4), + .cfg_enc_stream_buf_limit = REG_FIELD(SWREG(48), 0, 31), + .cfg_enc_row_len = REG_FIELD(SWREG(15), 12, 25), + .cfg_enc_overfill_r = REG_FIELD(SWREG(15), 10, 11), + .cfg_enc_overfill_b = REG_FIELD(SWREG(15), 6, 9), + .cfg_enc_src_format = REG_FIELD(SWREG(15), 2, 5), + .cfg_enc_init_qp = REG_FIELD(SWREG(16), 26, 31), + .cfg_enc_slice_alpha_div2 = REG_FIELD(SWREG(16), 22, 25), + .cfg_enc_slice_beta_div2 = REG_FIELD(SWREG(16), 18, 21), + .cfg_enc_idr_pic_id = REG_FIELD(SWREG(16), 1, 4), + .cfg_enc_pps_id = REG_FIELD(SWREG(17), 24, 31), + .cfg_enc_frame_num = REG_FIELD(SWREG(17), 0, 15), + .cfg_enc_chroma_qp_offset = REG_FIELD(SWREG(16), 13, 17), + .cfg_enc_deblocking_filter_dis = REG_FIELD(SWREG(18), 30, 31), + .cfg_enc_slice_size = REG_FIELD(SWREG(18), 23, 29), + .cfg_enc_cabac_init_idc = REG_FIELD(SWREG(18), 19, 20), + .cfg_enc_entropy_coding_mode = REG_FIELD(SWREG(18), 18, 18), + .cfg_enc_trans8x8_mode_en = REG_FIELD(SWREG(18), 21, 21), + .cfg_enc_inter4x4_mode = REG_FIELD(SWREG(18), 17, 17), + .cfg_enc_quarter_pixmv_dis = REG_FIELD(SWREG(18), 22, 22), + .cfg_enc_addr_str = REG_FIELD(SWREG(5), 0, 31), + .cfg_enc_addr_size_table = REG_FIELD(SWREG(6), 0, 31), + .cfg_enc_addr_rec_luma = REG_FIELD(SWREG(9), 0, 31), + .cfg_enc_addr_rec_chroma = REG_FIELD(SWREG(10), 0, 31), + .cfg_enc_addr_ref_luma = REG_FIELD(SWREG(7), 0, 31), + .cfg_enc_addr_ref_chroma = REG_FIELD(SWREG(8), 0, 31), + .cfg_enc_addr_src_y = REG_FIELD(SWREG(11), 0, 31), + .cfg_enc_addr_src_cb = REG_FIELD(SWREG(12), 0, 31), + .cfg_enc_addr_src_cr = REG_FIELD(SWREG(13), 0, 31), +}; + +static const struct hantro_field_enc vc8000e_field = { + .cfg_enc_burst_len = REG_FIELD(SWREG(81), 24, 31), + .cfg_enc_timeout_e = REG_FIELD(SWREG(81), 23, 23), + .cfg_enc_timeout_cycles = REG_FIELD(SWREG(81), 0, 22), + .cfg_enc_mode = REG_FIELD(SWREG(4), 29, 31), + .cfg_enc_stream_mode = REG_FIELD(SWREG(4), 18, 18), + .cfg_enc_enable = REG_FIELD(SWREG(5), 0, 0), + .cfg_enc_pic_type = REG_FIELD(SWREG(5), 1, 2), + .cfg_enc_pic_width = REG_FIELD(SWREG(5), 22, 31), + .cfg_enc_pic_height = REG_FIELD(SWREG(5), 11, 21), + .cfg_enc_stream_buf_limit = REG_FIELD(SWREG(9), 0, 31), + .cfg_enc_row_len = REG_FIELD(SWREG(38), 6, 19), + .cfg_enc_overfill_r = REG_FIELD(SWREG(38), 4, 5), + .cfg_enc_overfill_b = REG_FIELD(SWREG(38), 1, 3), + .cfg_enc_src_format = REG_FIELD(SWREG(38), 28, 31), + .cfg_enc_init_qp = REG_FIELD(SWREG(7), 26, 31), + .cfg_enc_idr_pic_id = REG_FIELD(SWREG(193), 2, 2), + .cfg_enc_nal_ref_idc = REG_FIELD(SWREG(193), 3, 3), + .cfg_enc_pic_qp = REG_FIELD(SWREG(7), 8, 13), + .cfg_enc_qp_frac = REG_FIELD(SWREG(182), 16, 31), + .cfg_enc_nal_unit_type = REG_FIELD(SWREG(191), 26, 31), + .cfg_enc_pps_id = REG_FIELD(SWREG(191), 17, 22), + .cfg_enc_frame_num = REG_FIELD(SWREG(192), 0, 31), + .cfg_enc_min_cb_size = REG_FIELD(SWREG(4), 25, 26), + .cfg_enc_max_cb_size = REG_FIELD(SWREG(4), 23, 24), + .cfg_enc_min_trb_size = REG_FIELD(SWREG(4), 21, 22), + .cfg_enc_max_trb_size = REG_FIELD(SWREG(4), 19, 20), + .cfg_enc_chroma_qp_offset = REG_FIELD(SWREG(4), 13, 17), + .cfg_enc_slice_deblocking_filter_dis = REG_FIELD(SWREG(6), 15, 15), + .cfg_enc_pps_deblocking_filter_override = REG_FIELD(SWREG(5), 9, 9), + .cfg_enc_slice_deblocking_filter_override = REG_FIELD(SWREG(5), 8, 8), + .cfg_enc_slice_alpha_div2 = REG_FIELD(SWREG(6), 11, 14), + .cfg_enc_slice_beta_div2 = REG_FIELD(SWREG(6), 7, 10), + .cfg_enc_slice_size = REG_FIELD(SWREG(6), 25, 31), + .cfg_enc_nal_size_write = REG_FIELD(SWREG(6), 1, 1), + .cfg_enc_cabac_init_idc = REG_FIELD(SWREG(7), 25, 25), + .cfg_enc_entropy_coding_mode = REG_FIELD(SWREG(193), 0, 0), + .cfg_enc_axi_r_outstanding_num = REG_FIELD(SWREG(261), 4, 11), + .cfg_enc_axi_w_outstanding_num = REG_FIELD(SWREG(246), 6, 13), + .cfg_enc_trans8x8_mode_en = REG_FIELD(SWREG(193), 1, 1), + .cfg_enc_addr_str = REG_FIELD(SWREG(8), 0, 31), + .cfg_enc_addr_size_table = REG_FIELD(SWREG(10), 0, 31), + .cfg_enc_addr_rec_luma_4n = REG_FIELD(SWREG(72), 0, 31), + .cfg_enc_addr_ref_luma_l0_4n0 = REG_FIELD(SWREG(74), 0, 31), + .cfg_enc_addr_rec_luma = REG_FIELD(SWREG(15), 0, 31), + .cfg_enc_addr_rec_chroma = REG_FIELD(SWREG(16), 0, 31), + .cfg_enc_addr_ref_luma = REG_FIELD(SWREG(18), 0, 31), + .cfg_enc_addr_ref_chroma = REG_FIELD(SWREG(19), 0, 31), + .cfg_enc_addr_src_y = REG_FIELD(SWREG(12), 0, 31), + .cfg_enc_addr_src_cb = REG_FIELD(SWREG(13), 0, 31), + .cfg_enc_addr_src_cr = REG_FIELD(SWREG(14), 0, 31), + .cfg_enc_log2_max_pic_order_cnt_lsb = REG_FIELD(SWREG(277), 27, 31), + .cfg_enc_log2_max_frame_num = REG_FIELD(SWREG(277), 22, 26), + .cfg_enc_pic_order_cnt_type = REG_FIELD(SWREG(277), 20, 21), + .cfg_enc_l0_delta_framenum0 = REG_FIELD(SWREG(193), 21, 31), + .cfg_enc_l0_used_by_next_pic0 = REG_FIELD(SWREG(193), 20, 20), + .cfg_enc_l0_used_by_next_pic1 = REG_FIELD(SWREG(193), 8, 8), + + .cfg_enc_lu_stride = REG_FIELD(SWREG(210), 12, 31), + .cfg_enc_cr_stride = REG_FIELD(SWREG(211), 12, 31), + .cfg_enc_ref_lu_stride = REG_FIELD(SWREG(212), 12, 31), + .cfg_enc_ref_cr_stride = REG_FIELD(SWREG(237), 12, 31), + .cfg_enc_ref_ds_lu_stride = REG_FIELD(SWREG(213), 14, 31), + + .cfg_enc_ipcm2_left = REG_FIELD(SWREG(210), 3, 11), + .cfg_enc_ipcm2_right = REG_FIELD(SWREG(211), 3, 11), + .cfg_enc_ipcm2_top = REG_FIELD(SWREG(212), 3, 11), + .cfg_enc_ipcm2_bottom = REG_FIELD(SWREG(213), 5, 13), + + .cfg_enc_slice_qp_offset = REG_FIELD(SWREG(170), 5, 10), + .cfg_enc_qp_min = REG_FIELD(SWREG(172), 5, 10), + .cfg_enc_qp_max = REG_FIELD(SWREG(173), 5, 10), + + .cfg_enc_lambda_satd_me_0 = REG_FIELD(SWREG(28), 19, 31), + .cfg_enc_lambda_satd_me_1 = REG_FIELD(SWREG(28), 6, 18), + .cfg_enc_lambda_satd_me_2 = REG_FIELD(SWREG(29), 19, 31), + .cfg_enc_lambda_satd_me_3 = REG_FIELD(SWREG(29), 6, 18), + .cfg_enc_lambda_satd_me_4 = REG_FIELD(SWREG(30), 19, 31), + .cfg_enc_lambda_satd_me_5 = REG_FIELD(SWREG(30), 6, 18), + .cfg_enc_lambda_satd_me_6 = REG_FIELD(SWREG(31), 19, 31), + .cfg_enc_lambda_satd_me_7 = REG_FIELD(SWREG(31), 6, 18), + .cfg_enc_lambda_satd_me_8 = REG_FIELD(SWREG(32), 19, 31), + .cfg_enc_lambda_satd_me_9 = REG_FIELD(SWREG(32), 6, 18), + .cfg_enc_lambda_satd_me_10 = REG_FIELD(SWREG(33), 19, 31), + .cfg_enc_lambda_satd_me_11 = REG_FIELD(SWREG(33), 6, 18), + .cfg_enc_lambda_satd_me_12 = REG_FIELD(SWREG(34), 19, 31), + .cfg_enc_lambda_satd_me_13 = REG_FIELD(SWREG(34), 6, 18), + .cfg_enc_lambda_satd_me_14 = REG_FIELD(SWREG(78), 19, 31), + .cfg_enc_lambda_satd_me_15 = REG_FIELD(SWREG(78), 6, 18), + .cfg_enc_lambda_satd_me_16 = REG_FIELD(SWREG(150), 19, 31), + .cfg_enc_lambda_satd_me_17 = REG_FIELD(SWREG(150), 6, 18), + .cfg_enc_lambda_satd_me_18 = REG_FIELD(SWREG(151), 19, 31), + .cfg_enc_lambda_satd_me_19 = REG_FIELD(SWREG(151), 6, 18), + .cfg_enc_lambda_satd_me_20 = REG_FIELD(SWREG(152), 19, 31), + .cfg_enc_lambda_satd_me_21 = REG_FIELD(SWREG(152), 6, 18), + .cfg_enc_lambda_satd_me_22 = REG_FIELD(SWREG(153), 19, 31), + .cfg_enc_lambda_satd_me_23 = REG_FIELD(SWREG(153), 6, 18), + .cfg_enc_lambda_satd_me_24 = REG_FIELD(SWREG(154), 19, 31), + .cfg_enc_lambda_satd_me_25 = REG_FIELD(SWREG(154), 6, 18), + .cfg_enc_lambda_satd_me_26 = REG_FIELD(SWREG(155), 19, 31), + .cfg_enc_lambda_satd_me_27 = REG_FIELD(SWREG(155), 6, 18), + .cfg_enc_lambda_satd_me_28 = REG_FIELD(SWREG(156), 19, 31), + .cfg_enc_lambda_satd_me_29 = REG_FIELD(SWREG(156), 6, 18), + .cfg_enc_lambda_satd_me_30 = REG_FIELD(SWREG(157), 19, 31), + .cfg_enc_lambda_satd_me_31 = REG_FIELD(SWREG(157), 6, 18), + + .cfg_enc_lambda_satd_0 = REG_FIELD(SWREG(125), 18, 31), + .cfg_enc_lambda_satd_1 = REG_FIELD(SWREG(125), 4, 17), + .cfg_enc_lambda_satd_2 = REG_FIELD(SWREG(126), 18, 31), + .cfg_enc_lambda_satd_3 = REG_FIELD(SWREG(126), 4, 17), + .cfg_enc_lambda_satd_4 = REG_FIELD(SWREG(127), 18, 31), + .cfg_enc_lambda_satd_5 = REG_FIELD(SWREG(127), 4, 17), + .cfg_enc_lambda_satd_6 = REG_FIELD(SWREG(128), 18, 31), + .cfg_enc_lambda_satd_7 = REG_FIELD(SWREG(128), 4, 17), + .cfg_enc_lambda_satd_8 = REG_FIELD(SWREG(129), 18, 31), + .cfg_enc_lambda_satd_9 = REG_FIELD(SWREG(129), 4, 17), + .cfg_enc_lambda_satd_10 = REG_FIELD(SWREG(130), 18, 31), + .cfg_enc_lambda_satd_11 = REG_FIELD(SWREG(130), 4, 17), + .cfg_enc_lambda_satd_12 = REG_FIELD(SWREG(131), 18, 31), + .cfg_enc_lambda_satd_13 = REG_FIELD(SWREG(131), 4, 17), + .cfg_enc_lambda_satd_14 = REG_FIELD(SWREG(132), 18, 31), + .cfg_enc_lambda_satd_15 = REG_FIELD(SWREG(132), 4, 17), + .cfg_enc_lambda_satd_16 = REG_FIELD(SWREG(174), 18, 31), + .cfg_enc_lambda_satd_17 = REG_FIELD(SWREG(174), 4, 17), + .cfg_enc_lambda_satd_18 = REG_FIELD(SWREG(175), 18, 31), + .cfg_enc_lambda_satd_19 = REG_FIELD(SWREG(175), 4, 17), + .cfg_enc_lambda_satd_20 = REG_FIELD(SWREG(176), 18, 31), + .cfg_enc_lambda_satd_21 = REG_FIELD(SWREG(176), 4, 17), + .cfg_enc_lambda_satd_22 = REG_FIELD(SWREG(177), 18, 31), + .cfg_enc_lambda_satd_23 = REG_FIELD(SWREG(177), 4, 17), + .cfg_enc_lambda_satd_24 = REG_FIELD(SWREG(178), 18, 31), + .cfg_enc_lambda_satd_25 = REG_FIELD(SWREG(178), 4, 17), + .cfg_enc_lambda_satd_26 = REG_FIELD(SWREG(179), 18, 31), + .cfg_enc_lambda_satd_27 = REG_FIELD(SWREG(179), 4, 17), + .cfg_enc_lambda_satd_28 = REG_FIELD(SWREG(180), 18, 31), + .cfg_enc_lambda_satd_29 = REG_FIELD(SWREG(180), 4, 17), + .cfg_enc_lambda_satd_30 = REG_FIELD(SWREG(181), 18, 31), + .cfg_enc_lambda_satd_31 = REG_FIELD(SWREG(181), 4, 17), + + .cfg_enc_lambda_sse_me_0 = REG_FIELD(SWREG(79), 11, 31), + .cfg_enc_lambda_sse_me_1 = REG_FIELD(SWREG(122), 11, 31), + .cfg_enc_lambda_sse_me_2 = REG_FIELD(SWREG(123), 11, 31), + .cfg_enc_lambda_sse_me_3 = REG_FIELD(SWREG(124), 11, 31), + .cfg_enc_lambda_sse_me_4 = REG_FIELD(SWREG(138), 11, 31), + .cfg_enc_lambda_sse_me_5 = REG_FIELD(SWREG(139), 11, 31), + .cfg_enc_lambda_sse_me_6 = REG_FIELD(SWREG(140), 11, 31), + .cfg_enc_lambda_sse_me_7 = REG_FIELD(SWREG(141), 11, 31), + .cfg_enc_lambda_sse_me_8 = REG_FIELD(SWREG(142), 11, 31), + .cfg_enc_lambda_sse_me_9 = REG_FIELD(SWREG(143), 11, 31), + .cfg_enc_lambda_sse_me_10 = REG_FIELD(SWREG(144), 11, 31), + .cfg_enc_lambda_sse_me_11 = REG_FIELD(SWREG(145), 11, 31), + .cfg_enc_lambda_sse_me_12 = REG_FIELD(SWREG(146), 11, 31), + .cfg_enc_lambda_sse_me_13 = REG_FIELD(SWREG(147), 11, 31), + .cfg_enc_lambda_sse_me_14 = REG_FIELD(SWREG(148), 11, 31), + .cfg_enc_lambda_sse_me_15 = REG_FIELD(SWREG(149), 11, 31), + .cfg_enc_lambda_sse_me_16 = REG_FIELD(SWREG(158), 11, 31), + .cfg_enc_lambda_sse_me_17 = REG_FIELD(SWREG(159), 11, 31), + .cfg_enc_lambda_sse_me_18 = REG_FIELD(SWREG(160), 11, 31), + .cfg_enc_lambda_sse_me_19 = REG_FIELD(SWREG(161), 11, 31), + .cfg_enc_lambda_sse_me_20 = REG_FIELD(SWREG(162), 11, 31), + .cfg_enc_lambda_sse_me_21 = REG_FIELD(SWREG(163), 11, 31), + .cfg_enc_lambda_sse_me_22 = REG_FIELD(SWREG(164), 11, 31), + .cfg_enc_lambda_sse_me_23 = REG_FIELD(SWREG(165), 11, 31), + .cfg_enc_lambda_sse_me_24 = REG_FIELD(SWREG(166), 11, 31), + .cfg_enc_lambda_sse_me_25 = REG_FIELD(SWREG(167), 11, 31), + .cfg_enc_lambda_sse_me_26 = REG_FIELD(SWREG(168), 11, 31), + .cfg_enc_lambda_sse_me_27 = REG_FIELD(SWREG(169), 11, 31), + .cfg_enc_lambda_sse_me_28 = REG_FIELD(SWREG(170), 11, 31), + .cfg_enc_lambda_sse_me_29 = REG_FIELD(SWREG(171), 11, 31), + .cfg_enc_lambda_sse_me_30 = REG_FIELD(SWREG(172), 11, 31), + .cfg_enc_lambda_sse_me_31 = REG_FIELD(SWREG(173), 11, 31), }; static const struct hantro_field_dec g1_field = { @@ -353,7 +740,181 @@ static int hantro_regmap_fields_init_enc(struct hantro_dev *vpu, if (!vpu->reg_fields_enc) return -ENOMEM; - /* TODO: add encoder fields */ + /* Encoder */ + INIT_ENC_FIELD(enc_timeout_cycles); + INIT_ENC_FIELD(enc_timeout_e); + INIT_ENC_FIELD(enc_mode); + INIT_ENC_FIELD(enc_stream_mode); + INIT_ENC_FIELD(enc_enable); + INIT_ENC_FIELD(enc_pic_type); + INIT_ENC_FIELD(enc_pic_width); + INIT_ENC_FIELD(enc_pic_height); + INIT_ENC_FIELD(enc_burst_len); + INIT_ENC_FIELD(enc_clk_gate_en); + INIT_ENC_FIELD(enc_stream_buf_limit); + INIT_ENC_FIELD(enc_row_len); + INIT_ENC_FIELD(enc_overfill_r); + INIT_ENC_FIELD(enc_overfill_b); + INIT_ENC_FIELD(enc_src_format); + INIT_ENC_FIELD(enc_init_qp); + INIT_ENC_FIELD(enc_chroma_qp_offset); + INIT_ENC_FIELD(enc_deblocking_filter_dis); + INIT_ENC_FIELD(enc_slice_deblocking_filter_dis); + INIT_ENC_FIELD(enc_pps_deblocking_filter_override); + INIT_ENC_FIELD(enc_slice_deblocking_filter_override); + INIT_ENC_FIELD(enc_axi_r_outstanding_num); + INIT_ENC_FIELD(enc_axi_w_outstanding_num); + INIT_ENC_FIELD(enc_slice_alpha_div2); + INIT_ENC_FIELD(enc_slice_beta_div2); + INIT_ENC_FIELD(enc_idr_pic_id); + INIT_ENC_FIELD(enc_nal_ref_idc); + INIT_ENC_FIELD(enc_pps_id); + INIT_ENC_FIELD(enc_nal_unit_type); + INIT_ENC_FIELD(enc_frame_num); + INIT_ENC_FIELD(enc_min_cb_size); + INIT_ENC_FIELD(enc_max_cb_size); + INIT_ENC_FIELD(enc_min_trb_size); + INIT_ENC_FIELD(enc_max_trb_size); + INIT_ENC_FIELD(enc_slice_size); + INIT_ENC_FIELD(enc_nal_size_write); + INIT_ENC_FIELD(enc_cabac_init_idc); + INIT_ENC_FIELD(enc_pic_qp); + INIT_ENC_FIELD(enc_qp_frac); + INIT_ENC_FIELD(enc_entropy_coding_mode); + INIT_ENC_FIELD(enc_trans8x8_mode_en); + INIT_ENC_FIELD(enc_inter4x4_mode); + INIT_ENC_FIELD(enc_quarter_pixmv_dis); + INIT_ENC_FIELD(enc_addr_str); + INIT_ENC_FIELD(enc_addr_size_table); + INIT_ENC_FIELD(enc_addr_rec_luma); + INIT_ENC_FIELD(enc_addr_rec_chroma); + INIT_ENC_FIELD(enc_addr_rec_luma_4n); + INIT_ENC_FIELD(enc_addr_ref_luma_l0_4n0); + INIT_ENC_FIELD(enc_addr_ref_luma); + INIT_ENC_FIELD(enc_addr_ref_chroma); + INIT_ENC_FIELD(enc_addr_src_y); + INIT_ENC_FIELD(enc_addr_src_cb); + INIT_ENC_FIELD(enc_addr_src_cr); + INIT_ENC_FIELD(enc_log2_max_pic_order_cnt_lsb); + INIT_ENC_FIELD(enc_log2_max_frame_num); + INIT_ENC_FIELD(enc_pic_order_cnt_type); + INIT_ENC_FIELD(enc_l0_delta_framenum0); + INIT_ENC_FIELD(enc_l0_used_by_next_pic0); + INIT_ENC_FIELD(enc_l0_used_by_next_pic1); + + INIT_ENC_FIELD(enc_lu_stride); + INIT_ENC_FIELD(enc_cr_stride); + INIT_ENC_FIELD(enc_ref_lu_stride); + INIT_ENC_FIELD(enc_ref_ds_lu_stride); + INIT_ENC_FIELD(enc_ref_cr_stride); + INIT_ENC_FIELD(enc_ipcm2_left); + INIT_ENC_FIELD(enc_ipcm2_right); + INIT_ENC_FIELD(enc_ipcm2_top); + INIT_ENC_FIELD(enc_ipcm2_bottom); + + /* Quantization fields */ + INIT_ENC_FIELD(enc_slice_qp_offset); + INIT_ENC_FIELD(enc_qp_min); + INIT_ENC_FIELD(enc_qp_max); + + INIT_ENC_FIELD(enc_lambda_satd_me_0); + INIT_ENC_FIELD(enc_lambda_satd_me_1); + INIT_ENC_FIELD(enc_lambda_satd_me_2); + INIT_ENC_FIELD(enc_lambda_satd_me_3); + INIT_ENC_FIELD(enc_lambda_satd_me_4); + INIT_ENC_FIELD(enc_lambda_satd_me_5); + INIT_ENC_FIELD(enc_lambda_satd_me_6); + INIT_ENC_FIELD(enc_lambda_satd_me_7); + INIT_ENC_FIELD(enc_lambda_satd_me_8); + INIT_ENC_FIELD(enc_lambda_satd_me_9); + INIT_ENC_FIELD(enc_lambda_satd_me_10); + INIT_ENC_FIELD(enc_lambda_satd_me_11); + INIT_ENC_FIELD(enc_lambda_satd_me_12); + INIT_ENC_FIELD(enc_lambda_satd_me_13); + INIT_ENC_FIELD(enc_lambda_satd_me_14); + INIT_ENC_FIELD(enc_lambda_satd_me_15); + INIT_ENC_FIELD(enc_lambda_satd_me_16); + INIT_ENC_FIELD(enc_lambda_satd_me_17); + INIT_ENC_FIELD(enc_lambda_satd_me_18); + INIT_ENC_FIELD(enc_lambda_satd_me_19); + INIT_ENC_FIELD(enc_lambda_satd_me_20); + INIT_ENC_FIELD(enc_lambda_satd_me_21); + INIT_ENC_FIELD(enc_lambda_satd_me_22); + INIT_ENC_FIELD(enc_lambda_satd_me_23); + INIT_ENC_FIELD(enc_lambda_satd_me_24); + INIT_ENC_FIELD(enc_lambda_satd_me_25); + INIT_ENC_FIELD(enc_lambda_satd_me_26); + INIT_ENC_FIELD(enc_lambda_satd_me_27); + INIT_ENC_FIELD(enc_lambda_satd_me_28); + INIT_ENC_FIELD(enc_lambda_satd_me_29); + INIT_ENC_FIELD(enc_lambda_satd_me_30); + INIT_ENC_FIELD(enc_lambda_satd_me_31); + + INIT_ENC_FIELD(enc_lambda_satd_0); + INIT_ENC_FIELD(enc_lambda_satd_1); + INIT_ENC_FIELD(enc_lambda_satd_2); + INIT_ENC_FIELD(enc_lambda_satd_3); + INIT_ENC_FIELD(enc_lambda_satd_4); + INIT_ENC_FIELD(enc_lambda_satd_5); + INIT_ENC_FIELD(enc_lambda_satd_6); + INIT_ENC_FIELD(enc_lambda_satd_7); + INIT_ENC_FIELD(enc_lambda_satd_8); + INIT_ENC_FIELD(enc_lambda_satd_9); + INIT_ENC_FIELD(enc_lambda_satd_10); + INIT_ENC_FIELD(enc_lambda_satd_11); + INIT_ENC_FIELD(enc_lambda_satd_12); + INIT_ENC_FIELD(enc_lambda_satd_13); + INIT_ENC_FIELD(enc_lambda_satd_14); + INIT_ENC_FIELD(enc_lambda_satd_15); + INIT_ENC_FIELD(enc_lambda_satd_16); + INIT_ENC_FIELD(enc_lambda_satd_17); + INIT_ENC_FIELD(enc_lambda_satd_18); + INIT_ENC_FIELD(enc_lambda_satd_19); + INIT_ENC_FIELD(enc_lambda_satd_20); + INIT_ENC_FIELD(enc_lambda_satd_21); + INIT_ENC_FIELD(enc_lambda_satd_22); + INIT_ENC_FIELD(enc_lambda_satd_23); + INIT_ENC_FIELD(enc_lambda_satd_24); + INIT_ENC_FIELD(enc_lambda_satd_25); + INIT_ENC_FIELD(enc_lambda_satd_26); + INIT_ENC_FIELD(enc_lambda_satd_27); + INIT_ENC_FIELD(enc_lambda_satd_28); + INIT_ENC_FIELD(enc_lambda_satd_29); + INIT_ENC_FIELD(enc_lambda_satd_30); + INIT_ENC_FIELD(enc_lambda_satd_31); + + INIT_ENC_FIELD(enc_lambda_sse_me_0); + INIT_ENC_FIELD(enc_lambda_sse_me_1); + INIT_ENC_FIELD(enc_lambda_sse_me_2); + INIT_ENC_FIELD(enc_lambda_sse_me_3); + INIT_ENC_FIELD(enc_lambda_sse_me_4); + INIT_ENC_FIELD(enc_lambda_sse_me_5); + INIT_ENC_FIELD(enc_lambda_sse_me_6); + INIT_ENC_FIELD(enc_lambda_sse_me_7); + INIT_ENC_FIELD(enc_lambda_sse_me_8); + INIT_ENC_FIELD(enc_lambda_sse_me_9); + INIT_ENC_FIELD(enc_lambda_sse_me_10); + INIT_ENC_FIELD(enc_lambda_sse_me_11); + INIT_ENC_FIELD(enc_lambda_sse_me_12); + INIT_ENC_FIELD(enc_lambda_sse_me_13); + INIT_ENC_FIELD(enc_lambda_sse_me_14); + INIT_ENC_FIELD(enc_lambda_sse_me_15); + INIT_ENC_FIELD(enc_lambda_sse_me_16); + INIT_ENC_FIELD(enc_lambda_sse_me_17); + INIT_ENC_FIELD(enc_lambda_sse_me_18); + INIT_ENC_FIELD(enc_lambda_sse_me_19); + INIT_ENC_FIELD(enc_lambda_sse_me_20); + INIT_ENC_FIELD(enc_lambda_sse_me_21); + INIT_ENC_FIELD(enc_lambda_sse_me_22); + INIT_ENC_FIELD(enc_lambda_sse_me_23); + INIT_ENC_FIELD(enc_lambda_sse_me_24); + INIT_ENC_FIELD(enc_lambda_sse_me_25); + INIT_ENC_FIELD(enc_lambda_sse_me_26); + INIT_ENC_FIELD(enc_lambda_sse_me_27); + INIT_ENC_FIELD(enc_lambda_sse_me_28); + INIT_ENC_FIELD(enc_lambda_sse_me_29); + INIT_ENC_FIELD(enc_lambda_sse_me_30); + INIT_ENC_FIELD(enc_lambda_sse_me_31); return 0; } @@ -379,6 +940,21 @@ int hantro_regmap_init_enc(struct hantro_dev *vpu) clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); + switch (vpu->core_hw_enc_rev) { + case HANTRO_H1_REV: + hantro_regmap_enc.max_register = 0x300; + field = &h1_field; + break; + case HANTRO_VC8000_REV: + hantro_regmap_enc.max_register = 0x640; + field = &vc8000e_field; + break; + default: + dev_err(vpu->dev, "Encoder revision 0x%x not supported by driver.\n", + vpu->core_hw_enc_rev); + return -ENODEV; + } + vpu->regs_enc = devm_regmap_init_mmio(vpu->dev, enc_base, &hantro_regmap_enc); if (IS_ERR(vpu->regs_enc)) { diff --git a/drivers/staging/media/hantro/hantro_regmap.h b/drivers/staging/media/hantro/hantro_regmap.h index 083c4e92c4bd..549c16f72919 100644 --- a/drivers/staging/media/hantro/hantro_regmap.h +++ b/drivers/staging/media/hantro/hantro_regmap.h @@ -10,6 +10,7 @@ #define HANTRO_REGMAP_H_ #define HANTRO_G1_REV 0x6731 +#define HANTRO_H1_REV 0x4831 #define HANTRO_VC8000_REV 0x8001 #define SWREG(nr) ((nr) << 2) @@ -111,7 +112,181 @@ struct hantro_regmap_fields_dec { }; struct hantro_regmap_fields_enc { - /* TODO: populate encoder fields */ + /* Encoder */ + struct regmap_field *enc_timeout_cycles; + struct regmap_field *enc_timeout_e; + struct regmap_field *enc_mode; + struct regmap_field *enc_stream_mode; + struct regmap_field *enc_enable; + struct regmap_field *enc_pic_type; + struct regmap_field *enc_pic_width; + struct regmap_field *enc_pic_height; + struct regmap_field *enc_burst_len; + struct regmap_field *enc_clk_gate_en; + struct regmap_field *enc_stream_buf_limit; + struct regmap_field *enc_row_len; + struct regmap_field *enc_overfill_r; + struct regmap_field *enc_overfill_b; + struct regmap_field *enc_src_format; + struct regmap_field *enc_init_qp; + struct regmap_field *enc_qp_frac; + struct regmap_field *enc_chroma_qp_offset; + struct regmap_field *enc_deblocking_filter_dis; + struct regmap_field *enc_slice_deblocking_filter_dis; + struct regmap_field *enc_slice_deblocking_filter_override; + struct regmap_field *enc_pps_deblocking_filter_override; + struct regmap_field *enc_slice_alpha_div2; + struct regmap_field *enc_slice_beta_div2; + struct regmap_field *enc_idr_pic_id; + struct regmap_field *enc_nal_ref_idc; + struct regmap_field *enc_pps_id; + struct regmap_field *enc_nal_unit_type; + struct regmap_field *enc_frame_num; + struct regmap_field *enc_min_cb_size; + struct regmap_field *enc_max_cb_size; + struct regmap_field *enc_min_trb_size; + struct regmap_field *enc_max_trb_size; + struct regmap_field *enc_slice_size; + struct regmap_field *enc_nal_size_write; + struct regmap_field *enc_cabac_init_idc; + struct regmap_field *enc_pic_qp; + struct regmap_field *enc_entropy_coding_mode; + struct regmap_field *enc_axi_r_outstanding_num; + struct regmap_field *enc_axi_w_outstanding_num; + struct regmap_field *enc_trans8x8_mode_en; + struct regmap_field *enc_inter4x4_mode; + struct regmap_field *enc_quarter_pixmv_dis; + struct regmap_field *enc_addr_cabac; + struct regmap_field *enc_addr_str; + struct regmap_field *enc_addr_size_table; + struct regmap_field *enc_addr_rec_luma; + struct regmap_field *enc_addr_rec_luma_4n; + struct regmap_field *enc_addr_ref_luma_l0_4n0; + struct regmap_field *enc_addr_rec_chroma; + struct regmap_field *enc_addr_ref_luma; + struct regmap_field *enc_addr_ref_chroma; + struct regmap_field *enc_addr_src_y; + struct regmap_field *enc_addr_src_cb; + struct regmap_field *enc_addr_src_cr; + struct regmap_field *enc_log2_max_pic_order_cnt_lsb; + struct regmap_field *enc_log2_max_frame_num; + struct regmap_field *enc_pic_order_cnt_type; + struct regmap_field *enc_l0_delta_framenum0; + struct regmap_field *enc_l0_used_by_next_pic0; + struct regmap_field *enc_l0_used_by_next_pic1; + + struct regmap_field *enc_lu_stride; + struct regmap_field *enc_cr_stride; + struct regmap_field *enc_ref_lu_stride; + struct regmap_field *enc_ref_ds_lu_stride; + struct regmap_field *enc_ref_cr_stride; + struct regmap_field *enc_ipcm2_left; + struct regmap_field *enc_ipcm2_right; + struct regmap_field *enc_ipcm2_top; + struct regmap_field *enc_ipcm2_bottom; + + struct regmap_field *enc_slice_qp_offset; + struct regmap_field *enc_qp_min; + struct regmap_field *enc_qp_max; + + struct regmap_field *enc_lambda_satd_me_0; + struct regmap_field *enc_lambda_satd_me_1; + struct regmap_field *enc_lambda_satd_me_2; + struct regmap_field *enc_lambda_satd_me_3; + struct regmap_field *enc_lambda_satd_me_4; + struct regmap_field *enc_lambda_satd_me_5; + struct regmap_field *enc_lambda_satd_me_6; + struct regmap_field *enc_lambda_satd_me_7; + struct regmap_field *enc_lambda_satd_me_8; + struct regmap_field *enc_lambda_satd_me_9; + struct regmap_field *enc_lambda_satd_me_10; + struct regmap_field *enc_lambda_satd_me_11; + struct regmap_field *enc_lambda_satd_me_12; + struct regmap_field *enc_lambda_satd_me_13; + struct regmap_field *enc_lambda_satd_me_14; + struct regmap_field *enc_lambda_satd_me_15; + struct regmap_field *enc_lambda_satd_me_16; + struct regmap_field *enc_lambda_satd_me_17; + struct regmap_field *enc_lambda_satd_me_18; + struct regmap_field *enc_lambda_satd_me_19; + struct regmap_field *enc_lambda_satd_me_20; + struct regmap_field *enc_lambda_satd_me_21; + struct regmap_field *enc_lambda_satd_me_22; + struct regmap_field *enc_lambda_satd_me_23; + struct regmap_field *enc_lambda_satd_me_24; + struct regmap_field *enc_lambda_satd_me_25; + struct regmap_field *enc_lambda_satd_me_26; + struct regmap_field *enc_lambda_satd_me_27; + struct regmap_field *enc_lambda_satd_me_28; + struct regmap_field *enc_lambda_satd_me_29; + struct regmap_field *enc_lambda_satd_me_30; + struct regmap_field *enc_lambda_satd_me_31; + + struct regmap_field *enc_lambda_satd_0; + struct regmap_field *enc_lambda_satd_1; + struct regmap_field *enc_lambda_satd_2; + struct regmap_field *enc_lambda_satd_3; + struct regmap_field *enc_lambda_satd_4; + struct regmap_field *enc_lambda_satd_5; + struct regmap_field *enc_lambda_satd_6; + struct regmap_field *enc_lambda_satd_7; + struct regmap_field *enc_lambda_satd_8; + struct regmap_field *enc_lambda_satd_9; + struct regmap_field *enc_lambda_satd_10; + struct regmap_field *enc_lambda_satd_11; + struct regmap_field *enc_lambda_satd_12; + struct regmap_field *enc_lambda_satd_13; + struct regmap_field *enc_lambda_satd_14; + struct regmap_field *enc_lambda_satd_15; + struct regmap_field *enc_lambda_satd_16; + struct regmap_field *enc_lambda_satd_17; + struct regmap_field *enc_lambda_satd_18; + struct regmap_field *enc_lambda_satd_19; + struct regmap_field *enc_lambda_satd_20; + struct regmap_field *enc_lambda_satd_21; + struct regmap_field *enc_lambda_satd_22; + struct regmap_field *enc_lambda_satd_23; + struct regmap_field *enc_lambda_satd_24; + struct regmap_field *enc_lambda_satd_25; + struct regmap_field *enc_lambda_satd_26; + struct regmap_field *enc_lambda_satd_27; + struct regmap_field *enc_lambda_satd_28; + struct regmap_field *enc_lambda_satd_29; + struct regmap_field *enc_lambda_satd_30; + struct regmap_field *enc_lambda_satd_31; + + struct regmap_field *enc_lambda_sse_me_0; + struct regmap_field *enc_lambda_sse_me_1; + struct regmap_field *enc_lambda_sse_me_2; + struct regmap_field *enc_lambda_sse_me_3; + struct regmap_field *enc_lambda_sse_me_4; + struct regmap_field *enc_lambda_sse_me_5; + struct regmap_field *enc_lambda_sse_me_6; + struct regmap_field *enc_lambda_sse_me_7; + struct regmap_field *enc_lambda_sse_me_8; + struct regmap_field *enc_lambda_sse_me_9; + struct regmap_field *enc_lambda_sse_me_10; + struct regmap_field *enc_lambda_sse_me_11; + struct regmap_field *enc_lambda_sse_me_12; + struct regmap_field *enc_lambda_sse_me_13; + struct regmap_field *enc_lambda_sse_me_14; + struct regmap_field *enc_lambda_sse_me_15; + struct regmap_field *enc_lambda_sse_me_16; + struct regmap_field *enc_lambda_sse_me_17; + struct regmap_field *enc_lambda_sse_me_18; + struct regmap_field *enc_lambda_sse_me_19; + struct regmap_field *enc_lambda_sse_me_20; + struct regmap_field *enc_lambda_sse_me_21; + struct regmap_field *enc_lambda_sse_me_22; + struct regmap_field *enc_lambda_sse_me_23; + struct regmap_field *enc_lambda_sse_me_24; + struct regmap_field *enc_lambda_sse_me_25; + struct regmap_field *enc_lambda_sse_me_26; + struct regmap_field *enc_lambda_sse_me_27; + struct regmap_field *enc_lambda_sse_me_28; + struct regmap_field *enc_lambda_sse_me_29; + struct regmap_field *enc_lambda_sse_me_30; + struct regmap_field *enc_lambda_sse_me_31; }; int hantro_regmap_init_dec(struct hantro_dev *vpu);