From patchwork Tue Feb 28 15:11:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94633 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1363474qgi; Tue, 28 Feb 2017 07:11:58 -0800 (PST) X-Received: by 10.237.60.41 with SMTP id t38mr3195719qte.148.1488294718132; Tue, 28 Feb 2017 07:11:58 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id s49si1659905qts.188.2017.02.28.07.11.57; Tue, 28 Feb 2017 07:11:58 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9EB9F636DF; Tue, 28 Feb 2017 15:11:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 6672D636E2; Tue, 28 Feb 2017 15:11:38 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0CBD4636DC; Tue, 28 Feb 2017 15:11:36 +0000 (UTC) Received: from mail-wr0-f182.google.com (mail-wr0-f182.google.com [209.85.128.182]) by lists.linaro.org (Postfix) with ESMTPS id 6E7B1636DC for ; Tue, 28 Feb 2017 15:11:34 +0000 (UTC) Received: by mail-wr0-f182.google.com with SMTP id u108so10883842wrb.3 for ; Tue, 28 Feb 2017 07:11:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c0P2p64u6RO1vgls6qON6Hi7ExyzlbfPrgHNXvjkiZo=; b=YBxD67AXmgBEQQ10sB2CDf6VjKuHLY4tMGSFVLF7GppxZung19Ha6grZpH3hAJuwlu 0N8QP6QWsJihnrluS9XVqfol8Uy82EzU40qBze1OnPaWcMs8YQZd9gFPuWqmiqasD/2H burj66F5UBhBQChnZLLGJXRvOyHfChZXZPJSP5eGqy+osPxRPdgMKG8kdD92Uq7tcKBI UNwHn3PFN9fVyuSjvzKaI5SSQQT47v6qaKFhQvxPRSQT5OuVotI68iPfMK8yVqRq/Tz8 akBSuqv/01D/Byo2XIYy8FXMk7E8UITAzNsK4q15n3an3zydGoUf/a/wnSMEayZRc4rk hDWQ== X-Gm-Message-State: AMke39kJ5G/Fgd3x2DYzqqkm0B6QrJrULmCRKkomo1VqgCTIdAni4UgV5awsMFKZhII6T01Lecs= X-Received: by 10.223.135.43 with SMTP id a40mr2996442wra.197.1488294693547; Tue, 28 Feb 2017 07:11:33 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:32 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:17 +0000 Message-Id: <1488294680-1884-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 1/4] Platforms/AMD/Styx/PlatformSmbiosDxe: don't write to string literals X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Remove the code from PlatformSmbiosDxe that writes to a string literal to turn the string 'L# Cache' into L1/L2/L3, and just emit the three versions instead. This is necessary given that string literals are emitted into .rodata by default, which makes them read-only when strict memory permissions are in effect. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 5ee5d92fdf9c..7548be727849 100644 --- a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -354,17 +354,10 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { CacheTypeUnknown, // System Cache Type CacheAssociativity2Way // Associativity }; -#if (FixedPcdGetBool (PcdIscpSupport)) -CHAR8 *mCacheInfoType7Strings[] = { - "L# Cache", - NULL -}; -#else CHAR8 *mCacheInfoType7Strings[] = { "Cache1", NULL }; -#endif /*********************************************************************** SMBIOS data definition TYPE9 System Slot Information @@ -710,7 +703,7 @@ CacheInfoUpdateSmbiosType7 ( dstType7.SocketDesignation = 1; // "L# Cache" // L1 cache settings - mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache" + mCacheInfoType7Strings[0] = "L1 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -726,7 +719,7 @@ CacheInfoUpdateSmbiosType7 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); // L2 cache settings - mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache" + mCacheInfoType7Strings[0] = "L2 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -742,7 +735,7 @@ CacheInfoUpdateSmbiosType7 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); // L3 cache settings - mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache" + mCacheInfoType7Strings[0] = "L3 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; From patchwork Tue Feb 28 15:11:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94634 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1363910qgi; Tue, 28 Feb 2017 07:12:51 -0800 (PST) X-Received: by 10.233.223.195 with SMTP id t186mr3055402qkf.153.1488294771391; Tue, 28 Feb 2017 07:12:51 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id c27si1676896qta.35.2017.02.28.07.12.50; Tue, 28 Feb 2017 07:12:51 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BCDD3636F8; Tue, 28 Feb 2017 15:12:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1496F636E2; Tue, 28 Feb 2017 15:12:18 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3D83A636E2; Tue, 28 Feb 2017 15:12:02 +0000 (UTC) Received: from mail-wr0-f182.google.com (mail-wr0-f182.google.com [209.85.128.182]) by lists.linaro.org (Postfix) with ESMTPS id 63126636E0 for ; Tue, 28 Feb 2017 15:11:37 +0000 (UTC) Received: by mail-wr0-f182.google.com with SMTP id u48so10909991wrc.0 for ; Tue, 28 Feb 2017 07:11:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fBBWa8rLpetj/Wc3UDXS3Ojs0wSKSLIvjy8ULTkTu9o=; b=MUfEpc/enIygZHTMPOlHPtXe7m2WSFjParFq9QRJuN8BexWUsmtaPfR7Np4Ek9uQu7 44F/3zcVJym6a59Y5fmk+cS4oYILSRtBJD22yl90DoUCwVXRg8rb68QXbBgjnppgMqpB 5w3pchvp1HcSJWwZgBKXG4V5PMPWtQ6dA093HpeiyPAa70dK1KWeUq2278KPiiDCluuL M5/VioOoNjeGnzUjBdz8tq1pxuHMUqQO9758My68PH0TGOlDwm5ueMLTQvepM1oiuSsI 6Fdlet6pcT023P4iKH4tPJ0G1cky5BeQQGUvH11u7DZh9ZXKxsYgRWgLZ/MNJ0xvpRtj 9NoQ== X-Gm-Message-State: AMke39lOGRBrfCYkuBDWjISOD0xc87/LKrtcWlox/i4SpbpcPChzvuXBFV/YSGTBASEylMbeZiU= X-Received: by 10.223.178.239 with SMTP id g102mr2700747wrd.126.1488294696060; Tue, 28 Feb 2017 07:11:36 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:35 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:18 +0000 Message-Id: <1488294680-1884-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 2/4] Platforms/AMD/Styx: constify/staticize all local functions and variables X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Now that we've made a clean spot, let's clean up this module by making everything we can STATIC and/or CONST. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 66 ++++++++++++-------- 1 file changed, 39 insertions(+), 27 deletions(-) diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 7548be727849..53380b311ba7 100644 --- a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -57,15 +57,15 @@ extern EFI_BOOT_SERVICES *gBS; * G L O B A L S *---------------------------------------------------------------------------------------- */ -EFI_SMBIOS_PROTOCOL *mSmbiosProtocol; -AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol; -ISCP_SMBIOS_INFO mSmbiosInfo; +STATIC EFI_SMBIOS_PROTOCOL *mSmbiosProtocol; +STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol; +STATIC ISCP_SMBIOS_INFO mSmbiosInfo; /*********************************************************************** SMBIOS data definition TYPE0 BIOS Information ************************************************************************/ -SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = { +STATIC CONST SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = { { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 }, 1, // Vendor String 2, // BiosVersion String @@ -130,7 +130,7 @@ SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = { 0xFF, // EmbeddedControllerFirmwareMinorRelease }; -CHAR8 *mBIOSInfoType0Strings[] = { +STATIC CHAR8 CONST * CONST mBIOSInfoType0Strings[] = { "edk2.sourceforge.net", // Vendor String __TIME__, // BiosVersion String __DATE__, // BiosReleaseDate String @@ -140,7 +140,7 @@ CHAR8 *mBIOSInfoType0Strings[] = { /*********************************************************************** SMBIOS data definition TYPE1 System Information ************************************************************************/ -SMBIOS_TABLE_TYPE1 mSysInfoType1 = { +STATIC CONST SMBIOS_TABLE_TYPE1 mSysInfoType1 = { { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 }, 1, // Manufacturer String 2, // ProductName String @@ -151,7 +151,7 @@ SMBIOS_TABLE_TYPE1 mSysInfoType1 = { 5, // SKUNumber String 6, // Family String }; -CHAR8 *mSysInfoType1Strings[] = { +STATIC CHAR8 CONST * CONST mSysInfoType1Strings[] = { "AMD", "Seattle", "1.0", @@ -164,7 +164,7 @@ CHAR8 *mSysInfoType1Strings[] = { /*********************************************************************** SMBIOS data definition TYPE2 Board Information ************************************************************************/ -SMBIOS_TABLE_TYPE2 mBoardInfoType2 = { +STATIC CONST SMBIOS_TABLE_TYPE2 mBoardInfoType2 = { { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 }, 1, // Manufacturer String 2, // ProductName String @@ -185,7 +185,7 @@ SMBIOS_TABLE_TYPE2 mBoardInfoType2 = { 0, // NumberOfContainedObjectHandles; { 0 } // ContainedObjectHandles[1]; }; -CHAR8 *mBoardInfoType2Strings[] = { +STATIC CHAR8 CONST * CONST mBoardInfoType2Strings[] = { "AMD", "Seattle", "1.0", @@ -198,7 +198,7 @@ CHAR8 *mBoardInfoType2Strings[] = { /*********************************************************************** SMBIOS data definition TYPE3 Enclosure Information ************************************************************************/ -SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = { +STATIC CONST SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = { { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 }, 1, // Manufacturer String MiscChassisTypeLapTop, // Type; @@ -216,7 +216,7 @@ SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = { 0, // ContainedElementRecordLength; { { 0 } }, // ContainedElements[1]; }; -CHAR8 *mEnclosureInfoType3Strings[] = { +STATIC CHAR8 CONST * CONST mEnclosureInfoType3Strings[] = { "AMD", "1.0", "Chassis Board Serial#", @@ -227,7 +227,7 @@ CHAR8 *mEnclosureInfoType3Strings[] = { /*********************************************************************** SMBIOS data definition TYPE4 Processor Information ************************************************************************/ -SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { +STATIC SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0}, 1, // Socket String ProcessorOther, // ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA. @@ -306,7 +306,7 @@ SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { ProcessorFamilyARM, // ARM Processor Family; }; -CHAR8 *mProcessorInfoType4Strings[] = { +STATIC CHAR8 CONST * CONST mProcessorInfoType4Strings[] = { "Socket", "ARM", #ifdef ARM_CPU_AARCH64 @@ -323,7 +323,7 @@ CHAR8 *mProcessorInfoType4Strings[] = { /*********************************************************************** SMBIOS data definition TYPE7 Cache Information ************************************************************************/ -SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { +STATIC SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, 1, // SocketDesignation String 0x018A, // Cache Configuration @@ -354,7 +354,7 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { CacheTypeUnknown, // System Cache Type CacheAssociativity2Way // Associativity }; -CHAR8 *mCacheInfoType7Strings[] = { +STATIC CHAR8 CONST *mCacheInfoType7Strings[] = { "Cache1", NULL }; @@ -362,7 +362,7 @@ CHAR8 *mCacheInfoType7Strings[] = { /*********************************************************************** SMBIOS data definition TYPE9 System Slot Information ************************************************************************/ -SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = { +STATIC CONST SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = { { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 }, 1, // SlotDesignation String SlotTypeOther, // SlotType; ///< The enumeration value from MISC_SLOT_TYPE. @@ -390,7 +390,7 @@ SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = { 0, // BusNum; 0, // DevFuncNum; }; -CHAR8 *mSysSlotInfoType9Strings[] = { +STATIC CHAR8 CONST * CONST mSysSlotInfoType9Strings[] = { "SD Card", NULL }; @@ -398,7 +398,7 @@ CHAR8 *mSysSlotInfoType9Strings[] = { /*********************************************************************** SMBIOS data definition TYPE16 Physical Memory ArrayInformation ************************************************************************/ -SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { +STATIC SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 }, MemoryArrayLocationSystemBoard, // Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION. MemoryArrayUseSystemMemory, // Use; ///< The enumeration value from MEMORY_ARRAY_USE. @@ -408,14 +408,14 @@ SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { 1, // NumberOfMemoryDevices; 0x3fffffffffffffffULL, // ExtendedMaximumCapacity; }; -CHAR8 *mPhyMemArrayInfoType16Strings[] = { +STATIC CHAR8 CONST * CONST mPhyMemArrayInfoType16Strings[] = { NULL }; /*********************************************************************** SMBIOS data definition TYPE17 Memory Device Information ************************************************************************/ -SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { +STATIC SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 }, 0, // MemoryArrayHandle; 0xFFFE, // MemoryErrorInformationHandle; @@ -456,9 +456,9 @@ SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { }; #if (FixedPcdGetBool (PcdIscpSupport)) -CHAR8 *mMemDevInfoType17Strings[ 7 ] = {0}; +STATIC CHAR8 CONST *mMemDevInfoType17Strings[ 7 ] = {0}; #else -CHAR8 *mMemDevInfoType17Strings[] = { +STATIC CHAR8 CONST * CONST mMemDevInfoType17Strings[] = { "OS Virtual Memory", "malloc", "OSV", @@ -469,7 +469,7 @@ CHAR8 *mMemDevInfoType17Strings[] = { /*********************************************************************** SMBIOS data definition TYPE19 Memory Array Mapped Address Information ************************************************************************/ -SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { +STATIC SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 }, 0x80000000, // StartingAddress; 0xbfffffff, // EndingAddress; @@ -478,20 +478,20 @@ SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { 0, // ExtendedStartingAddress; 0, // ExtendedEndingAddress; }; -CHAR8 *mMemArrMapInfoType19Strings[] = { +STATIC CHAR8 CONST * CONST mMemArrMapInfoType19Strings[] = { NULL }; /*********************************************************************** SMBIOS data definition TYPE32 Boot Information ************************************************************************/ -SMBIOS_TABLE_TYPE32 mBootInfoType32 = { +STATIC CONST SMBIOS_TABLE_TYPE32 mBootInfoType32 = { { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 }, { 0, 0, 0, 0, 0, 0 }, // Reserved[6]; BootInformationStatusNoError // BootStatus }; -CHAR8 *mBootInfoType32Strings[] = { +STATIC CHAR8 CONST * CONST mBootInfoType32Strings[] = { NULL }; @@ -526,11 +526,12 @@ CHAR8 *mBootInfoType32Strings[] = { NULL is OK. **/ +STATIC EFI_STATUS EFIAPI LogSmbiosData ( IN EFI_SMBIOS_TABLE_HEADER *Template, - IN CHAR8 **StringPack + IN CONST CHAR8* CONST *StringPack ) { EFI_STATUS Status; @@ -593,6 +594,7 @@ LogSmbiosData ( /*********************************************************************** SMBIOS data update TYPE0 BIOS Information ************************************************************************/ +STATIC VOID BIOSInfoUpdateSmbiosType0 ( VOID @@ -604,6 +606,7 @@ BIOSInfoUpdateSmbiosType0 ( /*********************************************************************** SMBIOS data update TYPE1 System Information ************************************************************************/ +STATIC VOID SysInfoUpdateSmbiosType1 ( VOID @@ -615,6 +618,7 @@ SysInfoUpdateSmbiosType1 ( /*********************************************************************** SMBIOS data update TYPE2 Board Information ************************************************************************/ +STATIC VOID BoardInfoUpdateSmbiosType2 ( VOID @@ -626,6 +630,7 @@ BoardInfoUpdateSmbiosType2 ( /*********************************************************************** SMBIOS data update TYPE3 Enclosure Information ************************************************************************/ +STATIC VOID EnclosureInfoUpdateSmbiosType3 ( VOID @@ -637,6 +642,7 @@ EnclosureInfoUpdateSmbiosType3 ( /*********************************************************************** SMBIOS data update TYPE4 Processor Information ************************************************************************/ +STATIC VOID ProcessorInfoUpdateSmbiosType4 ( VOID @@ -688,6 +694,7 @@ ProcessorInfoUpdateSmbiosType4 ( /*********************************************************************** SMBIOS data update TYPE7 Cache Information ************************************************************************/ +STATIC VOID CacheInfoUpdateSmbiosType7 ( VOID @@ -757,6 +764,7 @@ CacheInfoUpdateSmbiosType7 ( /*********************************************************************** SMBIOS data update TYPE9 System Slot Information ************************************************************************/ +STATIC VOID SysSlotInfoUpdateSmbiosType9 ( VOID @@ -768,6 +776,7 @@ SysSlotInfoUpdateSmbiosType9 ( /*********************************************************************** SMBIOS data update TYPE16 Physical Memory Array Information ************************************************************************/ +STATIC VOID PhyMemArrayInfoUpdateSmbiosType16 ( VOID @@ -790,6 +799,7 @@ PhyMemArrayInfoUpdateSmbiosType16 ( /*********************************************************************** SMBIOS data update TYPE17 Memory Device Information ************************************************************************/ +STATIC VOID MemDevInfoUpdatedstType17 ( VOID @@ -872,6 +882,7 @@ MemDevInfoUpdatedstType17 ( /*********************************************************************** SMBIOS data update TYPE19 Memory Array Map Information ************************************************************************/ +STATIC VOID MemArrMapInfoUpdateSmbiosType19 ( VOID @@ -897,6 +908,7 @@ MemArrMapInfoUpdateSmbiosType19 ( /*********************************************************************** SMBIOS data update TYPE32 Boot Information ************************************************************************/ +STATIC VOID BootInfoUpdateSmbiosType32 ( VOID From patchwork Tue Feb 28 15:11:19 2017 Content-Type: text/plain; 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[54.225.227.206]) by mx.google.com with ESMTP id s68si1670123qkf.118.2017.02.28.07.13.55; Tue, 28 Feb 2017 07:13:56 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8B2E5636FE; Tue, 28 Feb 2017 15:13:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CE857636DE; Tue, 28 Feb 2017 15:12:32 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 43273636EA; Tue, 28 Feb 2017 15:12:26 +0000 (UTC) Received: from mail-wr0-f177.google.com (mail-wr0-f177.google.com [209.85.128.177]) by lists.linaro.org (Postfix) with ESMTPS id 390C0636E5 for ; Tue, 28 Feb 2017 15:11:39 +0000 (UTC) Received: by mail-wr0-f177.google.com with SMTP id g10so10889542wrg.2 for ; Tue, 28 Feb 2017 07:11:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=43Ujz+XhbYj6K39qNA6KFJkJIWeS/j5NOgEep48o88k=; b=XklGU+8GCwps6H+vLb7W6bfdprdcCTaP6YgTC4yXOMm8Iq3teWjpScJR6REcDsnobY +MTTxmnS/65pnsMdoqIulb0Ypr1poh4L9rOB6RMxQBRmKcvgBylyqxzFWGsij7e2ZB+9 cQ6K9jLDVrzjO02jFzwBN44kf2CQmqZZNFEFcEKdjsylcYFUkII2CvpGJ9AA7p5gmYyL qlf/Z22Yy/ISUd6z4gjS3TL7xsFl6zJXPIjaLNQEEIianX4eNYA85s8lb6gl/z1SrXtg U/7eU/qDtT9njwwdqJhLwxvHJADQ+mEa2JFpe1vE3MBZKVt6okkHgIsAB1tGfPAnqEVt mtZA== X-Gm-Message-State: AMke39ls2PkfZbmE4XblL6Ig19d2Iz1wifGbZprOi7De9Mumex9JA4h0s4d44ZSV7FFtYOxUq7w= X-Received: by 10.223.138.250 with SMTP id z55mr3032485wrz.130.1488294698294; Tue, 28 Feb 2017 07:11:38 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:37 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:19 +0000 Message-Id: <1488294680-1884-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 3/4] Platforms/AMD/Overdrive: enable strict memory permission policy X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Implement a strict separation between writable and executable memory, by enabling the new core features that - map PE/COFF code and data sections with either executable or writable permissions, but never both; - map all other regions with the XN attributes set. Note that the former requires 4 KB section alignment, which is not the default when using the tiny code model, so set the section alignment explicitly both for DEBUG and RELEASE builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index a236836db691..dcab8fb43cec 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -273,6 +273,9 @@ DEFINE DO_KCS = 1 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 +[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -440,6 +443,19 @@ DEFINE DO_KCS = 1 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 + !if $(DO_PSCI) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE !else From patchwork Tue Feb 28 15:11:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94636 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1364460qgi; Tue, 28 Feb 2017 07:14:09 -0800 (PST) X-Received: by 10.200.38.72 with SMTP id v8mr3334095qtv.27.1488294849268; Tue, 28 Feb 2017 07:14:09 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j135si1667082qke.129.2017.02.28.07.14.08; Tue, 28 Feb 2017 07:14:09 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C37CB63706; Tue, 28 Feb 2017 15:14:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1AE14636E5; Tue, 28 Feb 2017 15:12:37 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7AEE8636DC; Tue, 28 Feb 2017 15:12:27 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.linaro.org (Postfix) with ESMTPS id 66065636DC for ; Tue, 28 Feb 2017 15:11:41 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id v77so14158220wmv.0 for ; Tue, 28 Feb 2017 07:11:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rYGZDOZm7tZQKVAqta8r3XRO8vkYBPURhkgBVGYHlr0=; b=UN/MvxVwdJrqAUveQGVEW9gd2FWZZHK/lxAE2fRBTXHgVIfZJvgKY4Nm4tK24CdUdy 57dId2wPu/1tVfQpxz1pHZwVTK0WLk951Y9z1eP7Kqzrxiy9tU+R9sUodZzeeUP5WFl6 sLWTQpTMxSwUTb44pLkWR3u0NOQsqji4Y1XnVx1EX1zBGoiFJLTIQPhT3KA1UBolRmhz MQhRw6vqEl8I7wPsXS1J4JfPRIak8w/oJ9lKw9Pbxy2aSjAcKrdvd47oDfwIxTv0PYV+ UWkVvXwk8dyjBC97QexrWLLs4Ew4MK54nzGSmJgxoIzIE6rcYNtmuRQ/qi0wyPWmMGxz ytMQ== X-Gm-Message-State: AMke39kGOyVqd7h8BbanAl+S+xLyDbz/xWLLUua8ShGXDOkrh+gC0RGZMDzp4wTmpwJxAPmIhdk= X-Received: by 10.28.144.135 with SMTP id s129mr2874143wmd.18.1488294700451; Tue, 28 Feb 2017 07:11:40 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:39 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:20 +0000 Message-Id: <1488294680-1884-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 4/4] Platforms/AMD/Cello: enable strict memory permission policy X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Implement a strict separation between writable and executable memory, by enabling the new core features that - map PE/COFF code and data sections with either executable or writable permissions, but never both; - map all other regions with the XN attributes set. Note that the former requires 4 KB section alignment, which is not the default when using the tiny code model, so set the section alignment explicitly both for DEBUG and RELEASE builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index d7e1a538f863..cb8b6cd0d822 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -266,6 +266,9 @@ DEFINE DO_KCS = 0 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 +[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -430,6 +433,19 @@ DEFINE DO_KCS = 0 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 + gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE