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[198.145.21.10]) by mx.google.com with ESMTPS id g14si3081748plj.470.2017.12.08.09.31.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YWJKNwDp; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 450A1221EA0C0; Fri, 8 Dec 2017 09:27:08 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 50E5F221EA0BA for ; Fri, 8 Dec 2017 09:27:06 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id h1so11466107wre.12 for ; Fri, 08 Dec 2017 09:31:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OGlj+CBDTrqLnoWMQoK/IB25mtOzOz3/jcn1k2i/9bo=; b=YWJKNwDpSiE+JTbDF6F8Cnao3JFnN5netbUl9GrEtMZNihl34sPwPstckgHKh6repu LAbfqk6x/tbbHCycwW3U9XShaW84IJTpBahmYV2OqJav/8plajDImQEhPI8u7Zec4/Lo VSVrgXlKJdsMU02n1F07Ao4ry3AHm5v8hE2b4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OGlj+CBDTrqLnoWMQoK/IB25mtOzOz3/jcn1k2i/9bo=; b=YpstPAJ2cANEUxDZS3WaQMKU7jThXyZyNRLpTXy0p3APAAzhuyc9VJNIE1aLSL3llA heeXSWAGbFo0b2HqGctyx/aR2kxPsU+uwMIzlylGtYL8+jVpd8ZMBlxoBCIZJEoMnJhS zPzLk19MC3CQNHL4ky8HQdno0gUcFROeZ/vmPjmReHX75qbstGEc8R2JGHBydAZvKIfZ itYHoe3T5rXc033WGBs3lHOBmuIq3c+WPibxWL4mVH2yRk2UriiU+nzYT54LJBgJlE45 661SyTrPgiaSwvwfcU7uOSR6xp94/NM+OzOAjXEQFOzmEYU3O+HiIcLO9Wz37nx34FC7 UNWw== X-Gm-Message-State: AJaThX7JfNcZtOr7qQ+rU8PsppVN8d5TXoN6oSFME72w8Iw69gjNVEAD 3lW3Pz1ks2JLz6KQ+iVsFBxpHoGUWh8= X-Received: by 10.223.150.175 with SMTP id u44mr29060174wrb.115.1512754299105; Fri, 08 Dec 2017 09:31:39 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id q15sm8904685wra.91.2017.12.08.09.31.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 17:31:24 +0000 Message-Id: <20171208173128.28485-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171208173128.28485-1-ard.biesheuvel@linaro.org> References: <20171208173128.28485-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/5] ArmPlatformPkg: introduce LcdHwLib library class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add the declaration and include file for the new LcdHwLib library class, which will allow us to abstract away from platform variations in the LCD graphics output driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd [ardb: add NULL implementation as well and add it to ArmPlatformPkg.dsc] Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/ArmPlatformPkg.dsc | 1 + ArmPlatformPkg/Include/Library/LcdHwLib.h | 68 ++++++++++++++++++ ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c | 75 ++++++++++++++++++++ ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf | 28 ++++++++ 5 files changed, 173 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 6a7bbc02d011..b33b6e630d85 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -33,6 +33,7 @@ [Includes.common] [LibraryClasses] ArmPlatformLib|Include/Library/ArmPlatformLib.h + LcdHwLib|Include/Library/LcdHwLib.h LcdPlatformLib|Include/Library/LcdPlatformLib.h NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h PL011UartLib|Include/Library/PL011UartLib.h diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc index c3a8c257cb02..9dd64b472acf 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dsc +++ b/ArmPlatformPkg/ArmPlatformPkg.dsc @@ -101,6 +101,7 @@ [Components.common] ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.inf ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.inf ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf diff --git a/ArmPlatformPkg/Include/Library/LcdHwLib.h b/ArmPlatformPkg/Include/Library/LcdHwLib.h new file mode 100644 index 000000000000..0c0480862aea --- /dev/null +++ b/ArmPlatformPkg/Include/Library/LcdHwLib.h @@ -0,0 +1,68 @@ +/** @file LcdHwLib.h + + This file contains interface functions for LcdHwLib of ArmPlatformPkg + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef LCD_HW_LIB_H_ +#define LCD_HW_LIB_H_ + +#include + +/** + Check for presence of display + + @retval EFI_SUCCESS Platform implements display. + @retval EFI_NOT_FOUND Display not found on the platform. + +**/ +EFI_STATUS +LcdIdentify ( + VOID + ); + +/** + Initialize display. + + @param FrameBaseAddress Address of the frame buffer. + @retval EFI_SUCCESS Display initialization success. + @retval !(EFI_SUCCESS) Display initialization failure. + +**/ +EFI_STATUS +LcdInitialize ( + EFI_PHYSICAL_ADDRESS FrameBaseAddress + ); + +/** + Set requested mode of the display. + + @param ModeNumber Display mode number. + @retval EFI_SUCCESS Display set mode success. + @retval EFI_DEVICE_ERROR If mode not found/supported. + +**/ +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ); + +/** + De-initializes the display. +**/ +VOID +LcdShutdown ( + VOID + ); + +#endif /* LCD_HW_LIB_H_ */ diff --git a/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c new file mode 100644 index 000000000000..2d31b5183c95 --- /dev/null +++ b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c @@ -0,0 +1,75 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +/** + Check for presence of display + + @retval EFI_SUCCESS Platform implements display. + @retval EFI_NOT_FOUND Display not found on the platform. + +**/ +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize display. + + @param FrameBaseAddress Address of the frame buffer. + @retval EFI_SUCCESS Display initialization success. + @retval !(EFI_SUCCESS) Display initialization failure. + +**/ +EFI_STATUS +LcdInitialize ( + EFI_PHYSICAL_ADDRESS FrameBaseAddress + ) +{ + return EFI_SUCCESS; +} + +/** + Set requested mode of the display. + + @param ModeNumber Display mode number. + @retval EFI_SUCCESS Display set mode success. + @retval EFI_DEVICE_ERROR If mode not found/supported. + +**/ +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + return EFI_SUCCESS; +} + +/** + De-initializes the display. +**/ +VOID +LcdShutdown ( + VOID + ) +{ +} diff --git a/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf new file mode 100644 index 000000000000..d556bed65548 --- /dev/null +++ b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LcdHwNullLib + FILE_GUID = bb1fde98-1de2-410e-8850-fdcb8e67ebc0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = LcdHwLib + +[Sources] + LcdHwNullLib.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec From patchwork Fri Dec 8 17:31:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121222 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp928908qgn; Fri, 8 Dec 2017 09:31:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMbtvTPZsHtWUsuLyVjhBIY8Ml2+3+qVVTvfUFKjAE2tqHELB/xSwGRDM27SJ7Qa+n3C7JhC X-Received: by 10.101.70.70 with SMTP id k6mr30093911pgr.292.1512754305553; Fri, 08 Dec 2017 09:31:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512754305; cv=none; d=google.com; s=arc-20160816; b=C34NSHZoTiB96F8qrqKPAwjeXkQws2p6Trb4PClubq6+WbzcaLNJqszGGdCFBSbnUZ asz/kxYQKZvkftomtrc2vT1ZLhpQeD4gLYfUfr0XHviTLGDrymczWIkfD/noRlqFUvgM ydUgO+2scXqGlNkhFLpGVgwMTKlSqaYBB5IWarkoJCu2r6InRIERZ7kQXFVvh3cM/ulT 61eScZDpczuknpw/o3WAKHbAhGfKCmibh04J9fjm1KatPfgfnwzo88UdiVHKYEAPdxcp 0pKCCSR+e+Xam0Vi+aHyi4E893jRPUSlo6KpU/XbdHkg29bEzpEPm9Zdw9drI6GfFd30 wG+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=xSG6fxir7ghrB/yhkfkY+mPLY6MPGYtynRcTtFf2+D0=; b=bgxQTj7Ke/Kw0MsS3tTMckTu03uav3jjFTcVNSTp8qd2jB+7m7+yviLS9UkbXip3Pc DD8nCrQ52yHN7FK/R5HF7CGQUvEgquqF8gdVTjJyjCXRE6RNdmdGUU30DnSNVgR7EvKd aok6ssz560dUtD8J+Is4NwvSMqf05x/JtHABW+40Zs5p77JBG25oDY1FryBC4OCEJUEA DUeddv57/lf7paa8Zm2t6HjB68NlmYaF5OwKc/FJHb9BagonIP3JRlBOdOt8cFefe5pv acbqVebdA54YgpFrjI4RoI4oGPCBQaTlOqVdH7NddrQ8Lh3q4jkW39Ux8Q4XejttWyTZ 26pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L1Z9TP0Z; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o12si5813354plg.494.2017.12.08.09.31.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L1Z9TP0Z; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8F3EA221EA0BF; Fri, 8 Dec 2017 09:27:10 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::232; helo=mail-wr0-x232.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x232.google.com (mail-wr0-x232.google.com [IPv6:2a00:1450:400c:c0c::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1696F2218E951 for ; Fri, 8 Dec 2017 09:27:08 -0800 (PST) Received: by mail-wr0-x232.google.com with SMTP id k61so11491055wrc.4 for ; Fri, 08 Dec 2017 09:31:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VzJPVu4lDVayls0DM83XqoWaUJ7cAtGntSajL+TSdW0=; b=L1Z9TP0ZXbyn8p73yHGY3sy/zBw1ysMsxsXSZPsYD4NPpmJO8i7k/sYo/FpdkC8oPz gqcMKwDeZcSyTXQJyBXleTPoy9pk4BtQ9tZIVtrBwqSg8Y9P8s/Klrv5QOVLI0KLl+Pq BPJFsjeRmIPQpHizS5pK1ATozb5P7avfV78+U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VzJPVu4lDVayls0DM83XqoWaUJ7cAtGntSajL+TSdW0=; b=IKeWEYipSa0pUYHjY3N/0Djy6zQW5HSdZpZ7SgQAv4yZBOwRDsHHqh1jkjtXu111zx 5nFD2+0OaTzHM3+ja7qz2uyeE08QeTqgYL1GITOWnx8s5gaYJ4my32BXU4VZ7OBbSbQF w3WLt3VsTamC0PQird2sqmEkgOsv95KmZTmbeqUiANUjPJxVgEUHs5Qg8wyYPz7VXVkK hsEI80sPwEregHCh62/Vzc7iJ7E9Af2V7SQcu1ydpUcA5CMEOnucJOcsx0kVwqvBD1jk IRUJxX9lZLhCHWvf3zAJW8a+9lE+kBQDt9gZyN1mNmpgsB/wI3jwz+UYaD9wEKg8OAUD Yyog== X-Gm-Message-State: AJaThX6D/t1ZUq0vBEdrPT8Ty6LYF6pp7uqls9PnDwh6HBijRAy0YWHk aEn9hFsQ89uHDNGtQ4Bf93HZd8ceH9E= X-Received: by 10.223.143.66 with SMTP id p60mr24892288wrb.99.1512754301631; Fri, 08 Dec 2017 09:31:41 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id q15sm8904685wra.91.2017.12.08.09.31.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:40 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 17:31:25 +0000 Message-Id: <20171208173128.28485-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171208173128.28485-1-ard.biesheuvel@linaro.org> References: <20171208173128.28485-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 2/5] ArmPlatformPkg: implement LcdHwLib for PL111 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Convert the PL111 specific code of LcdGraphicsOutputDxe into a LcdHwlib implementation that we will wire up later into LcdGraphicsOutputDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 126 +++++++++++++++++ ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h | 149 ++++++++++++++++++++ ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf | 40 ++++++ 3 files changed, 315 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c new file mode 100644 index 000000000000..9b4a02045ab7 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -0,0 +1,126 @@ +/** @file PL111Lcd.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include + +#include "PL111Lcd.h" + +/********************************************************************** + * + * This file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", + PL111_REG_CLCD_PERIPH_ID_0)); + + // Check if this is a PL111 + if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && + (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { + return EFI_SUCCESS; + } + return EFI_NOT_FOUND; +} + +EFI_STATUS +LcdInitialize ( + IN EFI_PHYSICAL_ADDRESS VramBaseAddress + ) +{ + // Define start of the VRAM. This never changes for any graphics mode + MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); + MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer + + // Disable all interrupts from the PL111 + MmioWrite32(PL111_REG_LCD_IMSC, 0); + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 HRes; + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VRes; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; + UINT32 LcdControl; + LCD_BPP LcdBpp; + + // Set the video mode timings and other relevant information + Status = LcdPlatformGetTimings (ModeNumber, + &HRes,&HSync,&HBackPorch,&HFrontPorch, + &VRes,&VSync,&VBackPorch,&VFrontPorch); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + // Disable the CLCD_LcdEn bit + LcdControl = MmioRead32( PL111_REG_LCD_CONTROL); + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); + + // Set Timings + MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); + + // PL111_REG_LCD_CONTROL + LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + // Turn on power to the LCD Panel + LcdControl |= PL111_CTRL_LCD_PWR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + return EFI_SUCCESS; +} + +VOID +LcdShutdown ( + VOID + ) +{ + // Disable the controller + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); +} diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h new file mode 100644 index 000000000000..18e28af805f6 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h @@ -0,0 +1,149 @@ +/** @file PL111Lcd.h + + Copyright (c) 2011, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#ifndef _PL111LCD_H__ +#define _PL111LCD_H__ + +/********************************************************************** + * + * This header file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +// Controller Register Offsets +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) + +// Identification Register Offsets +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) + +#define PL111_CLCD_PERIPH_ID_0 0x11 +#define PL111_CLCD_PERIPH_ID_1 0x11 +#define PL111_CLCD_PERIPH_ID_2 0x04 +#define PL111_CLCD_PERIPH_ID_3 0x00 +#define PL111_CLCD_P_CELL_ID_0 0x0D +#define PL111_CLCD_P_CELL_ID_1 0xF0 +#define PL111_CLCD_P_CELL_ID_2 0x05 +#define PL111_CLCD_P_CELL_ID_3 0xB1 + +/**********************************************************************/ + +// Register components (register bits) + +// This should make life easier to program specific settings in the different registers +// by simplifying the setting up of the individual bits of each register +// and then assembling the final register value. + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) + +// Register: PL111_REG_LCD_TIMING_1 +#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_SHIFT_PCD_HI 27 +#define PL111_BIT_SHIFT_BCD 26 +#define PL111_BIT_SHIFT_CPL 16 +#define PL111_BIT_SHIFT_IOE 14 +#define PL111_BIT_SHIFT_IPC 13 +#define PL111_BIT_SHIFT_IHS 12 +#define PL111_BIT_SHIFT_IVS 11 +#define PL111_BIT_SHIFT_ACB 6 +#define PL111_BIT_SHIFT_CLKSEL 5 +#define PL111_BIT_SHIFT_PCD_LO 0 + +#define PL111_BCD (1 << 26) +#define PL111_IPC (1 << 13) +#define PL111_IHS (1 << 12) +#define PL111_IVS (1 << 11) + +#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_SHIFT_LEE 16 +#define PL111_BIT_SHIFT_LED 0 + +#define PL111_CTRL_WATERMARK (1 << 16) +#define PL111_CTRL_LCD_V_COMP (1 << 12) +#define PL111_CTRL_LCD_PWR (1 << 11) +#define PL111_CTRL_BEPO (1 << 10) +#define PL111_CTRL_BEBO (1 << 9) +#define PL111_CTRL_BGR (1 << 8) +#define PL111_CTRL_LCD_DUAL (1 << 7) +#define PL111_CTRL_LCD_MONO_8 (1 << 6) +#define PL111_CTRL_LCD_TFT (1 << 5) +#define PL111_CTRL_LCD_BW (1 << 4) +#define PL111_CTRL_LCD_1BPP (0 << 1) +#define PL111_CTRL_LCD_2BPP (1 << 1) +#define PL111_CTRL_LCD_4BPP (2 << 1) +#define PL111_CTRL_LCD_8BPP (3 << 1) +#define PL111_CTRL_LCD_16BPP (4 << 1) +#define PL111_CTRL_LCD_24BPP (5 << 1) +#define PL111_CTRL_LCD_16BPP_565 (6 << 1) +#define PL111_CTRL_LCD_12BPP_444 (7 << 1) +#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) +#define PL111_CTRL_LCD_EN 1 + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) +#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) + +// Register: PL111_REG_LCD_TIMING_1 +#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) +#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_MASK_PCD_HI 0xF8000000 +#define PL111_BIT_MASK_BCD 0x04000000 +#define PL111_BIT_MASK_CPL 0x03FF0000 +#define PL111_BIT_MASK_IOE 0x00004000 +#define PL111_BIT_MASK_IPC 0x00002000 +#define PL111_BIT_MASK_IHS 0x00001000 +#define PL111_BIT_MASK_IVS 0x00000800 +#define PL111_BIT_MASK_ACB 0x000007C0 +#define PL111_BIT_MASK_CLKSEL 0x00000020 +#define PL111_BIT_MASK_PCD_LO 0x0000001F + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_MASK_LEE 0x00010000 +#define PL111_BIT_MASK_LED 0x0000007F + +#endif /* _PL111LCD_H__ */ diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf new file mode 100644 index 000000000000..40db77eb079e --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf @@ -0,0 +1,40 @@ +#/** @file PL111Lcd.inf +# +# Component description file for PL111Lcd module +# +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PL111Lcd + FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = LcdHwLib + +[Sources.common] + PL111Lcd.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + IoLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase From patchwork Fri Dec 8 17:31:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121223 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp928965qgn; Fri, 8 Dec 2017 09:31:48 -0800 (PST) X-Google-Smtp-Source: AGs4zMbhwmDDwrHkGYQ+jbGnVuZqlqiWsDpZCpC366Md0FU4FOUj6sund/Zan00zELGj3Qjv3Zm1 X-Received: by 10.99.117.90 with SMTP id f26mr30489082pgn.201.1512754308780; Fri, 08 Dec 2017 09:31:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512754308; cv=none; d=google.com; s=arc-20160816; b=eXnVJXfVrMNkp/2i9AYLrF19ZfL2uS1/ewFEDqjzBj3sbFCxf4xf7aF+/zjOdPAad7 +LnrLXsww4Lt91ZP7DaFY4uHUvfg8Z/DwjuwfKQDEr0BpNC8oxeeH+6T52+fTTETlSGd QGq52A6BIGBCRCMmQupPHmiGUkEmjBNUBloG2VX5UGkFEv4lAOO/7F1P2WG12p8Fi/hO vePZ3OtFgdKpLv3idF9iR811r1efzDdsf7KhOJOzN8OJs3x+cX3A271I9agDAZT4kyNR d5UntokLtU6TncfUTtvYATfGjra9mpZT03npH9RaRSvHWFxux0emdbOqkkGykH8YISSF PJlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=Xyt8xPryiTTuBvsq8Eg+DJSy5JKZjPe0SGzENfBz3Ng=; b=uXQcIGDVW8mVgxU9w0Al4qdG1GJA2hYFPtPeW8zM5gYyEz77qlTjUm/02YRly7bd6k LslVNXLCJKLkI6XxZkD8c0ZgJ3rgTJYnSDFF0DYbcFBZfoAG7/mePFHXGZ3A+9MIsCnl T6lTXArIRi6MlzeKINYoWAoqzuAuLO9LnDI9h83/n49Rzz4nSEzTci59qDWoD5LOSYeR C3EX6sQwyuekbudd5OtZLTnXNb0MVn9R1ZGMo9sqmYZyOd5CFR/2iMryWCGm0AD1NLEI BfhB35XnB2ewNmCB831FwK5hb5QaO1tG9BF1jceEKZ2i0KAgedTqrI6j0iHTyp1J7ale 4JhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PiOg98qX; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 20si6483552pfp.408.2017.12.08.09.31.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PiOg98qX; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CADB8221EA0C5; Fri, 8 Dec 2017 09:27:13 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::236; helo=mail-wr0-x236.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x236.google.com (mail-wr0-x236.google.com [IPv6:2a00:1450:400c:c0c::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B4F772218E951 for ; Fri, 8 Dec 2017 09:27:11 -0800 (PST) Received: by mail-wr0-x236.google.com with SMTP id x49so11469731wrb.13 for ; Fri, 08 Dec 2017 09:31:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m9sJYt0r8BuVeOBEJGZXRfwWuU6Xatiga80sGeip4h0=; b=PiOg98qXLSIcK54DtqmwlFNm8R9YcdhZvaWBVW+p5T8oc4Tt6K4asnCvjs3CZGyqnh nnQa4H7jzhghJ104KZX2VacG0smCiw6fCltjC1GxUy1e7dPSw73Sp35oht80Q0YkF/9Y vmCY1V68lemhvzUC0AjRvaNA6MzW8T72QNgDM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m9sJYt0r8BuVeOBEJGZXRfwWuU6Xatiga80sGeip4h0=; b=Savelf0dSUmG3mZ6f2bxk3FBrIhmYRA+ZmX7KlEgKxtI35JNVoXI7BwJo5K5/LiNH/ aX9KlwBXApHYiMK9A5kLnz3uY3zgl4r1Y+OugtNdT2qp0ZGdffWWH3JWO42DVIIt47Ch t9gJjP6aadd+hCREuXbLQU+T0dds/JKlobS9zBIXH4Md8hEFmT8ziYYeJwN7LgdjzF77 HxIxSPNSz+x5WbhRoMeSDGjqSyXi8hUKSnr9bKNsIES12rJaSgIthEa/i/ryoy84q0Qw oilzb8rcDOFvgXFtzSSaUXXp/lm6Yh5Zgm6yUD+RA74MmSxYbpK47K+CCE0z9aJVTkaM lpug== X-Gm-Message-State: AJaThX7ZEW49tDWUI5KBnh++FO/fZzMdVoj6n+2wqZUwzCc3AfsE23/o R+oXa+OhkWXsqqCzWYODdWArMGHAC68= X-Received: by 10.223.189.5 with SMTP id j5mr25941671wrh.172.1512754304312; Fri, 08 Dec 2017 09:31:44 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id q15sm8904685wra.91.2017.12.08.09.31.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:43 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 17:31:26 +0000 Message-Id: <20171208173128.28485-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171208173128.28485-1-ard.biesheuvel@linaro.org> References: <20171208173128.28485-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 3/5] ArmPlatformPkg: implement LcdHwLib for HdLcd X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Convert the HdLcd specific code of LcdGraphicsOutputDxe into a LcdHwlib implementation that we will wire up later into LcdGraphicsOutputDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 158 ++++++++++++++++++++ ArmPlatformPkg/Library/HdLcd/HdLcd.h | 89 +++++++++++ ArmPlatformPkg/Library/HdLcd/HdLcd.inf | 42 ++++++ 3 files changed, 289 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/HdLcd/HdLcd.c new file mode 100644 index 000000000000..24efb68f23e3 --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -0,0 +1,158 @@ +/** @file Lcd.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +#include "HdLcd.h" + +/********************************************************************** + * + * This file contains all the bits of the Lcd that are + * platform independent. + * + **********************************************************************/ + +STATIC +UINTN +GetBytesPerPixel ( + IN LCD_BPP Bpp + ) +{ + switch(Bpp) { + case LCD_BITS_PER_PIXEL_24: + return 4; + + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_12_444: + return 2; + + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + return 1; + + default: + return 0; + } +} + +EFI_STATUS +LcdInitialize ( + IN EFI_PHYSICAL_ADDRESS VramBaseAddress + ) +{ + // Disable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + + // Disable all interrupts + MmioWrite32(HDLCD_REG_INT_MASK, 0); + + // Define start of the VRAM. This never changes for any graphics mode + MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); + + // Setup various registers that never change + MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); + MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); + MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL); + MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); + MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); + MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 HRes; + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VRes; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; + UINT32 BytesPerPixel; + LCD_BPP LcdBpp; + + + // Set the video mode timings and other relevant information + Status = LcdPlatformGetTimings (ModeNumber, + &HRes,&HSync,&HBackPorch,&HFrontPorch, + &VRes,&VSync,&VBackPorch,&VFrontPorch); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + BytesPerPixel = GetBytesPerPixel(LcdBpp); + + // Disable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + + // Update the frame buffer information with the new settings + MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); + MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); + MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); + + // Set the vertical timing information + MmioWrite32(HDLCD_REG_V_SYNC, VSync); + MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); + MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); + MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + + // Set the horizontal timing information + MmioWrite32(HDLCD_REG_H_SYNC, HSync); + MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); + MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); + MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + + // Enable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); + + return EFI_SUCCESS; +} + +VOID +LcdShutdown ( + VOID + ) +{ + // Disable the controller + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); +} + +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/HdLcd/HdLcd.h new file mode 100644 index 000000000000..6df97a9dfee6 --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -0,0 +1,89 @@ +/** @file HDLcd.h + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#ifndef _HDLCD_H_ +#define _HDLCD_H_ + +// +// HDLCD Controller Register Offsets +// + +#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000) +#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010) +#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014) +#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018) +#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C) +#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100) +#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104) +#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108) +#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C) +#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110) +#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200) +#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204) +#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208) +#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C) +#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210) +#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214) +#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218) +#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C) +#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220) +#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230) +#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240) +#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244) +#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248) +#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C) + + +// +// HDLCD Values of registers +// + +// HDLCD Interrupt mask, clear and status register +#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */ +#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ +#define HDLCD_SYNC BIT2 /* Vertical sync */ +#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */ + +// CLCD_CONTROL Control register +#define HDLCD_DISABLE 0 +#define HDLCD_ENABLE BIT0 + +// Bus Options +#define HDLCD_BURST_1 BIT0 +#define HDLCD_BURST_2 BIT1 +#define HDLCD_BURST_4 BIT2 +#define HDLCD_BURST_8 BIT3 +#define HDLCD_BURST_16 BIT4 + +// Polarities - HIGH +#define HDLCD_VSYNC_HIGH BIT0 +#define HDLCD_HSYNC_HIGH BIT1 +#define HDLCD_DATEN_HIGH BIT2 +#define HDLCD_DATA_HIGH BIT3 +#define HDLCD_PXCLK_HIGH BIT4 +// Polarities - LOW (for completion and for ease of understanding the hardware settings) +#define HDLCD_VSYNC_LOW 0 +#define HDLCD_HSYNC_LOW 0 +#define HDLCD_DATEN_LOW 0 +#define HDLCD_DATA_LOW 0 +#define HDLCD_PXCLK_LOW 0 + +// Pixel Format +#define HDLCD_LITTLE_ENDIAN (0 << 31) +#define HDLCD_BIG_ENDIAN (1 << 31) + +// Number of bytes per pixel +#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) + +#endif /* _HDLCD_H_ */ diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.inf b/ArmPlatformPkg/Library/HdLcd/HdLcd.inf new file mode 100644 index 000000000000..67aad05d210b --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Component description file for HDLCD module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = HdLcd + FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = LcdHwLib + +[Sources.common] + HdLcd.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + UefiLib + BaseLib + DebugLib + IoLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase From patchwork Fri Dec 8 17:31:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121224 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp929122qgn; Fri, 8 Dec 2017 09:31:51 -0800 (PST) X-Google-Smtp-Source: AGs4zMaOFLw3muC9CPQWhDcRURauOxjbSEOVI0rsjrUIWT/080ZYYsUrFlwr3wqtobtqt5cw0xP6 X-Received: by 10.99.107.7 with SMTP id g7mr29774284pgc.387.1512754311015; Fri, 08 Dec 2017 09:31:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512754311; cv=none; d=google.com; s=arc-20160816; b=qvAJpb8QOXmQR4Qsqpk5BGLSLGF2a6Y0jhvpWbcpd0laBDSTWiMHibgwsuarz3SiQB eMkN2OjGKdDpdOrfP/wAcvYhtiWzaSKUD9mk9UATjlauRnhUvvUUTc145j4i5RFtX2x9 k3bacBJCKJa5uYZVyB6C7wU2KT4EqKNMasoe5KyD+2BsP6bVtk+QbdhgMpLmi+A+booa tO+ntDuCSEf4SHiS7/kBdQdPoGnzCgLFwV+ALwrczoB4Ck31+MYt72gdMTqQw9NaV1ND 2ocI8AR4pdl1jHc2/AwKrRquqWpiJJyNFbuphfwJpD3qOzSwmq929bhPxKKKN2P0amyA VUGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=YR/+x6Y00XDsk65yHEb5iecNK34hEdbf40jx6eh94mU=; b=repTEC5YaVJwtDWxsOAVyWl9n+OW03LWlxJwp34JlePINH0M/TvG+NyktjfqLUcxRH ZkC98uqu9yZhmiaJ1WIl7akRrLV16x83brcMnLPfN362UUAlfvcwoRzRuVNaAEC03xhW xZ13/hV38Db/MD7oS0SK0pqMiN3JHNzy25EbqotlYP1Ac1hcPs3MF+78zTorSPpLCH06 fNOykpEl5ZupmaMCNQcTYYM4aDTCPQJxX54gEVLP3EhnoMsXBv/zwXRUjjjnoAmN89wX +bJeu5IfpWD48BDZS21feFEajN7tSjIeV+lRqeRncnabCOQWN6MNxwWKTUYPX9ov2sDI /fpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RBXFSU7E; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id c1si5293285plk.35.2017.12.08.09.31.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RBXFSU7E; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0CBEA221EA0DC; Fri, 8 Dec 2017 09:27:16 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 943F32218E951 for ; Fri, 8 Dec 2017 09:27:14 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id y82so5287496wmg.1 for ; Fri, 08 Dec 2017 09:31:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oLv9/Izi2Kd7alY49SxRoVvVTC0Zscw4On7DYHqcDSU=; b=RBXFSU7EUg3n3apd7B8hc7mi7ZZpmUHCX+Q8E8TSzVZC1/iYkDiLSyy+LYUeCGe0Z/ BXVHWRHd2rFztS3HRqUKJPm4Oq0tQC8DGuZ/9XeIH4n/7amNkkoewUraHZR5zu/D7FpO ud5DUYaVRoP9VGezullJ8kYhP9mlZoGwROXzw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oLv9/Izi2Kd7alY49SxRoVvVTC0Zscw4On7DYHqcDSU=; b=fgaK25XsAyP6ZqF/0hjGXrYa2tPdUW8UMQl+r5NhfuunhIjylmNWAmQLfJaR5/XviJ 3FrLRK190KTaIDE2G7FxPgFHVP39zwMsN5cUAxvComPpb1HUbltKn/g7s4Wp8fktMEiX dTuV4siLzXB650NA2WrsvD8sp4YoErE3zhigSqe7M5UZE6aG55N7N1D5t8S6qzKA2Lan oQH/YdtX6sacd19dKhk09fvrvuWLMoaGAEec+aHVz4irdX/XufdOqIu2kAXV4CmlBhZq nizCZzbya1SHVul15u5k3EUv5pOqp6DqBB/WMdfeM4g6nP4RqpoL/VYcathun/xzBuQy g5rQ== X-Gm-Message-State: AKGB3mIlBdqryDU6zu90IWxZG6p2ApNF3ig6Bwiy9b26gX+VLZPWEFiS xMDSgmQSaBNgy047nAudYs9faUNJJfk= X-Received: by 10.28.27.206 with SMTP id b197mr4819587wmb.96.1512754307427; Fri, 08 Dec 2017 09:31:47 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id q15sm8904685wra.91.2017.12.08.09.31.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:45 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 17:31:27 +0000 Message-Id: <20171208173128.28485-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171208173128.28485-1-ard.biesheuvel@linaro.org> References: <20171208173128.28485-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 4/5] ArmPlatformPkg: create hw-agnostic LcdGraphicsOutputDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Create a new LcdGraphicsOutputDxe driver from the existing sources that takes its hardware abstractions from a LcdHwLib library instance rather than from a .c file linked directly. All we need is a new .inf file, and a minimal tweak to LcdGraphicsOutputDxe.h to reuse the LcdHwlib prototypes rather than open code them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd [ardb: add it to ArmPlatformPkg.dsc so we can build test it standalone] Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dsc | 2 + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h | 21 +------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf | 54 ++++++++++++++++++++ 3 files changed, 57 insertions(+), 20 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc index 9dd64b472acf..69ae9b67bc79 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dsc +++ b/ArmPlatformPkg/ArmPlatformPkg.dsc @@ -53,6 +53,7 @@ [LibraryClasses.common] DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + LcdHwLib|ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf LcdPlatformLib|ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.inf LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf @@ -93,6 +94,7 @@ [LibraryClasses.common.SEC] [Components.common] ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h index 8856b79901b6..b66efd34561f 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -105,24 +106,4 @@ InitializeDisplay ( IN LCD_INSTANCE* Instance ); -EFI_STATUS -LcdIdentify ( - VOID -); - -EFI_STATUS -LcdInitialize ( - EFI_PHYSICAL_ADDRESS VramBaseAddress -); - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber -); - -VOID -LcdShutdown ( - VOID -); - #endif /* __ARM_VE_GRAPHICS_DXE_H__ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf new file mode 100644 index 000000000000..e6424475f79d --- /dev/null +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -0,0 +1,54 @@ +#/** @file +# +# Component description file for LcdGraphicsOutputDxe module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LcdGraphicsOutputDxe + FILE_GUID = 89464DAE-8DAA-41FE-A4C8-40D2175AF1E9 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = LcdGraphicsOutputDxeInitialize + +[Sources.common] + LcdGraphicsOutputDxe.c + LcdGraphicsOutputBlt.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseLib + BaseMemoryLib + DebugLib + LcdHwLib + LcdPlatformLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + +[FeaturePcd] + gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices + +[Depex] + TRUE From patchwork Fri Dec 8 17:31:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 121225 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp929212qgn; Fri, 8 Dec 2017 09:31:55 -0800 (PST) X-Google-Smtp-Source: AGs4zMbEnjvvtryl5TiPD7TSsIDd1I0LbSWZYV7UZDLo7ZYbkN3/Bz9mvBcnDMAK+yzA9209eIct X-Received: by 10.84.245.149 with SMTP id j21mr31280937pll.315.1512754315257; Fri, 08 Dec 2017 09:31:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512754315; cv=none; d=google.com; s=arc-20160816; b=SSLlrKBYWwVD8N/M69qf452KsjyePv5QI+vch5K1EUw/XHFnChyLernjyWFnMdTCcb hgfiy7mtuEerP7lq7UeBWDm8kyWTSGR+W0qQKfyXXG3TSxByqQeoAOVTzQup0B1Gr07q qWmRvAYv8NXfZF7vPP+Lido6nPY5AqLPurs3/XUan+MB8wspeOyBHylXUF/BJ1vlDdv+ JejhuOM8xwsok4f1h3Lm+a1YevODGepplNGIAUtSZnU2cmedaQu73zu89xfICmWAtiFY Cj7/fzXMBRQg8GBLVBoH3is6CHQrznFAMBhMMe4qi1I72sFSPh0E2zTl19BmUrPL8mQQ fxgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=2WQKqFfiYqvRyQis4ALgK/Gj6xsVM8SN4bQjt5Qb2yc=; b=fYNYpx4iIX4EDESHfbQKCjmPJjqIBDhpkMi71SKtlk1eVIRB1a5uT6QSXs3r7WJk3q Ufb4qRfsd4xwHCvBf8M1nUug0PuFBpfsEIL4zk7+LQAC/hS32T4ElfOfmCuSrWTqcKnj aWZK0Id5IlKvJ90xPYSzx4V155wTnHLkW8x6mH9lJC6PYryMemkLsAD+4hFAue+9IIWc XH+Bj6MMD48y5zaeL7WE1g60sglBOJ8Cpa/z5MJrp8G+cAoIeSOhOl3SAFExe/YZE8sM aUsd/eGZFMt4apIPDQegskeRk4I70Pjx009KjodfniWPJNRGg8AdDZvC+KL2SNjnx/G+ ubYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DwAkIvng; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id p16si4078624pgu.525.2017.12.08.09.31.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DwAkIvng; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 489EA2220AFA4; Fri, 8 Dec 2017 09:27:20 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 502DF2220AFA2 for ; Fri, 8 Dec 2017 09:27:19 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id g75so4491992wme.0 for ; Fri, 08 Dec 2017 09:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=irkauIh5hQPvliWcfm+tSFCpNbP1NVnoKDHaLRsLQ8w=; b=DwAkIvngG9E+sHhrFRE1oCTFTvmUs6zPKUb6ETIdgr5ZAfSVFXzGtGh9u3KHU+nB/R 9eo7zyXGXjqQ8YI5hj2Y6lq4ICG+4WbNOioSMyRNw5itAyD6DMApWsldPWdrRTmM9p5i 4f6RPFGG4yUcZLc2g3gRYohv7/OgrT12PlRAU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=irkauIh5hQPvliWcfm+tSFCpNbP1NVnoKDHaLRsLQ8w=; b=aS2KKSASgQbOYpX2avWPgFeZfTqI0556Autnt/3AufICsQAFweMohn0aRWrRsNFzUN FJ2OgzpjYDwy6lIY21IdhRP2lcMEPiJ1EgEj0iA0kN3Mvhzk2ISrhYiQrqRHeWWmGZpD UqXbUJPnkGGmSXYzSa3TLsiHPVP5Pt81uY+RLg3yyWiDGpmh2WYyqwBRbBAY+UZlTaQe OhNxFSmu2Vxw26np/F+olykYa8M2KTrTVSh5vXwAMk3n4lijNx3J2+NgZHEI0kmKPzK6 4kMjiCZT62XlCbmLpZEsnkGIx2W2/NHVN9NFDvefOsf17ej8EVchJl+6ZTfe9wLHbfzs g/zw== X-Gm-Message-State: AKGB3mJZeQVGZVu9M4+tnN2AAKHnQviKPKCjG/eq+aVw5nO0C7sA7Za4 yHWyl8FIDGKTnSilySS0/uWSrdzzhD0= X-Received: by 10.28.54.207 with SMTP id y76mr4978734wmh.94.1512754311788; Fri, 08 Dec 2017 09:31:51 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id q15sm8904685wra.91.2017.12.08.09.31.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Dec 2017 09:31:49 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 17:31:28 +0000 Message-Id: <20171208173128.28485-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171208173128.28485-1-ard.biesheuvel@linaro.org> References: <20171208173128.28485-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 5/5] ArmPlatformPkg: remove old PL111/HdLcd driver code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Now that LcdGraphicsOutputDxe has been refactored, remove the old code that is no longer used. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dsc | 2 - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c | 132 ----------------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h | 89 ------------ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf | 62 -------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c | 125 ---------------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h | 149 -------------------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf | 58 -------- 7 files changed, 617 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc index 69ae9b67bc79..82adb9ef8891 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dsc +++ b/ArmPlatformPkg/ArmPlatformPkg.dsc @@ -93,9 +93,7 @@ [LibraryClasses.common.SEC] PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf [Components.common] - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf - ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c deleted file mode 100644 index f5d7b53905fb..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ /dev/null @@ -1,132 +0,0 @@ -/** @file Lcd.c - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include - -#include "HdLcd.h" -#include "LcdGraphicsOutputDxe.h" - -/********************************************************************** - * - * This file contains all the bits of the Lcd that are - * platform independent. - * - **********************************************************************/ - -EFI_STATUS -LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress - ) -{ - // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); - - // Disable all interrupts - MmioWrite32(HDLCD_REG_INT_MASK, 0); - - // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); - - // Setup various registers that never change - MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); - MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); - MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL); - MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; - - - // Set the video mode timings and other relevant information - Status = LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - BytesPerPixel = GetBytesPerPixel(LcdBpp); - - // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); - - // Update the frame buffer information with the new settings - MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); - - // Set the vertical timing information - MmioWrite32(HDLCD_REG_V_SYNC, VSync); - MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); - - // Set the horizontal timing information - MmioWrite32(HDLCD_REG_H_SYNC, HSync); - MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); - - // Enable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); - - return EFI_SUCCESS; -} - -VOID -LcdShutdown ( - VOID - ) -{ - // Disable the controller - MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); -} - -EFI_STATUS -LcdIdentify ( - VOID - ) -{ - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h deleted file mode 100644 index 6df97a9dfee6..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file HDLcd.h - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - **/ - -#ifndef _HDLCD_H_ -#define _HDLCD_H_ - -// -// HDLCD Controller Register Offsets -// - -#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000) -#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010) -#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014) -#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018) -#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C) -#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100) -#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104) -#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108) -#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C) -#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110) -#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200) -#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204) -#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208) -#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C) -#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210) -#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214) -#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218) -#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C) -#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220) -#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230) -#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240) -#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244) -#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248) -#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C) - - -// -// HDLCD Values of registers -// - -// HDLCD Interrupt mask, clear and status register -#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */ -#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ -#define HDLCD_SYNC BIT2 /* Vertical sync */ -#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */ - -// CLCD_CONTROL Control register -#define HDLCD_DISABLE 0 -#define HDLCD_ENABLE BIT0 - -// Bus Options -#define HDLCD_BURST_1 BIT0 -#define HDLCD_BURST_2 BIT1 -#define HDLCD_BURST_4 BIT2 -#define HDLCD_BURST_8 BIT3 -#define HDLCD_BURST_16 BIT4 - -// Polarities - HIGH -#define HDLCD_VSYNC_HIGH BIT0 -#define HDLCD_HSYNC_HIGH BIT1 -#define HDLCD_DATEN_HIGH BIT2 -#define HDLCD_DATA_HIGH BIT3 -#define HDLCD_PXCLK_HIGH BIT4 -// Polarities - LOW (for completion and for ease of understanding the hardware settings) -#define HDLCD_VSYNC_LOW 0 -#define HDLCD_HSYNC_LOW 0 -#define HDLCD_DATEN_LOW 0 -#define HDLCD_DATA_LOW 0 -#define HDLCD_PXCLK_LOW 0 - -// Pixel Format -#define HDLCD_LITTLE_ENDIAN (0 << 31) -#define HDLCD_BIG_ENDIAN (1 << 31) - -// Number of bytes per pixel -#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) - -#endif /* _HDLCD_H_ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf deleted file mode 100644 index 896fc588b275..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf +++ /dev/null @@ -1,62 +0,0 @@ -#/** @file -# -# Component description file for HDLCD module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = HdLcdGraphicsDxe - FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = LcdGraphicsOutputDxeInitialize - -[Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c - HdLcd.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - ArmLib - UefiLib - BaseLib - DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib - IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid # Produced - gEfiEdidDiscoveredProtocolGuid # Produced - gEfiEdidActiveProtocolGuid # Produced - gEfiEdidOverrideProtocolGuid # Produced - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase - -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c deleted file mode 100644 index a9ce60c5b0a6..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ /dev/null @@ -1,125 +0,0 @@ -/** @file PL111Lcd.c - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -#include "LcdGraphicsOutputDxe.h" -#include "PL111Lcd.h" - -/********************************************************************** - * - * This file contains all the bits of the PL111 that are - * platform independent. - * - **********************************************************************/ - -EFI_STATUS -LcdIdentify ( - VOID - ) -{ - DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", - PL111_REG_CLCD_PERIPH_ID_0)); - - // Check if this is a PL111 - if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && - MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && - (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && - MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { - return EFI_SUCCESS; - } - return EFI_NOT_FOUND; -} - -EFI_STATUS -LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress - ) -{ - // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); - MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer - - // Disable all interrupts from the PL111 - MmioWrite32(PL111_REG_LCD_IMSC, 0); - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 LcdControl; - LCD_BPP LcdBpp; - - // Set the video mode timings and other relevant information - Status = LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - // Disable the CLCD_LcdEn bit - LcdControl = MmioRead32( PL111_REG_LCD_CONTROL); - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); - - // Set Timings - MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); - - // PL111_REG_LCD_CONTROL - LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); - - // Turn on power to the LCD Panel - LcdControl |= PL111_CTRL_LCD_PWR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); - - return EFI_SUCCESS; -} - -VOID -LcdShutdown ( - VOID - ) -{ - // Disable the controller - MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); -} diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h deleted file mode 100644 index 18e28af805f6..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h +++ /dev/null @@ -1,149 +0,0 @@ -/** @file PL111Lcd.h - - Copyright (c) 2011, ARM Ltd. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - **/ - -#ifndef _PL111LCD_H__ -#define _PL111LCD_H__ - -/********************************************************************** - * - * This header file contains all the bits of the PL111 that are - * platform independent. - * - **********************************************************************/ - -// Controller Register Offsets -#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) -#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) -#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) -#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) -#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) -#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) -#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) -#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) -#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) -#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) -#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) -#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) -#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) -#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) - -// Identification Register Offsets -#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) -#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) -#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) -#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) -#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) -#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) -#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) -#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) - -#define PL111_CLCD_PERIPH_ID_0 0x11 -#define PL111_CLCD_PERIPH_ID_1 0x11 -#define PL111_CLCD_PERIPH_ID_2 0x04 -#define PL111_CLCD_PERIPH_ID_3 0x00 -#define PL111_CLCD_P_CELL_ID_0 0x0D -#define PL111_CLCD_P_CELL_ID_1 0xF0 -#define PL111_CLCD_P_CELL_ID_2 0x05 -#define PL111_CLCD_P_CELL_ID_3 0xB1 - -/**********************************************************************/ - -// Register components (register bits) - -// This should make life easier to program specific settings in the different registers -// by simplifying the setting up of the individual bits of each register -// and then assembling the final register value. - -/**********************************************************************/ - -// Register: PL111_REG_LCD_TIMING_0 -#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) - -// Register: PL111_REG_LCD_TIMING_1 -#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) - -// Register: PL111_REG_LCD_TIMING_2 -#define PL111_BIT_SHIFT_PCD_HI 27 -#define PL111_BIT_SHIFT_BCD 26 -#define PL111_BIT_SHIFT_CPL 16 -#define PL111_BIT_SHIFT_IOE 14 -#define PL111_BIT_SHIFT_IPC 13 -#define PL111_BIT_SHIFT_IHS 12 -#define PL111_BIT_SHIFT_IVS 11 -#define PL111_BIT_SHIFT_ACB 6 -#define PL111_BIT_SHIFT_CLKSEL 5 -#define PL111_BIT_SHIFT_PCD_LO 0 - -#define PL111_BCD (1 << 26) -#define PL111_IPC (1 << 13) -#define PL111_IHS (1 << 12) -#define PL111_IVS (1 << 11) - -#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) - -// Register: PL111_REG_LCD_TIMING_3 -#define PL111_BIT_SHIFT_LEE 16 -#define PL111_BIT_SHIFT_LED 0 - -#define PL111_CTRL_WATERMARK (1 << 16) -#define PL111_CTRL_LCD_V_COMP (1 << 12) -#define PL111_CTRL_LCD_PWR (1 << 11) -#define PL111_CTRL_BEPO (1 << 10) -#define PL111_CTRL_BEBO (1 << 9) -#define PL111_CTRL_BGR (1 << 8) -#define PL111_CTRL_LCD_DUAL (1 << 7) -#define PL111_CTRL_LCD_MONO_8 (1 << 6) -#define PL111_CTRL_LCD_TFT (1 << 5) -#define PL111_CTRL_LCD_BW (1 << 4) -#define PL111_CTRL_LCD_1BPP (0 << 1) -#define PL111_CTRL_LCD_2BPP (1 << 1) -#define PL111_CTRL_LCD_4BPP (2 << 1) -#define PL111_CTRL_LCD_8BPP (3 << 1) -#define PL111_CTRL_LCD_16BPP (4 << 1) -#define PL111_CTRL_LCD_24BPP (5 << 1) -#define PL111_CTRL_LCD_16BPP_565 (6 << 1) -#define PL111_CTRL_LCD_12BPP_444 (7 << 1) -#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) -#define PL111_CTRL_LCD_EN 1 - -/**********************************************************************/ - -// Register: PL111_REG_LCD_TIMING_0 -#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) -#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) -#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) -#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) - -// Register: PL111_REG_LCD_TIMING_1 -#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) -#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) -#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) -#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) - -// Register: PL111_REG_LCD_TIMING_2 -#define PL111_BIT_MASK_PCD_HI 0xF8000000 -#define PL111_BIT_MASK_BCD 0x04000000 -#define PL111_BIT_MASK_CPL 0x03FF0000 -#define PL111_BIT_MASK_IOE 0x00004000 -#define PL111_BIT_MASK_IPC 0x00002000 -#define PL111_BIT_MASK_IHS 0x00001000 -#define PL111_BIT_MASK_IVS 0x00000800 -#define PL111_BIT_MASK_ACB 0x000007C0 -#define PL111_BIT_MASK_CLKSEL 0x00000020 -#define PL111_BIT_MASK_PCD_LO 0x0000001F - -// Register: PL111_REG_LCD_TIMING_3 -#define PL111_BIT_MASK_LEE 0x00010000 -#define PL111_BIT_MASK_LED 0x0000007F - -#endif /* _PL111LCD_H__ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf deleted file mode 100644 index 39e42bcbab2a..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf +++ /dev/null @@ -1,58 +0,0 @@ -#/** @file -# -# Component description file for PL111LcdGraphicsOutputDxe module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PL111LcdGraphicsDxe - FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = LcdGraphicsOutputDxeInitialize - -[Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c - PL111Lcd.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - ArmLib - UefiLib - BaseLib - DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib - IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase - -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid