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[23.128.96.18]) by mx.google.com with ESMTP id f2si834335edn.26.2020.09.28.08.18.53; Mon, 28 Sep 2020 08:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726420AbgI1PSx (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:53 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14321 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726621AbgI1PSx (ORCPT ); Mon, 28 Sep 2020 11:18:53 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BE5F65DC023556F0FCCF; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:10 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Date: Mon, 28 Sep 2020 23:13:05 +0800 Message-ID: <20200928151324.2134-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. All Hi6220 dedicated controllers are grouped into subdirectory "hi3620". All HiPxx dedicated controllers are grouped into subdirectory "hipxx" Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 + .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++ .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++ .../controller/hisilicon,hi6220-sramctrl.txt | 16 ++ .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++ .../controller/hisilicon,hip01-sysctrl.txt | 19 ++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 + .../controller/hisilicon,hip04-fabric.txt | 5 + .../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++ .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 + .../controller/hisilicon,peri-subctrl.txt | 16 ++ .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++ .../bindings/arm/hisilicon/hisilicon.txt | 262 --------------------- 16 files changed, 235 insertions(+), 262 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt new file mode 100644 index 000000000000000..ceffac537671668 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt @@ -0,0 +1,8 @@ +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt new file mode 100644 index 000000000000000..4d1c6abf03f6f97 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 DSA sub system controller + +Required properties: +- compatible : "hisilicon,dsa-subctrl", "syscon"; +- reg : Register address and size + +The DSA sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt new file mode 100644 index 000000000000000..0d5282f4670658d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt @@ -0,0 +1,21 @@ +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt new file mode 100644 index 000000000000000..5a723c1d45f4a17 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt new file mode 100644 index 000000000000000..dcfdcbcb6455771 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt new file mode 100644 index 000000000000000..972842f07b5a2ce --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt new file mode 100644 index 000000000000000..086b7acccc5edc4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt @@ -0,0 +1,16 @@ +Hisilicon Hi6220 SRAM controller + +Required properties: +- compatible : "hisilicon,hi6220-sramctrl", "syscon" +- reg : Register address and size + +Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several +SRAM banks for power management, modem, security, etc. Further, use "syscon" +managing the common sram which can be shared by multiple modules. + +Example: + /*for Hi6220*/ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt new file mode 100644 index 000000000000000..07e318eda254f52 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt new file mode 100644 index 000000000000000..db2dfdce799db91 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt new file mode 100644 index 000000000000000..b0d53333f4fdae1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt @@ -0,0 +1,9 @@ +Bootwrapper boot method (software protocol on SMP): + +Required Properties: +- compatible: "hisilicon,hip04-bootwrapper"; +- boot-method: Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt new file mode 100644 index 000000000000000..40453d02f2024bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt @@ -0,0 +1,5 @@ +Fabric: + +Required Properties: +- compatible: "hisilicon,hip04-fabric"; +- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt new file mode 100644 index 000000000000000..1ef086bda81a3f5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 PCIe-SAS sub system controller + +Required properties: +- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; +- reg : Register address and size + +The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt new file mode 100644 index 000000000000000..deec777bc3a850a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt @@ -0,0 +1,13 @@ +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt new file mode 100644 index 000000000000000..b96c2896078b914 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt @@ -0,0 +1,16 @@ +Hisilicon HiP05/HiP06 PERI sub system controller + +Required properties: +- compatible : "hisilicon,peri-subctrl", "syscon"; +- reg : Register address and size + +The PERI sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. The peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt new file mode 100644 index 000000000000000..963f7f1ca7a2f0c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt @@ -0,0 +1,25 @@ +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-offset : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-offset : offset in sysctrl for notifying cpu0 when resume +- reboot-offset : offset in sysctrl for system reboot + +Example: + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..ffe760a636b5e7f 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -55,265 +55,3 @@ Required root node properties: HiP07 D05 Board Required root node properties: - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Mon Sep 28 15:13:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313667 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393818ilg; Mon, 28 Sep 2020 08:18:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7p/ooHDlnyWAiEwWMBOhurMy08qeT2D6FEXr6vTmLcZGnBi1dn+Y80AJSZkIZZaQKDeIY X-Received: by 2002:a17:906:a207:: with SMTP id r7mr2193164ejy.32.1601306312967; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306312; cv=none; d=google.com; s=arc-20160816; b=TUDuaMSCbHdFMd5n1YauC/kQJ8OUJviFd+ltykdz99FewOxUK9JruL24Mu4G8aWLh7 6hbDb9ZIIfLfQvamOk1NRR0XS3t5jldcJyS8KT54BSmfhlAu8VU7nDgTVbzj9SEkRl2B SXXkwx+GCFDVpdx4aSXHbgx/wOaM2hxMLiir+lJm4eb6iEs05IahZbMk9BkNXK0yPIsZ goUPuK0sSw6zaUITSQ1YtthBPnOwkFBtXck31XDdf7UBD8mAbIZHAKRepzrx+Ez7yDRx PYM785e8aIPmi8/szCHKybtQXbSbgkapNyTmGxFDfXy647ojnJiL7v+xvqZX2ZYRz1AJ a/ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=FXfRMj0AJwcKOcKMgYaSQk+g4kesZw806JW2F+bJxdI=; b=AzcpN0A0HJpnjziaG+hAGmMmGl7og2Qb8Bmz7mmxwodWjHTnMMedsdrVhsp1vtSHY0 RIFoKW4Dc3EHKJhmnX71ISofQN/ZVvxS3EX9re9EHDglwTa6T+ACFLDuCDExPIC674QU yoxWZB7UOdDAfKYlaQrakuYmxyt+Z/LLWhTOC9ESqipVPLfCTg2T7QT7BvINq9ijXVFL dHYhvG1BuOdpi92iS3rzxozOsv5gPmm+RNxf4GBWvDOUw5hlXN/yNZzMCLKKo+ik/p4D T896Izt8js8+yieNG/Nmh5pARdiR8WwTxJK3DJ0xBIm/vA4jZjaQw3zc4Ep/fi3zdT32 03Tg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.32; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726876AbgI1PSa (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:30 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14316 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726420AbgI1PR3 (ORCPT ); Mon, 28 Sep 2020 11:17:29 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id ACD45155813EB3A581B5; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:10 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Date: Mon, 28 Sep 2020 23:13:06 +0800 Message-ID: <20200928151324.2134-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/hisilicon.txt | 57 -------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml -- 1.8.3 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index ffe760a636b5e7f..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,57 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3670 SoC -Required root node properties: - - compatible = "hisilicon,hi3670"; - -HiKey970 Board -Required root node properties: - - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000000000..6d17309c7c84308 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 based boards. + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 based boards. + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 based boards. + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 based boards. + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 based boards. + items: + - const: hisilicon,hip01-ca9x2 + - const: hisilicon,hip01 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 +... 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[23.128.96.18]) by mx.google.com with ESMTP id f2si834335edn.26.2020.09.28.08.18.37; Mon, 28 Sep 2020 08:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726614AbgI1PR3 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14317 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726424AbgI1PR0 (ORCPT ); Mon, 28 Sep 2020 11:17:26 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B64F0E4EC2F8D1B921FD; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:11 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Date: Mon, 28 Sep 2020 23:13:07 +0800 Message-ID: <20200928151324.2134-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++ 1 file changed, 4 insertions(+) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml index 6d17309c7c84308..3337eebc61da812 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -59,4 +59,8 @@ properties: - description: HiP07 D05 Board items: - const: hisilicon,hip07-d05 + + - description: SD5203 Board + items: + - const: hisilicon,sd5203 ... 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[23.128.96.18]) by mx.google.com with ESMTP id k19si859451ejg.563.2020.09.28.08.17.25; Mon, 28 Sep 2020 08:17:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726466AbgI1PRY (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:24 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14318 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726461AbgI1PRY (ORCPT ); Mon, 28 Sep 2020 11:17:24 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A32B21FF84AB1D6B345B; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:11 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 04/20] ARM: hisi: add support for SD5203 SoC Date: Mon, 28 Sep 2020 23:13:08 +0800 Message-ID: <20200928151324.2134-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif From patchwork Mon Sep 28 15:13:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313666 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393813ilg; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiE2bww+U5Z4mled0iUswFOgoDKCFjwZEgOIQLvs+u0j+uOUGXeAnWVBM+P8bDO+cYdGJ6 X-Received: by 2002:a05:6402:1a48:: with SMTP id bf8mr2294150edb.298.1601306312552; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306312; cv=none; d=google.com; s=arc-20160816; b=RDwSHi96XGQJRpzJ8xrJDysSX9GSDp/9os7StXvIH10V/23bw8S2ENaJrxDCHk3P2j PNkptEg7uCt8xZYBnINAQCprCcmGwoEJWN1XaTYrpJfsByiFcUItc0n4yuremByEImu6 fgEHzeAA5p7gKaz9C9rk2CFCidGwEn6Dg8w/XmjJJCfBvbQ+ZPwEkIEdHEGpL7rD5qth GQxAEUGbAW6uJLzM8Xe2zXPlvZyoNpc7+ik83nOh7fI1tDe67N4rio0C1QdADUwUAqjR 5Nm6DOv/YriRM7VwfxNAf7dFHjpq6KH/iMOS1pjP6qmV33wL2/nSvw8Wy9bSCgLo3MmG zJwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vBY6HV1Qej/RJ01qRTL+9wLFWIqsKm76YvTE5EBi5y0=; b=PTYxshToEyYikY+TNtGRiv5KMzCF2HaUBr7QVspxrnlRRGiVdFiQO8mAuu7AKhaPqZ 96MJShAVHlcAvy/iYJNllDmDPHxHBwdwn3l9/zmP9Hibn7TQRKfb6Ek0useuzGN4u8Zk CPSRBc6O8zO+7TaD9qMmtrHn26eZHwFFjfL6Hp2pUMAshMZp1zqs6PixIWljeC/Z0tm8 ZkKI6PmyGxY5INps5qbkkLQ/PCUf/lOrBe+RNmWc97BiVVfvIc3pKLAWvWEiHwVIbSnC +aeT0MlsA4V9M4sV1Jr+gIwak8pc/sDfkkEl5M3yhYOEr6+37lEj8AVmpCbBym1LIWqF Z3Yw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.32; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726640AbgI1PR3 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14319 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726461AbgI1PR0 (ORCPT ); Mon, 28 Sep 2020 11:17:26 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BA40D6108F3A421C3A66; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:12 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 05/20] ARM: debug: add UART early console support for SD5203 Date: Mon, 28 Sep 2020 23:13:09 +0800 Message-ID: <20200928151324.2134-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add support of early console for SD5203. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/Kconfig.debug | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3549..d27a7764c3bfb46 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1086,6 +1086,14 @@ choice on SA-11x0 UART ports. The kernel will check for the first enabled UART in a sequence 3-1-2. + config DEBUG_SD5203_UART + bool "Hisilicon SD5203 Debug UART" + depends on ARCH_SD5203 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SD5203 UART. + config DEBUG_SOCFPGA_UART0 depends on ARCH_SOCFPGA bool "Use SOCFPGA UART0 for low-level debug" @@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR + default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART default 0xfed60000 if DEBUG_RK29_UART0 default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 From patchwork Mon Sep 28 15:13:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313653 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393025ilg; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeoM1DAXdv/H1tSt95jI9kL/x3owVxNz6ev5XtW7wJHkBKJPRVBM7W1e3PB8VCwyonW4gy X-Received: by 2002:aa7:d991:: with SMTP id u17mr2332250eds.11.1601306250055; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306250; cv=none; d=google.com; s=arc-20160816; b=ylMSOAck4yFypsdco6++soH1hA3BkpUwI9C2nrvt8/zwR4pvWGl11xV3faRxfuWsLa Sk+yr1/G+kt7RiAnPhLXgGWSNz9i1a64rXtHF93r3sbYltQQ4qWJcnwoO2GcNQrwqGLQ gUKL6CGRvKZZL0gfQc/JhtoQrgiBriYhivnbmxNeyxCJdySmUbZsH2JIVza1WXJwQM0/ yRGNMUxar4hU3ffQpF7pPe3rLa8l0zXtiKRGQzR7NjsgnzH551rpeze0+dA7veLSIBlU i3/EaoMt8uvm3P/oBjJyvPWnGaWBxHZh1TAssA5LaWXwg2pb4xEO4EFNPVY2FFzK0SYE tVWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eP9Kk2TWGXf3Fp1/uhi3NrjPJNNPWX/aTD0AhgZAW7o=; b=fnOk5xBJYWB3cC2l9EKtGp5zMM+KahRzXlnjSt7uIkU4K4ooRkTq1iNxjgPlKC1zR+ 2NAJrf+Q7VbTV4X1BW5wDGnl1h6O6zNcB55mE5r5DH7Ij8qSSmaaWgMuUIhqEKkBHFSf e2PRhl4H8kSU+tuo9HJ9PgSXbZku6GpSoFyLpstKeXcej1C0yITiwWEHUhYSLf+L40q6 AEqagZnHSAI92aT5zO/YZKSlhXIauo9h5mwPHyTdWxlC8NqoZ1fuifR6z29g4LSr0BT2 6cm6tMw4yyF8K3velw31s6NDcbbChN3UlD/V4qpneXPuSlcvKQ7iizV97OuotlDB0res yPNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k19si859451ejg.563.2020.09.28.08.17.29; Mon, 28 Sep 2020 08:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbgI1PR3 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14315 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726393AbgI1PRZ (ORCPT ); Mon, 28 Sep 2020 11:17:25 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9E15D6E15112732EB426; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 06/20] ARM: dts: add SD5203 dts Date: Mon, 28 Sep 2020 23:13:10 +0800 Message-ID: <20200928151324.2134-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..41113a46a71a584 --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; From patchwork Mon Sep 28 15:13:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313669 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393899ilg; Mon, 28 Sep 2020 08:18:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyT/uVqcSHlCeFHhuXVcbenGheryoUuIXpfZ+LkmmaRXIcchW957l6xW0T4UEXpBgbx1bMW X-Received: by 2002:a17:907:72c2:: with SMTP id du2mr2250293ejc.512.1601306318457; Mon, 28 Sep 2020 08:18:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306318; cv=none; d=google.com; s=arc-20160816; b=cwPROmGlX8TT8bvhyeNXbk/9kCUidyIga3TAO/ojmQwvRDpuDG9WvpNRqpmp/2rs1m dv0zHNsdOdRzB5bbaXFB18RXaAxq3thUW2+3P7IeUx3oOuuDh/q+A2gib4uaigCOLxTp ufu2fSoD33yTJGm70G1Zh7jMeXxPEBFPF6HkuOf7E7tTTA3olCPhUfM5yvuyn9K7AioF jlKEaVGlIRXa6SpjYMbU/H3lh8N373AqFC65HnZgehj/xQ4T2TIBOS95AHb7HWgiwyOn lyxgX3dlQGadTSQw7Co6+x2B0R8iCCWlVtriwdw8yJQS7wLA+uqft5MtSjJFkKYbLGQb hi/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kHexzk0FyI3xQ8yrB9F5xBHn8wZPj4UUENPfJkLxlvM=; b=rR6LbcM8Cbv00XSjFY/1f66XgtturLDP3XNAPdy++SeHMP30duugR9rVj47BzyIbKJ VsDUxrGcjuCfmsorNOOrNfjLursQO2Ycc5uDtnwLsZCGRSoTRuNwr86ZGFadjf27Yx5k XBZ30bTEemUyM9e56fBIQTJJJsWwG/1fzi59NThLfHgyjMyZ6vyR+yMH2swa+yZtfk94 jc7Np9QLROiErA6+qGDpSa5uXTYzgr+BEdathVaS+I5kp+sKRXOCYsv3++hJ9tPViQL0 GNbeRuXPjLa4ysdPiwd08XVHyXdNWntdG/ePYkRkeARf65CwtD0+Wb6ahovaw2+TVrWN zPeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f2si834335edn.26.2020.09.28.08.18.38; Mon, 28 Sep 2020 08:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbgI1PR3 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14314 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726409AbgI1PR1 (ORCPT ); Mon, 28 Sep 2020 11:17:27 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A787EF68131FF3540F79; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Date: Mon, 28 Sep 2020 23:13:11 +0800 Message-ID: <20200928151324.2134-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sysctrl.txt | 19 ---- .../controller/hisilicon,hip01-sysctrl.txt | 19 ---- .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ----- .../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 --- 5 files changed, 115 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt deleted file mode 100644 index 07e318eda254f52..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt deleted file mode 100644 index db2dfdce799db91..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt deleted file mode 100644 index 963f7f1ca7a2f0c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt +++ /dev/null @@ -1,25 +0,0 @@ -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml new file mode 100644 index 000000000000000..37b214e0a401d7d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - const: hisilicon,sysctrl + - items: + - const: hisilicon,sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + - items: + - const: hisilicon,hi6220-sysctrl + - const: syscon + - items: + - const: hisilicon,hi3519-sysctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + description: the number of cells occupied by one clock ID. + const: 1 + +required: + - compatible + - reg + +examples: + - | + /* Hisilicon system controller */ + system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 8defacc44dd5b9e..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; From patchwork Mon Sep 28 15:13:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313665 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393807ilg; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz1wAfKY35U8XdEho1OQGaAtRABvWeMg4AdB7/SoeIERqFGP73JUKOA+SohL727w8hCZ0fy X-Received: by 2002:a50:ed8d:: with SMTP id h13mr2241867edr.50.1601306312202; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306312; cv=none; d=google.com; s=arc-20160816; b=QCnZEtzS3FKYDz9hlpZhqx/z0qz7stMgAmqlkKc0N3NczfNwW7rswZr/Ln1QOrsY5I vlFbsxS45m1WnQEDxNslZrh7rYO9ti11zkCKkN8EmqYWMzVXtu7y3jXrmqy/ozNMwWQf nAdisW987NYQ2hssSae9aypmv1y7JzOD+PcZc4xxA49LDU85KEPGqL698xmfv1MeEgjg YJHU7YF38UhODviHzXxcnZJPWvkvDVkgN0i5YkG5Kob7AohhXWbuSMTzPGa4TTp1LEOP WPQ7Gy8EOEJRF010rSry7DMH1ZbyllENHGZugEnq3j9d1er2oC0aW4SqW8oFsLkzLNUi WklQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Uaj6Yn3XluKlP4n9rxXUULHTE+D+Vz1f7yEEX5pXWo8=; b=DGKA4rdiizNSTyXO0xifCs0UmeuiVI7reqURHf84fglQ9PbDtz3X5nHGp2pRqOtLDR H6yTpQEC2HEBevYYJdFxm2ehCBMqJC6OUTYnY6VIl4AUwGzyz3ZIDnz5NvVTcjVaBgkA 9v7tA8J93GO5QLGOrW1y1QxUVUXp17WktfDjsqasFS5Y0oYIpqzqAkxxVa7nCOr8bLMx I7qqS58h65VNqLuWkfQhAmkQYiAKEPnXnFh0ZPHoOtveJe4ii01M4W1JPPRpSj2AAIKl cFXl2qzyV7vbIJj1kLS3VkNliri2t3Ucufxwhqtx53l1kSpwdZm03KbwB3uM/yrGmUQF aFsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.29; Mon, 28 Sep 2020 08:18:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726863AbgI1PSZ (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:25 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:37822 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726565AbgI1PRa (ORCPT ); Mon, 28 Sep 2020 11:17:30 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E62479A315EEB3B5ABEE; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon, peri-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:12 +0800 Message-ID: <20200928151324.2134-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PERI subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,peri-subctrl.txt | 16 ---------- .../controller/hisilicon,peri-subctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt deleted file mode 100644 index b96c2896078b914..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml new file mode 100644 index 000000000000000..838b1a2a2c8a9a1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PERI subsystem controller + +maintainers: + - Wei Xu + +description: | + The PERI sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. The peripheral + controllers include mdio, ddr, iic, uart, timer and so on. + +properties: + compatible: + items: + - const: hisilicon,peri-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +examples: + - | + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x80000000 0x10000>; + }; +... From patchwork Mon Sep 28 15:13:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313660 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393426ilg; Mon, 28 Sep 2020 08:18:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxu5StEjH/MubLCqVpQbvo4HquREhnTQfkmPujjqDY1VkGKQS5jzRhHHB4NFSsaZ6Y9KEua X-Received: by 2002:a17:906:4805:: with SMTP id w5mr2241380ejq.313.1601306285458; Mon, 28 Sep 2020 08:18:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306285; cv=none; d=google.com; s=arc-20160816; b=y5B9DKEFWAY1ZvUgN3lRwZkbRGKt40jjzbc8/Y+iT13xaOvE7/ZEPKbvoU4ic5/YzT 7OGVxTNA0dbY8OBEjhqk96LOfxc4eATQELmQciA1+D0dJyqlM287AA2ZcIwZNPUzZ6WN oRw7WKRHfhYnGQ1RKjvkyZcHN6uIZTXD7OWY2WDsIbcMPQfln2W9y71N4IAoOt61UmS8 KU+fOVihl7r6VEGDHnDPuBn+AS1du0khImqzuAr5ojigC4TdPx/45aXiOr5OHCQQhCJX 8e3iAggDTUsnjzGJKHOyNzbsRS9gEbYQelC3k7qS3TKGMMTKKRrKUsOvUV9pvJEGRTx6 7ggA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=RNU9yaEfQxoyutZLWvt9tGmKc56T71YD/9quHqHLT/I=; b=UEhN1uAKJ1w2P6NF1B3uwo13of26dwVT5T0EobrI4pDFtwlPNYOQXDWpc2VlW2Qi1v 2FQKAf8hrkTfinU9iTCCY42h+PhcptNbBM+PUcTYhW5IaU5c0aAs0vFzVNakHO/Sy9rH ps9clABM2bZ/96g8CABVkH0xkIrF+xHz7cF/bjHvHuRIhwGQjBvp265usYWGbkj0DBlS r5r5Drci4UjbPMkaqiYvkO3fUQ8gSHFftOuC9w/uPVEK8bCxcFKRv4tgwMxeog1iO9hY nwHHruYK1cX1FalvEU2RvrH1Tsz2LwFHtouCK+oApWiNmivSn+A2+nvQCJisHqGKgaiq BDrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ds2si775629ejc.117.2020.09.28.08.18.05; Mon, 28 Sep 2020 08:18:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726798AbgI1PR7 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:59 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14760 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726691AbgI1PRu (ORCPT ); Mon, 28 Sep 2020 11:17:50 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C5BB7C5288583ED04631; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon, pcie-sas-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:13 +0800 Message-ID: <20200928151324.2134-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,pcie-sas-subctrl.txt | 15 --------- .../controller/hisilicon,pcie-sas-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt deleted file mode 100644 index 1ef086bda81a3f5..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml new file mode 100644 index 000000000000000..2de875ae781cf8a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller + +maintainers: + - Wei Xu + +description: | + The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,pcie-sas-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.28; Mon, 28 Sep 2020 08:18:28 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbgI1PS0 (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:26 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14759 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726629AbgI1PRb (ORCPT ); Mon, 28 Sep 2020 11:17:31 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B8AABE3B29F1C90710DA; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:15 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:14 +0800 Message-ID: <20200928151324.2134-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------- .../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671668..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml new file mode 100644 index 000000000000000..05b97e0bc35b090 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... 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[23.128.96.18]) by mx.google.com with ESMTP id ds2si775629ejc.117.2020.09.28.08.18.05; Mon, 28 Sep 2020 08:18:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726802AbgI1PSA (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:00 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14323 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726694AbgI1PRg (ORCPT ); Mon, 28 Sep 2020 11:17:36 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AB312D69C965B10A16DB; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon, pctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:15 +0800 Message-ID: <20200928151324.2134-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 --------- .../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt deleted file mode 100644 index deec777bc3a850a..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml new file mode 100644 index 000000000000000..8b00e9c222594f4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id n18si785494ejz.158.2020.09.28.08.17.41; Mon, 28 Sep 2020 08:17:41 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726722AbgI1PRg (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:36 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14758 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726667AbgI1PRf (ORCPT ); Mon, 28 Sep 2020 11:17:35 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B43DB21DEAD72E83E50D; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon, hi3798cv200-perictrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:16 +0800 Message-ID: <20200928151324.2134-13-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ---------- .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++ 2 files changed, 45 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt deleted file mode 100644 index 0d5282f4670658d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml new file mode 100644 index 000000000000000..4e547017e368393 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + description: Register address and size + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.19; Mon, 28 Sep 2020 08:18:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726466AbgI1PSI (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:08 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14761 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726615AbgI1PRe (ORCPT ); Mon, 28 Sep 2020 11:17:34 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C1308A9E82A37A76BA32; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:17 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon, dsa-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:17 +0800 Message-ID: <20200928151324.2134-14-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 DSA subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 --------- .../controller/hisilicon,dsa-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt deleted file mode 100644 index 4d1c6abf03f6f97..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml new file mode 100644 index 000000000000000..3e18fd8debd92f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 DSA subsystem controller + +maintainers: + - Wei Xu + +description: | + The DSA sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,dsa-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id sb9si926761ejb.54.2020.09.28.08.17.59; Mon, 28 Sep 2020 08:17:59 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbgI1PRz (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:55 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14322 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726672AbgI1PRh (ORCPT ); Mon, 28 Sep 2020 11:17:37 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AFFD115277287867032E; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:17 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon, hip04-fabric bindings to json-schema Date: Mon, 28 Sep 2020 23:13:18 +0800 Message-ID: <20200928151324.2134-15-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hip04-fabric.txt | 5 ----- .../controller/hisilicon,hip04-fabric.yaml | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 5 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt deleted file mode 100644 index 40453d02f2024bd..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt +++ /dev/null @@ -1,5 +0,0 @@ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml new file mode 100644 index 000000000000000..47a2ec6a4704f4c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... 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[23.128.96.18]) by mx.google.com with ESMTP id k19si859451ejg.563.2020.09.28.08.17.29; Mon, 28 Sep 2020 08:17:29 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726567AbgI1PR2 (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:28 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:37818 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726566AbgI1PR1 (ORCPT ); Mon, 28 Sep 2020 11:17:27 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E11FCAB5BEF7581E3E4D; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:18 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon, hip04-bootwrapper bindings to json-schema Date: Mon, 28 Sep 2020 23:13:19 +0800 Message-ID: <20200928151324.2134-16-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "" or ", " format. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hip04-bootwrapper.txt | 9 ------ .../controller/hisilicon,hip04-bootwrapper.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 9 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt deleted file mode 100644 index b0d53333f4fdae1..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt +++ /dev/null @@ -1,9 +0,0 @@ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml new file mode 100644 index 000000000000000..d88ef8487879fc1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method +... 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[23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.20; Mon, 28 Sep 2020 08:18:20 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726684AbgI1PSR (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:17 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14762 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726617AbgI1PRb (ORCPT ); Mon, 28 Sep 2020 11:17:31 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id BCCC113061393D79571E; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-aoctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:20 +0800 Message-ID: <20200928151324.2134-17-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Always ON domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-aoctrl.txt | 18 ---------- .../controller/hisilicon,hi6220-aoctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt deleted file mode 100644 index 5a723c1d45f4a17..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml new file mode 100644 index 000000000000000..6939fe85e1895f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Always ON domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power always + on domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-aoctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + }; +... From patchwork Mon Sep 28 15:13:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313661 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3393627ilg; Mon, 28 Sep 2020 08:18:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6TOJS9P00Seq4UzRnSfEA7ufoeMlrN7/LWA8eVbWdaxP4sJol8HACCfpMzWzjbZO/aRF6 X-Received: by 2002:aa7:c693:: with SMTP id n19mr2392431edq.101.1601306299373; Mon, 28 Sep 2020 08:18:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601306299; cv=none; d=google.com; s=arc-20160816; b=DU/eHlErfalatUv1MjJLii8/yTsekS8aaTxex/jncR+Cc035yqUz8OdW/Tn9gL3cMY 1C1qH1NVUelr1fCFAlQSsauZP85paw0ZpBeUOtuhiezqo4hgsHhquw0U7RKenuX8s1xb BQap4yzih0XiXngprpEhuq23bf8NhvvedC6lDp++uN/mszAGDUf1UtLUNQfvZq7FzalK l6oqwPqWeMD8gLS2zEUAqcg7aZoh6nBBgRx1sFv4qZffiZkgteZqHLF+mbcsUAiN9zxd IEk4bwKy9XN6eBQd/7M+aCltEOA5ZIjTm5Ihl31zGT23HZhmwZQmsiZQ6UITaXHuNCpp Ri/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Df5BIvaYH+dH9t2mAXW0P0qr5bqGzE64j0TyqPJe1rM=; b=PaFtouCF0CqYPlXCJf/1yHS2q0VVpho9gASqk8aPErJhgMFkje3Nqn0w1T+BzaERBZ k357SKltqRwHIXsTaykdAD2V9jMpjCII9LLSoDcYOzygkpmujHxE5jJFbYdhwe1c6tiA 9143+zJOC7lrEBcpui9Y/hjq5MQZJoekPa/LtYGGb6Zi1k/WaNUikLoZOZ2dQnhKM00A xWCFytkpqjf+eqV7oIko8hA9mU2ynSiUAjWmCladphLI1AjFgkbfgBkWYs7O0ih3Q26s UdllugfD1qhs6wg07RsoxMcfBA/9hXFilKYzwqzZh5nzo260EMl7rm0QH2HCXodmWaBe i1ow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l18si864473edw.354.2020.09.28.08.18.17; Mon, 28 Sep 2020 08:18:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726823AbgI1PSJ (ORCPT + 6 others); Mon, 28 Sep 2020 11:18:09 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14257 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726684AbgI1PRe (ORCPT ); Mon, 28 Sep 2020 11:17:34 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C5873411824F303FF16B; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-mediactrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:21 +0800 Message-ID: <20200928151324.2134-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Media domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-mediactrl.txt | 18 ---------- .../controller/hisilicon,hi6220-mediactrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt deleted file mode 100644 index dcfdcbcb6455771..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml new file mode 100644 index 000000000000000..d6edbe8773a103b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Media domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the multimedia + domain(e.g. codec, G3D ...) for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-mediactrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id ds2si775629ejc.117.2020.09.28.08.18.04; Mon, 28 Sep 2020 08:18:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbgI1PRg (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:36 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14259 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726686AbgI1PRf (ORCPT ); Mon, 28 Sep 2020 11:17:35 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D00FCE9BE18A85133902; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-pmctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:22 +0800 Message-ID: <20200928151324.2134-19-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Management domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-pmctrl.txt | 18 ---------- .../controller/hisilicon,hi6220-pmctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt deleted file mode 100644 index 972842f07b5a2ce..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml new file mode 100644 index 000000000000000..978a6920d69c217 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Management domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power management + domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-pmctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id la6si779104ejb.696.2020.09.28.08.17.51; Mon, 28 Sep 2020 08:17:51 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726573AbgI1PRu (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:50 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14260 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726693AbgI1PRi (ORCPT ); Mon, 28 Sep 2020 11:17:38 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D4BB6B6F12FD7EBCC3EA; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:20 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-sramctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:23 +0800 Message-ID: <20200928151324.2134-20-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 SRAM controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sramctrl.txt | 16 --------- .../controller/hisilicon,hi6220-sramctrl.yaml | 38 ++++++++++++++++++++++ 2 files changed, 38 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt deleted file mode 100644 index 086b7acccc5edc4..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml new file mode 100644 index 000000000000000..4ac1e14420ecfe7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 SRAM controller + +maintainers: + - Wei Xu + +description: | + Hisilicon's SoCs use SRAM for consistency purpose; on Hi6220 there have + several SRAM banks for power management, modem, security, etc. Further, use + "syscon" managing the common sram which can be shared by multiple modules. + +properties: + compatible: + items: + - const: hisilicon,hi6220-sramctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi6220 */ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0xfff80000 0x12000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id la6si779104ejb.696.2020.09.28.08.17.50; Mon, 28 Sep 2020 08:17:50 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726651AbgI1PRi (ORCPT + 6 others); Mon, 28 Sep 2020 11:17:38 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14258 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726685AbgI1PRi (ORCPT ); Mon, 28 Sep 2020 11:17:38 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CB0E52C6F86EFDA2BF55; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:21 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Mon, 28 Sep 2020 23:13:24 +0800 Message-ID: <20200928151324.2134-21-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml new file mode 100644 index 000000000000000..83ca10adce71b62 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hip06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + description: base memory range where the LPC register set is mapped. + maxItems: 1 + + '#address-cells': + description: must be 2 which stick to the ISA/EISA binding doc. + const: 2 + + '#size-cells': + description: must be 1 which stick to the ISA/EISA binding doc. + const: 1 + +required: + - compatible + - reg + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...