From patchwork Mon Oct 12 13:17:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317638 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616968ilm; Mon, 12 Oct 2020 06:20:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxF8nrtA1KtMu9w0Z6/I5j5m/76whGa4CIZfS9r/W3SlVaG+L+Aa7HUnOUHH77fX9Xvz8v+ X-Received: by 2002:a17:906:eb59:: with SMTP id mc25mr27555616ejb.34.1602508813983; Mon, 12 Oct 2020 06:20:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508813; cv=none; d=google.com; s=arc-20160816; b=Q7RqdzSlgcKLjX6OWkAEXtJMzpXg+TKFuhFNVi9ehpSVu3YZgCyV+KY7YmOv0FtqxH aG+wPjN8PwgUWQqP837ii/nuj91BKbSQPO3ooDey2nitZsDBUU2y7jEITJyn+oyPVO5Y FWY615Jvf4p+niCCkTan2O5H3yRHoE/ZiY0YmvCY5SNgpE+0JNC5cKRQxglTv4Lus2eF eN0qAWhE7iN8LosJV+pEgzHqedWYT7IApod4OIX4AtwNaOaPtLb+Y0qbQZhgHieSJ6CM tjyRRJ5KaBKkvJfqy3DT46w2p6TVeo80mDFrrZPJagAA8Ykj8kQroKVO6mWtEdyXThXH 8RvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=4vJZ539dMxDzV28hxz5DRGHDg0j64KXEc04XT8Ra2Fk=; b=TP9qRtTJjudWyM9T0SibxvhAt5gHRKwxzQqNmF2qHfyux0fqZWBS5hHYrfyi1byKD3 3Qu5YqgMCKTCXK/V+c/6cz4auHG4qEuCR9jUQZoRP0MzQ160NsR1gzxnkEw7OOk8LHJX ZGFyVUaGUtfE/BJ7Iihf6Zvl9gG75h1/HS/WzZZm1WYXFiTsEtGbscG/IW2ydpnXwNsf Jiwk31kp4l4d9ri1DH/RcrAbvZTsdvheAHh0VVoeoo6ZRYQw2/f0y3MRanf26X9gI4Nv Zh/9MiesaiGEOB/Sgtie7KqLOCILyZGgo9JCNx3QCc+Ein3HxuaR6kqGigVV0Vhc/m4v PXEQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.13; Mon, 12 Oct 2020 06:20:13 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387407AbgJLNUN (ORCPT + 6 others); Mon, 12 Oct 2020 09:20:13 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56730 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388883AbgJLNTf (ORCPT ); Mon, 12 Oct 2020 09:19:35 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 82C53D499816D365E587; Mon, 12 Oct 2020 21:19:30 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:23 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 01/11] arm64: dts: hisilicon: normalize the node name of the ITS devices Date: Mon, 12 Oct 2020 21:17:29 +0800 Message-ID: <20201012131739.1655-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change the node name of the ITS devices to match "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although "interrupt-controller" is allowed, but "msi-controller" is preferred. Otherwise, "interrupt-controller@b7000000: False schema does not allow" will be reported by arm,gic-v3.yaml. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++-------- 3 files changed, 13 insertions(+), 13 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index bc49955360db754..f7e3a7af4634233 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -242,28 +242,28 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_peri: interrupt-controller@8c000000 { + its_peri: msi-controller@8c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x8c000000 0x0 0x40000>; }; - its_m3: interrupt-controller@a3000000 { + its_m3: msi-controller@a3000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xa3000000 0x0 0x40000>; }; - its_pcie: interrupt-controller@b7000000 { + its_pcie: msi-controller@b7000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xb7000000 0x0 0x40000>; }; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 50ceaa959bdc016..a2fba458e047fd7 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -242,7 +242,7 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 4773a533fce589d..892691bb2adb446 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -924,56 +924,56 @@ <0x0 0xfe020000 0x0 0x10000>; /* GICV */ interrupts = ; - p0_its_peri_a: interrupt-controller@4c000000 { + p0_its_peri_a: msi-controller@4c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x4c000000 0x0 0x40000>; }; - p0_its_peri_b: interrupt-controller@6c000000 { + p0_its_peri_b: msi-controller@6c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x6c000000 0x0 0x40000>; }; - p0_its_dsa_a: interrupt-controller@c6000000 { + p0_its_dsa_a: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: msi-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: msi-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: msi-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: msi-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: msi-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; From patchwork Mon Oct 12 13:17:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317628 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616470ilm; Mon, 12 Oct 2020 06:19:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywaiXoscPtDrdPwUcJSOUTDFgDZYdeo7xcDqPdBpticMxQ5y75YGLd3yO9hX66B7aUwJPV X-Received: by 2002:a17:906:5593:: with SMTP id y19mr27402976ejp.369.1602508777772; Mon, 12 Oct 2020 06:19:37 -0700 (PDT) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id a2si11836700edr.352.2020.10.12.06.19.37; Mon, 12 Oct 2020 06:19:37 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388875AbgJLNTf (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:35 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56726 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387930AbgJLNTc (ORCPT ); Mon, 12 Oct 2020 09:19:32 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7CD5C785A6FADD2C97AB; Mon, 12 Oct 2020 21:19:30 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:24 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 02/11] arm64: dts: hisilicon: separate each group of data in the property "reg" Date: Mon, 12 Oct 2020 21:17:30 +0800 Message-ID: <20201012131739.1655-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Do not write the "reg" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \ 6291456] is too long Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 148 +++++++++++++++---------------- 2 files changed, 76 insertions(+), 76 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a2fba458e047fd7..941d527dcb8668c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -434,8 +434,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 892691bb2adb446..36a873d150897b8 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1321,8 +1321,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; @@ -1720,24 +1720,24 @@ }; p0_sec_a: crypto@d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x0 0xd0000000 0x0 0x10000 - 0x0 0xd2000000 0x0 0x10000 - 0x0 0xd2010000 0x0 0x10000 - 0x0 0xd2020000 0x0 0x10000 - 0x0 0xd2030000 0x0 0x10000 - 0x0 0xd2040000 0x0 0x10000 - 0x0 0xd2050000 0x0 0x10000 - 0x0 0xd2060000 0x0 0x10000 - 0x0 0xd2070000 0x0 0x10000 - 0x0 0xd2080000 0x0 0x10000 - 0x0 0xd2090000 0x0 0x10000 - 0x0 0xd20a0000 0x0 0x10000 - 0x0 0xd20b0000 0x0 0x10000 - 0x0 0xd20c0000 0x0 0x10000 - 0x0 0xd20d0000 0x0 0x10000 - 0x0 0xd20e0000 0x0 0x10000 - 0x0 0xd20f0000 0x0 0x10000 - 0x0 0xd2100000 0x0 0x10000>; + reg = <0x0 0xd0000000 0x0 0x10000>, + <0x0 0xd2000000 0x0 0x10000>, + <0x0 0xd2010000 0x0 0x10000>, + <0x0 0xd2020000 0x0 0x10000>, + <0x0 0xd2030000 0x0 0x10000>, + <0x0 0xd2040000 0x0 0x10000>, + <0x0 0xd2050000 0x0 0x10000>, + <0x0 0xd2060000 0x0 0x10000>, + <0x0 0xd2070000 0x0 0x10000>, + <0x0 0xd2080000 0x0 0x10000>, + <0x0 0xd2090000 0x0 0x10000>, + <0x0 0xd20a0000 0x0 0x10000>, + <0x0 0xd20b0000 0x0 0x10000>, + <0x0 0xd20c0000 0x0 0x10000>, + <0x0 0xd20d0000 0x0 0x10000>, + <0x0 0xd20e0000 0x0 0x10000>, + <0x0 0xd20f0000 0x0 0x10000>, + <0x0 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_a>; iommus = <&p0_smmu_alg_a 0x600>; dma-coherent; @@ -1761,24 +1761,24 @@ }; p0_sec_b: crypto@8,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x8 0xd0000000 0x0 0x10000 - 0x8 0xd2000000 0x0 0x10000 - 0x8 0xd2010000 0x0 0x10000 - 0x8 0xd2020000 0x0 0x10000 - 0x8 0xd2030000 0x0 0x10000 - 0x8 0xd2040000 0x0 0x10000 - 0x8 0xd2050000 0x0 0x10000 - 0x8 0xd2060000 0x0 0x10000 - 0x8 0xd2070000 0x0 0x10000 - 0x8 0xd2080000 0x0 0x10000 - 0x8 0xd2090000 0x0 0x10000 - 0x8 0xd20a0000 0x0 0x10000 - 0x8 0xd20b0000 0x0 0x10000 - 0x8 0xd20c0000 0x0 0x10000 - 0x8 0xd20d0000 0x0 0x10000 - 0x8 0xd20e0000 0x0 0x10000 - 0x8 0xd20f0000 0x0 0x10000 - 0x8 0xd2100000 0x0 0x10000>; + reg = <0x8 0xd0000000 0x0 0x10000>, + <0x8 0xd2000000 0x0 0x10000>, + <0x8 0xd2010000 0x0 0x10000>, + <0x8 0xd2020000 0x0 0x10000>, + <0x8 0xd2030000 0x0 0x10000>, + <0x8 0xd2040000 0x0 0x10000>, + <0x8 0xd2050000 0x0 0x10000>, + <0x8 0xd2060000 0x0 0x10000>, + <0x8 0xd2070000 0x0 0x10000>, + <0x8 0xd2080000 0x0 0x10000>, + <0x8 0xd2090000 0x0 0x10000>, + <0x8 0xd20a0000 0x0 0x10000>, + <0x8 0xd20b0000 0x0 0x10000>, + <0x8 0xd20c0000 0x0 0x10000>, + <0x8 0xd20d0000 0x0 0x10000>, + <0x8 0xd20e0000 0x0 0x10000>, + <0x8 0xd20f0000 0x0 0x10000>, + <0x8 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_b>; iommus = <&p0_smmu_alg_b 0x600>; dma-coherent; @@ -1802,24 +1802,24 @@ }; p1_sec_a: crypto@400,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; + reg = <0x400 0xd0000000 0x0 0x10000>, + <0x400 0xd2000000 0x0 0x10000>, + <0x400 0xd2010000 0x0 0x10000>, + <0x400 0xd2020000 0x0 0x10000>, + <0x400 0xd2030000 0x0 0x10000>, + <0x400 0xd2040000 0x0 0x10000>, + <0x400 0xd2050000 0x0 0x10000>, + <0x400 0xd2060000 0x0 0x10000>, + <0x400 0xd2070000 0x0 0x10000>, + <0x400 0xd2080000 0x0 0x10000>, + <0x400 0xd2090000 0x0 0x10000>, + <0x400 0xd20a0000 0x0 0x10000>, + <0x400 0xd20b0000 0x0 0x10000>, + <0x400 0xd20c0000 0x0 0x10000>, + <0x400 0xd20d0000 0x0 0x10000>, + <0x400 0xd20e0000 0x0 0x10000>, + <0x400 0xd20f0000 0x0 0x10000>, + <0x400 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_a>; iommus = <&p1_smmu_alg_a 0x600>; dma-coherent; @@ -1843,24 +1843,24 @@ }; p1_sec_b: crypto@408,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x408 0xd0000000 0x0 0x10000 - 0x408 0xd2000000 0x0 0x10000 - 0x408 0xd2010000 0x0 0x10000 - 0x408 0xd2020000 0x0 0x10000 - 0x408 0xd2030000 0x0 0x10000 - 0x408 0xd2040000 0x0 0x10000 - 0x408 0xd2050000 0x0 0x10000 - 0x408 0xd2060000 0x0 0x10000 - 0x408 0xd2070000 0x0 0x10000 - 0x408 0xd2080000 0x0 0x10000 - 0x408 0xd2090000 0x0 0x10000 - 0x408 0xd20a0000 0x0 0x10000 - 0x408 0xd20b0000 0x0 0x10000 - 0x408 0xd20c0000 0x0 0x10000 - 0x408 0xd20d0000 0x0 0x10000 - 0x408 0xd20e0000 0x0 0x10000 - 0x408 0xd20f0000 0x0 0x10000 - 0x408 0xd2100000 0x0 0x10000>; + reg = <0x408 0xd0000000 0x0 0x10000>, + <0x408 0xd2000000 0x0 0x10000>, + <0x408 0xd2010000 0x0 0x10000>, + <0x408 0xd2020000 0x0 0x10000>, + <0x408 0xd2030000 0x0 0x10000>, + <0x408 0xd2040000 0x0 0x10000>, + <0x408 0xd2050000 0x0 0x10000>, + <0x408 0xd2060000 0x0 0x10000>, + <0x408 0xd2070000 0x0 0x10000>, + <0x408 0xd2080000 0x0 0x10000>, + <0x408 0xd2090000 0x0 0x10000>, + <0x408 0xd20a0000 0x0 0x10000>, + <0x408 0xd20b0000 0x0 0x10000>, + <0x408 0xd20c0000 0x0 0x10000>, + <0x408 0xd20d0000 0x0 0x10000>, + <0x408 0xd20e0000 0x0 0x10000>, + <0x408 0xd20f0000 0x0 0x10000>, + <0x408 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_b>; iommus = <&p1_smmu_alg_b 0x600>; dma-coherent; From patchwork Mon Oct 12 13:17:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317629 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616477ilm; Mon, 12 Oct 2020 06:19:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxWvoUTAX9mdIRJPgbjQn11V44k4RQsRcCBvxQ3Fz5/8k8LuA+48Re/stSUgwuJiU+S6quQ X-Received: by 2002:a1c:48d4:: with SMTP id v203mr7880635wma.122.1602508778317; Mon, 12 Oct 2020 06:19:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508778; cv=none; d=google.com; s=arc-20160816; b=qsDdEP3SsobrN7qUdwGUrxLGuzdJBGzzdVbZ9wcfLcS2N7lA+iHKR7JcSXVlnPNqSL vQv0i4OPxzVivXE41MEwBh/z+oftUyQiD3XPQKk99mtUxpzibVUMXtOvTDF2cG2pCooD mAtoQHHEzRjcVmAp8T6Jm2SFw4pB8IvfFSWj+LVwE+VUKyIfV11yHIMhbECz2kJxTKFv cuRUhnPIR9XJoKbfhd6p89YvLtOx/Y1XUTdJgirR4k8sF6V+Wnrp/zm2Mp5ER0+7B4GK lIhqKwMRQ/dqmwHxzXSwBsvIz8IrhE22GUbeE8LDOw4E2Jtb5pCNymBd8/F8e7fS4evk p/VQ== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id a2si11836700edr.352.2020.10.12.06.19.38; Mon, 12 Oct 2020 06:19:38 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388887AbgJLNTg (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:36 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:41240 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388218AbgJLNTc (ORCPT ); Mon, 12 Oct 2020 09:19:32 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id AC974AEEC860769E8AED; Mon, 12 Oct 2020 21:19:30 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:24 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 03/11] arm64: dts: hisilicon: write the values of property-units into a uint32 array Date: Mon, 12 Oct 2020 21:17:31 +0800 Message-ID: <20201012131739.1655-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml. ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 9 ++++----- 3 files changed, 8 insertions(+), 7 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 994140fbc916eea..3f6b1715835af06 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,7 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 2dcffa3ed2189eb..668977d1acba94c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -667,7 +667,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 12bc1d3ed4243f5..993998ac27c503c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -91,11 +91,10 @@ gmacphyrst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; + ti,reset-bits = < + 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + >; }; }; From patchwork Mon Oct 12 13:17:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317635 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616840ilm; Mon, 12 Oct 2020 06:20:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIph4Z7yp7MyuKJCSCCcZhBz9S2FlyjHn99IOY307P5vO6dBJNTJVUFTS4cdKOge8qqqZu X-Received: by 2002:a05:6402:1c8f:: with SMTP id cy15mr14369140edb.335.1602508802313; Mon, 12 Oct 2020 06:20:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508800; cv=none; d=google.com; s=arc-20160816; b=ANJ8Dn5g+OfcUTaZ7zNxUrT3hmS/CQyPEmduXeh1MBKX+HrvA2mYi3V3QR/WayLlcA KxKSu4itHG8eFPSwbEWzPijqyA5GS427f/F7JJ1JqChOtRTVoL+uhmktT0R6mfpF81uX f1bZeNOE64I2GaikGkzTnRFebHKjWz9Bg/FcQHJJd+Y+ar3KUK1gBoDeSZ+EI4DNz6ZO n8T4KGIS4G/9zeNVSjPRi3jahKXkXwRXKOFGWjOf3sS/CFIy6capgfELC8zOEpIsnz6j y4xepmsI8ld55K/t/KUNcSLkWDYbdLdlZRDQibDh/kIfNXlflkhMu/eoGtWPqNqFqS6p zTGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=SuQPkPRTt3g766sORTWY/YChVsUCqcRF0nzkiIFGSPA=; b=yTGnfWJzwsSLcO2KuPufPuqllbWsecwHxzz88uXTsGxTO7axLUbDDqJ9hZTUG7htev eh5m/x+Y90rZWMpbXPwpnEi+1KYUfEDhlkTUgGbeYJXl7dYR0Dul/KS+AWQcw5Q+Zhjr JVbrV2V3mHXY8I+rv6hXAzP5RNnQaoqRMNNmV6o4O5rre7lR62docY28ciyj3DEFQ6r6 VcSBbIDu9qRRaQ+nBtWhl5G8/cxvwDR1QqCKalSiKkC9PNtVuAke6tjsK0z0lA47J9QY BxwlQpjVrU6DaFdZPW8cQ7j0l1DSSBuA4LtezE8oLYuRy5FZwSfWB0UinujELUDQYxzr w18Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.00; Mon, 12 Oct 2020 06:20:00 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388942AbgJLNTt (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:49 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56918 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388895AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A4E65BB5CE359F09560D; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:25 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 04/11] arm64: dts: hisilicon: remove unused property pinctrl-names Date: Mon, 12 Oct 2020 21:17:32 +0800 Message-ID: <20201012131739.1655-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names" can be deleted. In fact, the property "pinctrl-names" depends on the property "pinctrl-0". So the errors similar to the following will be reported by pinctrl-consumer.yaml. serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 -- 1 file changed, 2 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 668977d1acba94c..85b0dfb35d6d396 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -213,7 +213,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; @@ -260,7 +259,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; From patchwork Mon Oct 12 13:17:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317631 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616503ilm; Mon, 12 Oct 2020 06:19:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy12+dylbWtEaAMxQj/dTg7gx1lzd41RPveqVkB3X9IAx6NVsSzJoYEc9Cl+AzMlz0SXNQS X-Received: by 2002:a17:906:3b8e:: with SMTP id u14mr27772281ejf.127.1602508780702; Mon, 12 Oct 2020 06:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508780; cv=none; d=google.com; s=arc-20160816; b=gNrY5aEuR9+S4H67wMAL0TU5dMJlpE3vNRcq58MXrM0P2tAe7sRGb2QSSggwmVxuGz VXZE6aIb69KMPAxxDTrC5TPTJb/rRenSuRp43Qd54WCq71+l7hJwC2KLJKqcg5nTYOCf qnSKXIAFFqIiaQsZzAxyBmYfCGtOYif5GPHVEWiM+TF0kES1Xg1NvhDqXSqHZgtEePBY ZsPgQjq9xtMM7SAZPt2V3gN341Rfa+0vzTjjM3nIvXWaCaI1RhT2Wmb5bqqhVux0lmY+ snQk1q0mS9f9LzKRm3rAdHgDbXcLDdjmnqDwusGFhubRaqMQmoDZB4YzFNmFyDbyfya4 T6ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=8M6i70i2hsm6Iu3QYanqog1hwVmGI+nG/YInhlNegTA=; b=B6FhuFpWeFbqr7D+R1AdVg2AVCMGN+jt8yKINdwgmo+jHzOP83Iuo+RnjqAb4LXgNz rr8tjw/x9TU3zt7PSn3KLrvW7ghDkD+hbggKT62P1csiWP/qT5P2gBw8aNR6A8TMpaan fp/6DmRThyNzoOOxC+0wYOqnlsyEUMTAvW5DFVAeYD9OLYhNcb/4aANIyp9Fg/WeW7hl xr5ResKXwLUbxbBUi5b4FZjDmt12Pg4vMxtwSvJ0Hv77td2tQBo2LXFoHHYdqwvwJ4yO MsPjC/ZDbg+O+2X+9XhOdzux7NqEux3Z8TNgIMw2HHbtrKo+J5nd0hpPsPx58VFjsoHv HbWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a2si11836700edr.352.2020.10.12.06.19.40; Mon, 12 Oct 2020 06:19:40 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388917AbgJLNTj (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56854 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388894AbgJLNTi (ORCPT ); Mon, 12 Oct 2020 09:19:38 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 93418D42A3DE88C8277E; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:26 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 05/11] arm64: dts: hisilicon: place clock-names "biu" before "ciu" Date: Mon, 12 Oct 2020 21:17:33 +0800 Message-ID: <20201012131739.1655-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 993998ac27c503c..e24969d53c8fed0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -304,7 +304,7 @@ interrupts = ; clocks = <&crg HISTB_SDIO0_CIU_CLK>, <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; + clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset"; status = "disabled"; From patchwork Mon Oct 12 13:17:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317630 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616488ilm; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2Fc7tLvXFFQZ8pKdl43D6J44V1I0VoUCVdz9ctQAkQtbR6PlZZedsQw8+OfNtE6PKuFql X-Received: by 2002:a05:6402:3070:: with SMTP id bs16mr14464193edb.371.1602508779797; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508779; cv=none; d=google.com; s=arc-20160816; b=DTd1qjJmqu1X9EYx7MHco8LNREKgwuMYAgpeYTppEVnMjU6vOxAaVQIwfGmGly4vyN 56xVROeaXVVT2UZBqleEWrEZJC/EwGvXb+peeEWaWHpSUbdjESexkR+9C8LdqL/Lcj9W 7HC3BZ2kdFTQOUX8rjJYuaOA71TnrjuBHz3nTxQMWrs5SEivIgNm9pnF1t8KiT7x6xv3 19utQsqL4aRJLPMdoKlFiSZjPRIKDZeP8iJV4bqnIckGBrGBcUwy9WaHHzw9ANhaR1Dt DbcZY2lj7ZsIFK5e9aPhNH/NUrgc+n5hW9vovrMlxdS0VjmkA6cMwyJY9g4Omsg4PnPs 4axQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=oPtGyXytBwDyY7GLfqUK5ag6P/tIl9rUM7WWmVsOnzc=; b=ZfLJmJPD8knfQtyR0lF62yzZILJ9ssJwKtxLwBmsIFNNLhYL13EHl3EIvRFxSxRX3z M7+CNIMSeDVth37amIhXH1rWDgiJcu+O4vHeL2Q07LxE0OVIszHLOZhigglFyXGsc73L dZUkqNfbkk4SykXbS9p/Pk8pvSewYC3pSF3oRpNcmpzPWOKUAFaPuZHGMbarZn5cLmvM s6MIh35j3MzrZgLfC1lkzHq9cMic150U5k3KPRwRwCW7RJwTobjjID9MFUl0ObzG7Wja CFS9+fua7EMUMPhuMOXQqHJdLuqCOaJAyGJer4sy9YFvp2WwODs8s/jOxi3vX97RPDjl uNVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a2si11836700edr.352.2020.10.12.06.19.39; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388906AbgJLNTi (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:38 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56920 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388890AbgJLNTi (ORCPT ); Mon, 12 Oct 2020 09:19:38 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A97ABE762066B92B16EE; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:26 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 06/11] arm64: dts: hisilicon: normalize the node name of the SMMU devices Date: Mon, 12 Oct 2020 21:17:34 +0800 Message-ID: <20201012131739.1655-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 941d527dcb8668c..2f1930d4457fe1b 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -330,7 +330,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 36a873d150897b8..ba90b25853555b7 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1161,7 +1161,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; @@ -1170,7 +1170,7 @@ hisilicon,broken-prefetch-cmd; status = "disabled"; }; - p0_smmu_alg_a: smmu_alg@d0040000 { + p0_smmu_alg_a: iommu@d0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_a>; @@ -1183,7 +1183,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: iommu@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1196,7 +1196,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: iommu@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1209,7 +1209,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: iommu@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; From patchwork Mon Oct 12 13:17:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317637 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616954ilm; Mon, 12 Oct 2020 06:20:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjLQy1fCkDqa/KBZeHBzaHn8ZEjjLYvfyWRda882bGmEi2nIyS8hjM/6GNMwboyF2d1csZ X-Received: by 2002:a17:906:4dc7:: with SMTP id f7mr27538574ejw.73.1602508813182; Mon, 12 Oct 2020 06:20:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508813; cv=none; d=google.com; s=arc-20160816; b=ppawNvx0SD8IqbeiVaxQ+/AGAJByQmQsTZ3aA2PnkHy8+qq/kRcd+KsGJGYN21ZwDm WT/9lOP+fJzd/51xiQ9FTPNAZRvd92BPOMyE0WSdiXBaCDa4T/99uvsQV9EbUftk5EWJ 8rkqeXZv+vupdC8eyzkCWP0PW8XtTzyX6nL+L3EBRH/f3rXWARrMZ4HZgS0kcmxkSO2x f3KVw517bfB9WmwUhLhJ0Eny54ABSsRPGiXSzERPQetnmWqVJ+znI6WUhO5oLzrjmOhE uSmcdkFjDrzn/SNHhK2Oq2i8zn1GaJUpDfKqRygA8kRa8A8CBRmp3gjE83JwvE5Or5M1 BSsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eYTBJFqjlxjKW2fEkhP+LuMlCPatzUrTtgv9t1L//O8=; b=LlLZqqJP9gj943/AaBksPgCNWUlAdnTG/Z8Y9SZVn2tCGnJwLLeraYJiWUPi7MZ4/h 4lNiXKrEcPeAWhM4TxNdyKFsJTUlhKjsf+9SvfTpLI+l1IB6IjZOndfy0Ig3ffC8KFPi 2D0mea43/C+uOwEGTMijVcDVUFFndDg28Ez4hGUlgQbNiMviW4EU+8gGNYmjnRZG6QMl 3Lm88tcd9CKO97+h+gB2eSUHS7lwaU1asLrJp0QUqGW6ZL8aCg5w9e7RvClNChA4bBkw ibBfVaBS03V2dpYEGIeYDIKVwUx0BKhTgBMQCXCT1OgFrk2f0YaOY4wwIeBTWxJmtGgN Bckw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.13; Mon, 12 Oct 2020 06:20:13 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388939AbgJLNUB (ORCPT + 6 others); Mon, 12 Oct 2020 09:20:01 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56860 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388889AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 97A3DBEA199870C5118F; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:27 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 07/11] arm64: dts: hisilicon: normalize the node name of the usb devices Date: Mon, 12 Oct 2020 21:17:35 +0800 Message-ID: <20201012131739.1655-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index e24969d53c8fed0..11a72891e2a3a65 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - ohci: ohci@9880000 { + ohci: usb@9880000 { compatible = "generic-ohci"; reg = <0x9880000 0x10000>; interrupts = ; @@ -599,7 +599,7 @@ status = "disabled"; }; - ehci: ehci@9890000 { + ehci: usb@9890000 { compatible = "generic-ehci"; reg = <0x9890000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2f1930d4457fe1b..2d401d74a01f8b9 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -373,7 +373,7 @@ #clock-cells = <0>; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -382,7 +382,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index ba90b25853555b7..7832d9cdec21c93 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1253,7 +1253,7 @@ status = "disabled"; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -1262,7 +1262,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; From patchwork Mon Oct 12 13:17:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317634 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616857ilm; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzbdYkQXd5vxGsP3GDrRtYd0iee/9iqruWo1DWgvi8ZU2NQ89AN2YknIvGdEUTEGVPxqoZx X-Received: by 2002:a17:906:39ce:: with SMTP id i14mr29281519eje.170.1602508806371; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508806; cv=none; d=google.com; s=arc-20160816; b=IkVoedtNZJszZ8xPLv4twUfaSpQ7GnmZY65lkezg/OBrigePytAdGE0zPttaI4zYeC bfiiycDjSchsg2KHS1vuMWUyInhvZDGGf4IkSPigkrPRR/ucl43eXEmvOsC3mOjAtd9k Jt6iOPx2+1hYu3LjN98uICUPwEQMKiyueRDcNPNVHWW+2sM730CasVhrZk0qOGuqJcMj y6toAdL7EyJs3dKTuBjQ/ZMlKJCeHE3ZGNhTmJj7zGNRgNXmehNAX1oCZQ/R+yzwRTss hbSmfi2jMGWFwyJeGuyQAID6CAawdClaFp549/r9DZd79u/2YVE8QjY158cQpXpCRIE5 v+sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=wnnYzRHbTfbV/cwPl+rBglFCy11IV9Ol/tPQ5St+SQ4=; b=Iw6Bsdl/EDomX1ZgG+H98La7iMhbMJw+2VBAiOcEYgPfr9S22ZW+2Pu7kFJZAWeIKc T88+kzyqybMthMZXxPZvU4/fnjGeQgMNFfzc+UiY99QABu23x1Ds2vnPIvXx3dUTnIs+ 34eVbLpdKfewuUkEGv7NSdGmnaIcL+oDssTPHM+AQdSt6KdFZeLv3KOYDTb88PfQDMvR dV4Bh+c0oRRiPkl57id0ksAKKqgFzyyakK4h/MLPvHsgSMesHnFRZ9OphpX0kIr2/gkV olVHockJ52qpkpuqiB8Fa+fb+GNyn485bPMYnKxDwvwEUjEVxNN0vuWwUJjeyBIYXpaX gBrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.06; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388971AbgJLNUB (ORCPT + 6 others); Mon, 12 Oct 2020 09:20:01 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56884 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387930AbgJLNTo (ORCPT ); Mon, 12 Oct 2020 09:19:44 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9C3D8C0B8A6EB6466787; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:27 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 08/11] arm64: dts: hisilicon: normalize the node name of the UART devices Date: Mon, 12 Oct 2020 21:17:36 +0800 Message-ID: <20201012131739.1655-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index f7e3a7af4634233..26caf09e9511b3c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -296,7 +296,7 @@ clock-frequency = <200000000>; }; - uart0: uart@80300000 { + uart0: serial@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; @@ -307,7 +307,7 @@ status = "disabled"; }; - uart1: uart@80310000 { + uart1: serial@80310000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2d401d74a01f8b9..7980709e21ff020 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -359,7 +359,7 @@ status = "disabled"; }; - uart0: lpc-uart@2f8 { + uart0: serial@2f8 { compatible = "ns16550a"; clock-frequency = <1843200>; reg = <0x01 0x2f8 0x08>; From patchwork Mon Oct 12 13:17:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317632 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616714ilm; Mon, 12 Oct 2020 06:19:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCxzZklZ2g6y+AExSdC5DuF6TO0hD8bxoQDBw+XEsnfdaj3vDMs9PRyVyEkGACkv0SVccM X-Received: by 2002:a17:906:a207:: with SMTP id r7mr28928533ejy.32.1602508796154; Mon, 12 Oct 2020 06:19:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508796; cv=none; d=google.com; s=arc-20160816; b=OFgFtekWBjM+3vtPjvWQsjy9gHH2woBOZNrfK7C5aSXqniOC/G6/ukEm2F0S42GeFU r+pv9sZL/NWx83pth8afNICcpGH/l70suczLBGOsISLaDCA+/r7XgM7UtOn2A3qtaBMJ VcRdc5KjQOwQndK4BWS4rGkUpz5r77uuePExuDf3hKpAZI60I/Q2mOTjzJxPbsGzCUT4 X0KIIP5xBnr/Jrl2s455OREEnOYF/hvkeHIgIvF90a9yWxb2oAJk8LiYSVDzNVTlmriM +3np7xylVRPIo7kavwZQNSwxXmrECt8jXhds6ypEdhrjvBzuxQ7AfVYwBa27gxokjm7s bTJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Om3rrhjQM1xhOuv+1COS+kXeffn6dSOACZYs1Bz/xuY=; b=VNDQMGqQjf1D4/SPzgr53QuTCzwzHTUhRm5HPam/B1eePhSRKIu0fAU6bsGzPfMPL4 6w3yIklG3EFiuD1xro/Da092mT6TwKCQm/JRSwLxrEd6OUNjRTx99JevEhHh1hMaxB6T UXD8+m6lJPGxDrGGKiKieKCmJNlsvGernauynZ2ocMLytVGe7YHXnR+lTDbWDbqL76fu Ek15vrd1fiRdDDDOQ/8K2ftBiFWA7SiooiQ7VoEQsKFOSw/HS3A2DAemTF49QeyuBcOC rs3qWpSWp/Wv463zRqTODGplh4WsDtVa6vpLRYvJzCwi+G27ivvpAFcJSb7xWPJri4yC 7Suw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.19.55; Mon, 12 Oct 2020 06:19:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388959AbgJLNTz (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:55 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56900 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388956AbgJLNTy (ORCPT ); Mon, 12 Oct 2020 09:19:54 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A06F4E63F6AAF79F48A2; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:28 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 09/11] arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml Date: Mon, 12 Oct 2020 21:17:37 +0800 Message-ID: <20201012131739.1655-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3f6b1715835af06..edb80abf45b327b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -971,8 +971,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; @@ -986,8 +986,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 11a72891e2a3a65..1c7dda972c92856 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -291,8 +291,8 @@ interrupts = ; num-cs = <1>; cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 014735a9bc7312d..c6580c9f068ebf7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -725,8 +725,8 @@ interrupts = <0 50 4>; bus-id = <0>; enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; + clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; num-cs = <1>; From patchwork Mon Oct 12 13:17:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317636 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616940ilm; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyV+bXC7xF1TqVlus3HC4YJpiLx/EOhX8/BLRgh7IA3fd2Mc51KKtQ5SLtsTtBr9guO3aun X-Received: by 2002:a17:906:d964:: with SMTP id rp4mr802689ejb.110.1602508812315; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508812; cv=none; d=google.com; s=arc-20160816; b=SdviD8USo0ds7sXjp+wdHrMfjTZIM2Or9l71wCcOCng5lSZEf40yWoldSbJTllIXgj UZeQGvcTlsPOCpOmDvJy39rQFO+mXWzvsISLZYLMdnZmGx22ts0KIqw2oDQq4ydkFtmN LsPbWrRSRV6/rgEgwkGMkN2OTMoXtOC+GGmZDTEJybLml2iA0EerLvxbNrtisA3GkzkO XwRCFvcx+RlNVe5a1IC/2TVKxfASPjRlZozWgUeBXvD7xXMT8O47w1qSehKFo/pZgZPX g8/xTu3q9jLz1DOYLlDwHWFNiUx5OdlL5ALCsldQpqJ4mGJh7wQdVO3SyFF3tlVmauhB z/5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=9zop6Rw5JSGx3E+ApZcWr60zeHb+sDC9FfK4QtKUlhg=; b=Zec2YyWKCqRUjPMW7GkFIwCR3RBX4LbDQCZiIkdlFFQLmZtTYD39eszf8DHYOaMYb7 A1itw5WRvKb3jVEQOUa3zangLyTCd2orNFaMAbhHA1SS9k0n4nr6uZbwUgBlCRYGKKOq 6NGjsDxbgtu8WXmeGAqoC52J0W7Hn737Q8R2TNy6xX3q8vo8bG6rdG0e6YePS17mQf4F eBu/p0XqGxmnPTVxL5ZVL3Vdcb837O4gU02QNrMYMNOBh7TSoIf5+Cw769XwAlGHb8Q1 Mj9lnUh+aiwJS/RjSND84n4294FvCqwoWAwiNR1r19b0uJuh7Owo1Og9FkYutMGOrSz6 yBeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.12; Mon, 12 Oct 2020 06:20:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388976AbgJLNUB (ORCPT + 6 others); Mon, 12 Oct 2020 09:20:01 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:15278 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388891AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C55411CB2D0619CA4B7E; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:28 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 10/11] arm64: dts: hisilicon: list all clocks required by pl011.yaml Date: Mon, 12 Oct 2020 21:17:38 +0800 Message-ID: <20201012131739.1655-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 1c7dda972c92856..81d09434c5c610d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -216,8 +216,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; @@ -225,8 +225,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b02000 0x1000>; interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From patchwork Mon Oct 12 13:17:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317633 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616848ilm; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIJo11rhHNiiMqTBCtL2LAj/SVPW4aZ+Xs3UOBa2RCNZFqkIqabhBEOhz6rPRAyrZM4nDV X-Received: by 2002:aa7:dc18:: with SMTP id b24mr14403519edu.285.1602508806002; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508805; cv=none; d=google.com; s=arc-20160816; b=vo2qMzMiawvDbw4lUeyBxGLD4QV9Rz1DQXSg1RkPX8VOCemya2/B1S7N5c4cKCnTMk 8+0T1WcvBnCzujerI6v5brLFHdDay/0r5OaxOQnA7684nEzXUEQygkKllMjCZ6N+GB8E kSJxqaDrdNKk7u5SXUPYqI2y7Q8VO40ecSvl+DQTgdZQcxU7P1hNBXp7IbcC/w7AhBwp O2h/5Ywa2myM9MeJvT6pQ5Oqohca82PIyfrmg0JXrysbgXd7lcBac4N2kmRSnVq5Q0jt 1xUNJuCbn2UMjbvNIyZWUbOyoojN02BYPv4fb7lasV9ySvwyzFxngDO21fV9jB1hMmpN PKSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nPnPeqJfUPpUWYnp+1SgNMTLWJo/0M4HlOmNwYKWAm4=; b=09+dyhHqP6UITsP422ZKllKAhOu8Jii7fIMh4L/DC41cCNUbowT+kputR033L82FbI eJuZ90/Dc7SW05GpM8db40tIw7Z5uYxEzDKDPrgBi2BZf16mrhLJqWRajFzYJsRKSUQz 6dcxeTePqNNKRORicWclaGQlyG9p217bnHx5H4TivP3gMyXZ9ZpMnXslqjbmcEwxAUpt NUiYCwDHuihzBMCO8HEz2R1BNi9naHjTy6BpE0VBnr7aVsU1C1MOZ+KIyZiFbGyYngeg 0X6kvgebEzp9i8eE9ieNB9hSop8nqt7/OD9zoXCanq/wPsVCdnfLf30s7TPXUCmBgxt7 39kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.05; Mon, 12 Oct 2020 06:20:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388389AbgJLNTt (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:49 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:15279 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388892AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C9C39797ABAAB2713AE6; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:29 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 11/11] arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml Date: Mon, 12 Oct 2020 21:17:39 +0800 Message-ID: <20201012131739.1655-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 26caf09e9511b3c..c073d6d8b55c0b4 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -300,8 +300,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -311,8 +311,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";