From patchwork Wed Nov 25 17:48:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 333236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84A15C64E7C for ; Thu, 26 Nov 2020 02:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3E1C92075A for ; Thu, 26 Nov 2020 02:13:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SNBsC6UV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732902AbgKZCM2 (ORCPT ); Wed, 25 Nov 2020 21:12:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732838AbgKZCM0 (ORCPT ); Wed, 25 Nov 2020 21:12:26 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 610E2C0613D4; Wed, 25 Nov 2020 18:12:26 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id q16so533084edv.10; Wed, 25 Nov 2020 18:12:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RAarhppgBK7+aX8M/sAYyN7ZA+uJCDtTAY1PkQ2qLQw=; b=SNBsC6UVQD2oAq98zCCCBBxHADzjs4AGPCIAfGWmyzOssx2F4xFcSh6vppd+krG/wR ScCrRtRxI+EMWpWNhGgRO4UcDhHfXMR8JzDONwsq2vAuV5/YGm5AUh1PpcO/FxcL2V88 JXqMMxRAlKQtfUyf2kA8eNHfCIo220Y1NJ0PWz2Aq7uVffjwbIRSKFu1LpbGcbP9Yu/+ PnNqRgR/BE8SfVHMALhDNlWNWNpeQrIbL0IM/0fXmAEWcXvwdXXVpj38fEMJzFvIhzMP FJs3GTkb7VhDDrdDiiVhu8TXA0He6fDXgtA6Vll3l37fB1m1rsqTvdbr+iKz4rrh/012 ZMZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RAarhppgBK7+aX8M/sAYyN7ZA+uJCDtTAY1PkQ2qLQw=; b=pXYoRqul5II0yYExdjNE6pIYz0ChzxzVaJU12FWYIzzatNKp9cK6wnAqhV294n4LcI avzehQyD7a6Y1HydJvNWfD7FEVGkvtw6OBhx+zzAW9NT3JEni2YoA+M5I5R/YasFDUad BbPY7yuWIq549J6XrzWxgvM8/AFNI67U7qiEmF8gC8BK4Y9mmpNzH2+isG8aERCkIeXc e0r0xbnBOL0rzGhZ2JKKoo8bFSpWO3/cDk6fceS8V17JaxsZdc8Co1cu6dMmChZMb0Ie ow71gwBb/kiZ7caI/F15YL3XFqi163KN34zdImQVjDtKJ+78tGGDC9mPGp9f1ULSXWOr J2xw== X-Gm-Message-State: AOAM533juRGkV21RWy+SLAbAuMsyj7HFw8nV4JkciXkFbbmLZ4TugBlv xTNs6gQF5J0jEKbJO4SmKiE= X-Google-Smtp-Source: ABdhPJyoiyLD05+CDmcehT6U9g5YXacwvxvoTS+FMElcbdi4JGSRbambxMDI4brGyTkzIkrXg+6l0Q== X-Received: by 2002:a50:c050:: with SMTP id u16mr482267edd.177.1606356744957; Wed, 25 Nov 2020 18:12:24 -0800 (PST) Received: from ansuel-xps20.localdomain (93-39-149-95.ip76.fastwebnet.it. [93.39.149.95]) by smtp.googlemail.com with ESMTPSA id d7sm417276edv.17.2020.11.25.18.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 18:12:24 -0800 (PST) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/8] drivers: thermal: tsens: Add VER_0 tsens version Date: Wed, 25 Nov 2020 18:48:18 +0100 Message-Id: <20201125174826.24462-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125174826.24462-1-ansuelsmth@gmail.com> References: <20201125174826.24462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org VER_0 is used to describe device based on tsens version before v0.1. These device are devices based on msm8960 for example apq8064 or ipq806x. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 166 +++++++++++++++++++++++++++++------ drivers/thermal/qcom/tsens.h | 8 +- 2 files changed, 146 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index d8ce3a687b80..bda965b3ac05 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", hw_id, __func__, temp); } + + if (tsens_version(priv) < VER_0_1) { + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + break; + } } return IRQ_HANDLED; @@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + if (tsens_version(priv) < VER_0_1) { + /* Pre v0.1 IP had a single register for each type of interrupt + * and thresholds + */ + hw_id = 0; + } + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); @@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp) u32 valid; int ret; - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; - while (!valid) { - /* Valid bit is 0 for 6 AHB clock cycles. - * At 19.2MHz, 1 AHB clock is ~60ns. - * We should enter this loop very, very rarely. - */ - ndelay(400); + /* VER_0 doesn't have VALID bit */ + if (tsens_version(priv) >= VER_0_1) { ret = regmap_field_read(priv->rf[valid_idx], &valid); if (ret) return ret; + while (!valid) { + /* Valid bit is 0 for 6 AHB clock cycles. + * At 19.2MHz, 1 AHB clock is ~60ns. + * We should enter this loop very, very rarely. + */ + ndelay(400); + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; + } } /* Valid bit is set, OK to read the temperature */ @@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; int hw_id = s->hw_id; - int last_temp = 0, ret; + int last_temp = 0, ret, trdy; + unsigned long timeout; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); - if (ret) - return ret; + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); + do { + if (priv->rf[TRDY]) { + ret = regmap_field_read(priv->rf[TRDY], &trdy); + if (ret) + return ret; + if (!trdy) + continue; + } + + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); + if (ret) + return ret; - *temp = code_to_degc(last_temp, s) * 1000; + *temp = code_to_degc(last_temp, s) * 1000; - return 0; + return 0; + } while (time_before(jiffies, timeout)); + + return -ETIMEDOUT; } #ifdef CONFIG_DEBUG_FS @@ -738,19 +772,31 @@ int __init init_common(struct tsens_priv *priv) priv->tm_offset = 0x1000; } - res = platform_get_resource(op, IORESOURCE_MEM, 0); - tm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(tm_base)) { - ret = PTR_ERR(tm_base); - goto err_put_device; + if (tsens_version(priv) >= VER_0_1) { + res = platform_get_resource(op, IORESOURCE_MEM, 0); + tm_base = devm_ioremap_resource(dev, res); + if (IS_ERR(tm_base)) { + ret = PTR_ERR(tm_base); + goto err_put_device; + } + + priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); + } else { /* VER_0 share the same gcc regs using a syscon */ + struct device *parent = priv->dev->parent; + + if (parent) + priv->tm_map = syscon_node_to_regmap(parent->of_node); } - priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); - if (IS_ERR(priv->tm_map)) { + if (IS_ERR_OR_NULL(priv->tm_map)) { ret = PTR_ERR(priv->tm_map); goto err_put_device; } + /* VER_0 have only tm_map */ + if (!priv->srot_map) + priv->srot_map = priv->tm_map; + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, @@ -769,6 +815,10 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[TSENS_EN]); goto err_put_device; } + /* in VER_0 TSENS need to be explicitly enabled */ + if (tsens_version(priv) == VER_0) + regmap_field_write(priv->rf[TSENS_EN], 1); + ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; @@ -791,6 +841,61 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[TSENS_EN]); + if (IS_ERR(priv->rf[TSENS_EN])) { + ret = PTR_ERR(priv->rf[TSENS_EN]); + goto err_put_device; + } + + priv->rf[TSENS_SW_RST] = devm_regmap_field_alloc( + dev, priv->tm_map, priv->fields[TSENS_EN]); + if (IS_ERR(priv->rf[TSENS_EN])) { + ret = PTR_ERR(priv->rf[TSENS_EN]); + goto err_put_device; + } + + priv->rf[LOW_INT_CLEAR_0] = devm_regmap_field_alloc( + dev, priv->tm_map, priv->fields[LOW_INT_CLEAR_0]); + if (IS_ERR(priv->rf[LOW_INT_CLEAR_0])) { + ret = PTR_ERR(priv->rf[LOW_INT_CLEAR_0]); + goto err_put_device; + } + + priv->rf[UP_INT_CLEAR_0] = devm_regmap_field_alloc( + dev, priv->tm_map, priv->fields[UP_INT_CLEAR_0]); + if (IS_ERR(priv->rf[UP_INT_CLEAR_0])) { + ret = PTR_ERR(priv->rf[UP_INT_CLEAR_0]); + goto err_put_device; + } + + /* VER_0 require to set MIN and MAX THRESH */ + if (tsens_version(priv) < VER_0_1) { + priv->rf[MIN_THRESH_0] = devm_regmap_field_alloc( + dev, priv->tm_map, priv->fields[MIN_THRESH_0]); + if (IS_ERR(priv->rf[MIN_THRESH_0])) { + ret = PTR_ERR(priv->rf[MIN_THRESH_0]); + goto err_put_device; + } + + priv->rf[MAX_THRESH_0] = devm_regmap_field_alloc( + dev, priv->tm_map, priv->fields[MAX_THRESH_0]); + if (IS_ERR(priv->rf[MAX_THRESH_0])) { + ret = PTR_ERR(priv->rf[MAX_THRESH_0]); + goto err_put_device; + } + + regmap_field_write(priv->rf[MIN_THRESH_0], 0); + regmap_field_write(priv->rf[MAX_THRESH_0], 120000); + } + + priv->rf[TRDY] = + devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]); + if (IS_ERR(priv->rf[TRDY])) { + ret = PTR_ERR(priv->rf[TRDY]); + goto err_put_device; + } + /* This loop might need changes if enum regfield_ids is reordered */ for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -844,7 +949,11 @@ int __init init_common(struct tsens_priv *priv) } spin_lock_init(&priv->ul_lock); - tsens_enable_irq(priv); + + /* VER_0 interrupt doesn't need to be enabled */ + if (tsens_version(priv) >= VER_0_1) + tsens_enable_irq(priv); + tsens_debug_init(op); err_put_device: @@ -930,7 +1039,7 @@ static int tsens_register_irq(struct tsens_priv *priv, char *irqname, irq_handler_t thread_fn) { struct platform_device *pdev; - int ret, irq; + int ret, irq, irq_type = IRQF_ONESHOT; pdev = of_find_device_by_node(priv->dev->of_node); if (!pdev) @@ -943,9 +1052,12 @@ static int tsens_register_irq(struct tsens_priv *priv, char *irqname, if (irq == -ENXIO) ret = 0; } else { - ret = devm_request_threaded_irq(&pdev->dev, irq, - NULL, thread_fn, - IRQF_ONESHOT, + /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */ + if (tsens_version(priv) == VER_0) + irq_type = IRQF_TRIGGER_RISING; + + ret = devm_request_threaded_irq(&pdev->dev, irq, thread_fn, + NULL, irq_type, dev_name(&pdev->dev), priv); if (ret) dev_err(&pdev->dev, "%s: failed to get irq\n", diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f40b625f897e..42c12639582f 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,6 +13,7 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define TIMEOUT_US 100 #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 @@ -25,7 +26,8 @@ struct tsens_priv; /* IP version numbers in ascending order */ enum tsens_ver { - VER_0_1 = 0, + VER_0 = 0, + VER_0_1, VER_1_X, VER_2_X, }; @@ -441,6 +443,10 @@ enum regfield_ids { CRIT_THRESH_14, CRIT_THRESH_15, + /* VER_0 MIN MAX THRESH */ + MIN_THRESH_0, + MAX_THRESH_0, + /* WATCHDOG */ WDOG_BARK_STATUS, WDOG_BARK_CLEAR, From patchwork Wed Nov 25 17:48:19 2020 Content-Type: text/plain; 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[93.39.149.95]) by smtp.googlemail.com with ESMTPSA id d7sm417276edv.17.2020.11.25.18.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 18:12:26 -0800 (PST) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/8] drivers: thermal: tsens: Don't hardcode sensor slope Date: Wed, 25 Nov 2020 18:48:19 +0100 Message-Id: <20201125174826.24462-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125174826.24462-1-ansuelsmth@gmail.com> References: <20201125174826.24462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Function compute_intercept_slope hardcode the sensor slope to SLOPE_DEFAULT. Change this and use the default value only if a slope is not defined. This is needed for tsens VER_0 that has a hardcoded slope table. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index bda965b3ac05..80551e17cdbe 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, "%s: sensor%d - data_point1:%#x data_point2:%#x\n", __func__, i, p1[i], p2[i]); - priv->sensor[i].slope = SLOPE_DEFAULT; + if (!priv->sensor[i].slope) + priv->sensor[i].slope = SLOPE_DEFAULT; if (mode == TWO_PT_CALIB) { /* * slope (m) = adc_code2 - adc_code1 (y2 - y1)/ From patchwork Wed Nov 25 17:48:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 333238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D10C83014 for ; Thu, 26 Nov 2020 02:12:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B20FA207BC for ; Thu, 26 Nov 2020 02:12:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IVWWFORN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733143AbgKZCMf (ORCPT ); Wed, 25 Nov 2020 21:12:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732838AbgKZCMe (ORCPT ); Wed, 25 Nov 2020 21:12:34 -0500 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBB8CC0613D4; Wed, 25 Nov 2020 18:12:33 -0800 (PST) Received: by mail-ej1-x643.google.com with SMTP id oq3so608830ejb.7; Wed, 25 Nov 2020 18:12:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ILjgLO1gu3OAaJ22R8SZw9mkrx615wQIxgl8+dYN3Gg=; b=IVWWFORNV5BHhFaYS+NvMN3osEnjqv7jCERz48upU8l2dI5uDmpS2Fr24s95chsXFi FBxQ+H54wYOPVxTQ7LzyxGGY162GbqGLaTbP/oSAmYPFAGSiTtq1PW34z+lecYeNa3k0 wqgeO7PSvwj2xZEMuyT1fQVJU9IUftjG3qd0A3QcAusd+AWhUKm7dUZJ3idaOobjqWbb ITH/QEKj9DUA4CicU6sCUSimcr8riZoF254Q0ALKPg3uj6dgVZ03NQUIGdkkmnMo+NZR DyBgICtW98GGYWW7hQgyCVAp/t6RUCCRrBblZm3M8XitZapYntGtGFhBYkVJ62/GixcL alQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ILjgLO1gu3OAaJ22R8SZw9mkrx615wQIxgl8+dYN3Gg=; b=sZwWIHV5PQaOOzi3Rr6iEHerbZc7p8HkOVwcyuwTg/JQ7IWYe5sVIRJkBiXphRXHEM MQN1tAn8szrju6iOt5AUnPZg1NYPVxUjvrEV2qlSvTfj86yqvWv3tBcVzRi2ZtLCrUmG yehOJwZu/kjBPq9sE0zpglla9oiAqzyUxBReMBR3twJZVRZYkroQZjywmV8R13x0l9PV A28CQajPd8NUHhS+0k4NowRAZDZOzqC+UapN+fTVxjaoMcsDMZfCV6Re2hnH0MKuvLjI wmr+e4RV1wDhWy9jTCBnJyIXaBqZuRVMD1K04/JCRyId/mawFXsiX+xQn/LB1+bpQMM7 MfGg== X-Gm-Message-State: AOAM533HXEA61qj2NWX48HpDMx38f5DBz+dcrAVomsZrwBuIhEsaM39o 6KMcT4E7gUJV+AJrSnKmhuE= X-Google-Smtp-Source: ABdhPJxbDo53ZIGywt/XVzIMgDLvC5bng5aRcQkFz7cZYZDdlAMe6RlLz245mtl3Zqpim/SmadiRJw== X-Received: by 2002:a17:906:7b49:: with SMTP id n9mr730677ejo.418.1606356752572; Wed, 25 Nov 2020 18:12:32 -0800 (PST) Received: from ansuel-xps20.localdomain (93-39-149-95.ip76.fastwebnet.it. [93.39.149.95]) by smtp.googlemail.com with ESMTPSA id d7sm417276edv.17.2020.11.25.18.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 18:12:31 -0800 (PST) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 5/8] drivers: thermal: tsens: Fix bug in sensor enable for msm8960 Date: Wed, 25 Nov 2020 18:48:22 +0100 Message-Id: <20201125174826.24462-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125174826.24462-1-ansuelsmth@gmail.com> References: <20201125174826.24462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's present a hardware bug in tsens VER_0 where if sensors upper to id 6 are enabled selectively, underfined results are expected. Fix this by enabling all the remaining sensor in one step. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 93d2c6c7d1bd..f786f44f5d5d 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -27,9 +27,9 @@ #define EN BIT(0) #define SW_RST BIT(1) #define SENSOR0_EN BIT(3) +#define MEASURE_PERIOD BIT(18) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) -#define MEASURE_PERIOD 1 #define SENSOR0_SHIFT 3 /* INT_STATUS_ADDR bitmasks */ @@ -132,11 +132,26 @@ static int enable_8960(struct tsens_priv *priv, int id) if (ret) return ret; - mask = BIT(id + SENSOR0_SHIFT); + /* HARDWARE BUG: + * On platform with more than 5 sensors, all the remaining + * sensors needs to be enabled all togheder or underfined + * results are expected. (Sensor 6-7 disabled, Sensor 3 + * disabled...) In the original driver, all the sensors + * are enabled in one step hence this bug is not triggered. + */ + if (id > 5) + mask = GENMASK(10, 6); + else + mask = BIT(id); + + mask <<= SENSOR0_SHIFT; + ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); if (ret) return ret; + reg |= MEASURE_PERIOD; + if (priv->num_sensors > 1) reg |= mask | SLP_CLK_ENA | EN; else From patchwork Wed Nov 25 17:48:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 333237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF98C83011 for ; Thu, 26 Nov 2020 02:12:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D2F6207BC for ; Thu, 26 Nov 2020 02:12:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VFEEaZJn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733171AbgKZCMg (ORCPT ); Wed, 25 Nov 2020 21:12:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732838AbgKZCMg (ORCPT ); Wed, 25 Nov 2020 21:12:36 -0500 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B44A0C0613D4; Wed, 25 Nov 2020 18:12:35 -0800 (PST) Received: by mail-ej1-x642.google.com with SMTP id mc24so621986ejb.6; Wed, 25 Nov 2020 18:12:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=18mjJQ2LV7K44mzxIFRG9iVwB1Fl7ExfbKXsXQSaBWY=; b=VFEEaZJnQLGknvWEhR3vwlpib/YvHL9G5/+B/P2XdKjwGZPzD1sucFuNAas/mqgRBV 4LNHYvZqBQlsXW5KDnr5UO6ckuZV64BO7FGDwMyrlSUjqx3LhyRVh/77+gU/0BEG/R2g AiHw4JtUk1POMDj0gz8iTtKnZR5eJTEHTo3AUnoem30/luugzWHXnLbiTPlJI0iLCr8y kHZPIwp2vk3w73eTvgR1kMf5/yqXpD7i42l4UhyFxE/BU04WiEBFp2xikmu5NAjg2eZ+ QbaYm3WdTYr+F4xiZZBDobhJMjpAcxRKgIXp1pJlTl4IuxDEe7mzoXslmxb1gonWpONQ n4Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=18mjJQ2LV7K44mzxIFRG9iVwB1Fl7ExfbKXsXQSaBWY=; b=mHy3dnHxlrVbyAEMERODIPFdsL1uoZh3D4b3/s7CN2Aulo5GyDyUqR1sVxR5FxQ/2W 3jI5XbGQhm8aU0uqjgDWoVHm+A+dTem7cHKFCq2wVDWI3R0OUd3fOXC5yS2JHsEp2Ci+ TmU9NR0s7IIKlfIZU0ZYZH3wX1b/2pXL6l3IvhOwmhJXXbOodPbzOy/b/TjF983F67xE AN5LCW99LkB8kl3ewdBE4gEVWhs+6tMDAU4AAJdXm+m3aYDmQWY3fhCDv4Ijlk1+cLnk J2sZ3KTq1jf85Xkt7hEAyhl1N+6FwUQjsm5GYez1dXzNcNOe0OYYjN9dhOcfkQq2m+Tf GLtw== X-Gm-Message-State: AOAM532QkBoCzV3uyv/WBj5nJz5NqKrD9GpYprtVARZAeUl92pj/ska+ H4KEBTTZBkTG/+qbKinl6OjhTUdiFAAssg== X-Google-Smtp-Source: ABdhPJyx3iQ4SToqZSbz6dUucuv5772OZh4Yx2yNaCi56Wr42/0zVyLnVbg3xUrvGGJErwt6l2tLMA== X-Received: by 2002:a17:906:5a97:: with SMTP id l23mr772423ejq.232.1606356754395; Wed, 25 Nov 2020 18:12:34 -0800 (PST) Received: from ansuel-xps20.localdomain (93-39-149-95.ip76.fastwebnet.it. [93.39.149.95]) by smtp.googlemail.com with ESMTPSA id d7sm417276edv.17.2020.11.25.18.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 18:12:33 -0800 (PST) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 6/8] driver: thermal: tsens: Use get_temp_common for msm8960 Date: Wed, 25 Nov 2020 18:48:23 +0100 Message-Id: <20201125174826.24462-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125174826.24462-1-ansuelsmth@gmail.com> References: <20201125174826.24462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rework calibrate function to use common function. Derive the offset from a missing hardcoded slope table and the data from the nvmem calib efuses. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 56 +++++++++---------------------- 1 file changed, 15 insertions(+), 41 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index f786f44f5d5d..4cd2cc14bc4c 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -67,6 +67,13 @@ #define S9_STATUS_OFF 0x3674 #define S10_STATUS_OFF 0x3678 +/* Original slope - 200 to compensate mC to C inaccuracy */ +u32 tsens_msm8960_slope[] = { + 976, 976, 954, 976, + 911, 932, 932, 999, + 932, 999, 932 + }; + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -192,9 +199,7 @@ static int calibrate_8960(struct tsens_priv *priv) { int i; char *data; - - ssize_t num_read = priv->num_sensors; - struct tsens_sensor *s = priv->sensor; + u32 p1[11]; data = qfprom_read(priv->dev, "calib"); if (IS_ERR(data)) @@ -202,49 +207,18 @@ static int calibrate_8960(struct tsens_priv *priv) if (IS_ERR(data)) return PTR_ERR(data); - for (i = 0; i < num_read; i++, s++) - s->offset = data[i]; + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = data[i]; + priv->sensor[i].slope = tsens_msm8960_slope[i]; + } + + compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB); kfree(data); return 0; } -/* Temperature on y axis and ADC-code on x-axis */ -static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) -{ - int slope, offset; - - slope = thermal_zone_get_slope(s->tzd); - offset = CAL_MDEGC - slope * s->offset; - - return adc_code * slope + offset; -} - -static int get_temp_8960(const struct tsens_sensor *s, int *temp) -{ - int ret; - u32 code, trdy; - struct tsens_priv *priv = s->priv; - unsigned long timeout; - - timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); - do { - ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy); - if (ret) - return ret; - if (!(trdy & TRDY_MASK)) - continue; - ret = regmap_read(priv->tm_map, s->status, &code); - if (ret) - return ret; - *temp = code_to_mdegC(code, s); - return 0; - } while (time_before(jiffies, timeout)); - - return -ETIMEDOUT; -} - static struct tsens_features tsens_8960_feat = { .ver_major = VER_0, .crit_int = 0, @@ -308,7 +282,7 @@ static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = { static const struct tsens_ops ops_8960 = { .init = init_common, .calibrate = calibrate_8960, - .get_temp = get_temp_8960, + .get_temp = get_temp_common, .enable = enable_8960, .disable = disable_8960, .suspend = suspend_8960, From patchwork Wed Nov 25 17:48:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 333239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED162C8300F for ; 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[93.39.149.95]) by smtp.googlemail.com with ESMTPSA id d7sm417276edv.17.2020.11.25.18.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 18:12:37 -0800 (PST) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 8/8] dt-bindings: thermal: tsens: Document ipq8064 bindings Date: Wed, 25 Nov 2020 18:48:25 +0100 Message-Id: <20201125174826.24462-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125174826.24462-1-ansuelsmth@gmail.com> References: <20201125174826.24462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the use of bindings used for msm8960 tsens based devices. msm8960 use the same gcc regs and is set as a child of the qcom gcc. Signed-off-by: Ansuel Smith --- .../bindings/thermal/qcom-tsens.yaml | 103 ++++++++++++++---- 1 file changed, 79 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 95462e071ab4..3aacee5c0632 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -19,6 +19,11 @@ description: | properties: compatible: oneOf: + - description: msm9860 TSENS based + items: + - enum: + - qcom,ipq8064-tsens + - description: v0.1 of TSENS items: - enum: @@ -71,9 +76,6 @@ properties: nvmem-cell-names: minItems: 1 maxItems: 2 - items: - - const: calib - - const: calib_sel "#qcom,sensors": description: @@ -88,43 +90,96 @@ properties: Number of cells required to uniquely identify the thermal sensors. Since we have multiple sensors this is set to 1 +required: + - compatible + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - "#qcom,sensors" + allOf: - if: properties: compatible: contains: enum: - - qcom,msm8916-tsens - - qcom,msm8974-tsens - - qcom,msm8976-tsens - - qcom,qcs404-tsens - - qcom,tsens-v0_1 - - qcom,tsens-v1 + - qcom,ipq8064-tsens then: properties: - interrupts: - maxItems: 1 - interrupt-names: - maxItems: 1 + nvmem-cell-names: + items: + - const: calib + - const: calib_backup else: properties: - interrupts: - minItems: 2 - interrupt-names: - minItems: 2 + nvmem-cell-names: + items: + - const: calib + - const: calib_sel -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-tsens + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - qcom,msm8976-tsens + - qcom,qcs404-tsens + - qcom,tsens-v0_1 + - qcom,tsens-v1 + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + + else: + properties: + interrupts: + minItems: 2 + interrupt-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,tsens-v0_1 + - qcom,tsens-v1 + - qcom,tsens-v2 + + then: + required: + - reg additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + gcc: clock-controller { + + /* ... */ + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + - | #include // Example 1 (legacy: for pre v1 IP):