From patchwork Tue Jan 30 12:07:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 126217 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3300544ljd; Tue, 30 Jan 2018 04:09:01 -0800 (PST) X-Google-Smtp-Source: AH8x226ip3lTczo6qJcLErlM/XLkJrHBcFQRa/mXt+UPSwsjQOGjkqyLmGI4YSpTq6V66AQY/GLc X-Received: by 10.98.242.2 with SMTP id m2mr30680410pfh.102.1517314141438; Tue, 30 Jan 2018 04:09:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517314141; cv=none; d=google.com; s=arc-20160816; b=rmyX8z9nNhOaOduJktbTDztt5jVQK6uzoMv4DIikjlqbt0T3IqOdpKCMBegZ9qaTrU YRL/RIQNuQydShGL2tTmYzFw/4xz+TmuVbj5lOT/qEkrP/TOSLiiOWWOEbsyGZAah9NI lh3/MUlGWFK6BEO2kz0kwftJpu8OkmF/k9cFv4cZi7E4or0cnE8pP+w1DSRn48o/yTBk Mg9QrE/JSm6jo2tJTZsSFFNVXlx8pBy7r5K3b5ZrrR4IwU4vwcqvf+Bm8PUqBt/KGqCe ofO+WzhNlLRyZ9KQZHrWt/7JFSffzMSDXqZ82eTvXXZDvAPHOi8n9fliAfKFZkQrpogj r9Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=MJbec79m7RGDG5cB4OoY6gWoIWxfDLn972BtMdWwpO4=; b=bft5MFVp0MqFqOQGZl+dw0cheAQz7OFjy2WaF4LyOms0BY3YTzwXM+z9eAcnm2ZvKM 7zf0QIifRsB1QCZlgkU9o+5KfOJ4KlYDukX3jYKhMolKy9a9hW23guYsFhfd42yLapWj 8Er3SoSq0mccdraOYU+/v9rECvlVmpQNMv3tflQ2J0YKvPvHikb1knO24ijiC0yHF9HP 62yI3WIaOfk4y70XgMm1q8Ts5Id9yD9H+9mfqzpZsNkRlXUF5IucdPgpXl3hAqvaf1si GXyVfsnSG9ZmfcuxEunPBPkUxHX/1OIoVePj++jpw7qqDeQKdJaTEkM5wEnqd3Y23SKV vssQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JSIhNGKF; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg5-v6si2125659plb.822.2018.01.30.04.09.00; Tue, 30 Jan 2018 04:09:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JSIhNGKF; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751798AbeA3MI7 (ORCPT + 6 others); Tue, 30 Jan 2018 07:08:59 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:45793 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751796AbeA3MI5 (ORCPT ); Tue, 30 Jan 2018 07:08:57 -0500 Received: by mail-pf0-f193.google.com with SMTP id a88so8705538pfe.12 for ; Tue, 30 Jan 2018 04:08:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Fw+oTKOcD9WPc+Cak6Evz27nASVE/9LUbVzUjk3BZCU=; b=JSIhNGKF/rZQjpkDSkPKuMcbTXZ+9V2D4ufiVuyF0O5gE2TRaWyc8ROlX7EWW8bJu0 oNrLEhWQsQr6n291W6wSMum7FvHJF8C1aWJLMCy/V7vpinkXo0T41LqEp/zDwxUW9O46 84QDxpjuc+ErC8H6L0d4OZOMbBgyaBbZGK9BY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Fw+oTKOcD9WPc+Cak6Evz27nASVE/9LUbVzUjk3BZCU=; b=FwxDjWTjEi/ecEKHWNdmw847xWOJ0FYv8O5XsSKQGz09Tg5ngKdepwDZY3bSKSYDPk m4/QnMv06nb+2Of9lZ8nw50oCtiK1fi5EtxuCRzY2opstsGd+lQQos/BCJgycyXzJbwd OscPGJ4ksFpUCMJyspH706xJmoSR2rHbx1koA12TcT/VX/R0Bg8GPg2AlAtiL52faqES v0FpVv8WC6Bj2hJ5NoerM429frXuOWrPH1La7tOQjvn4E0Au3Y2aOnmfvaigX1MFGhtu dL/MOQoHxv5Zvv8MEz44UmKYcdfvXwaLE45AGVHuZYapb+SV5psSJ87K0AoeS6oR+hxS 29yg== X-Gm-Message-State: AKwxyte9bCccrGKnaCBJKJXqHOvlObVZUHFbHuDzuZX48QVuGaJ3bTza 5KgrM87yk7ENd6ohUTjIhBzxpA== X-Received: by 10.98.59.80 with SMTP id i77mr30418301pfa.146.1517314136463; Tue, 30 Jan 2018 04:08:56 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id y1sm22961534pge.78.2018.01.30.04.08.53 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Jan 2018 04:08:55 -0800 (PST) From: Baolin Wang To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org Subject: [PATCH 1/2] dt-bindings: gpio: Add Spreadtrum GPIO controller documentation Date: Tue, 30 Jan 2018 20:07:42 +0800 Message-Id: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the device tree bindings for the Spreadtrum GPIO controller. The gpios will be supported by the GPIO generic library. Signed-off-by: Baolin Wang --- .../devicetree/bindings/gpio/gpio-sprd.txt | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sprd.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt new file mode 100644 index 0000000..eca97d4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt @@ -0,0 +1,28 @@ +Spreadtrum GPIO controller bindings + +The controller's registers are organized as sets of sixteen 16-bit +registers with each set controlling a bank of up to 16 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: +- compatible: Should be "sprd,sc9860-gpio". +- reg: Define the base and range of the I/O address space containing +the GPIO controller registers. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the gpio number and +the second cell is used to specify optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be <2>. Specifies the number of cells needed +to encode interrupt source. +- interrupts: Should be the port interrupt shared by all the gpios. + +Example: + ap_gpio: gpio@40280000 { + compatible = "sprd,sc9860-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; From patchwork Tue Jan 30 12:07:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 126218 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3300594ljd; Tue, 30 Jan 2018 04:09:05 -0800 (PST) X-Google-Smtp-Source: AH8x226KeoKWIKiSYb7IVnwPo4z10WixnBhjmzwJAZNTRb0izbpaMN+FH1uU7/YrM+L7o8XvCaDA X-Received: by 2002:a17:902:2bc5:: with SMTP id l63-v6mr18002274plb.108.1517314145248; Tue, 30 Jan 2018 04:09:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517314145; cv=none; d=google.com; s=arc-20160816; b=mbE911WVBJo1MxGKubKFc9SnbAsN+y6ag1y5uO+pNbVldK9Vyk7+T7h9GH4PzXGSBD onWSlNIlL8f7Y8gcrdtlVU0vYuenfUIgbh4ph9dUsvXgC3pZEVhETDITjRoYkZdvkobW K4uZaBzmqpKrNhlHQJCEO6/Njb4NMCFIq3kHD0UuzNgswxndG/Rvu+4Z0Ku9jK74YtZG WjGQOsZWzBZJ0REcesCuXtkSz2WVSEynOKBbPoklYqw1w9G6WONNKitclRJCCwuVXNci jRYO191eiS2Y2jWVkxtF2y0zlAVtN5ylim5vBVWD0Ym/GmdgukOYV9e4ERFAXuU83jaW 7Row== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=OMj8Qpeo93ZcEQ3voXqXwWcKPmDKSpYC7KjA6u0r/qs=; b=QJDD+CYu6n0zar5H5XjuDqOsVnOPBtXGLwA9Pl2idTcWANGERJZYLOVFiVgTixKTdF 3r/Ju25CTOid7uaVKOm+bc4mGLtEfKGOBoSvN9z6cjVwwxlx5jYEPATZvcs/0ey2hhQJ By2OAapJ7bmTCOaBje71dd8bJuGYQ0wuKvH+DR7PVbnHHy9JbXRtRQ2yw68GCoCox5u7 Qeqik/1zCY/BAVCrgJvgb4Ojgw7XoWfZus5QgLPTaNTp+Lck/oSx5QIesSZ/iVnHJuoH qvR2csdd0jwLEDgobpHIIQEBjsGBIL2wEhoRcnu1ZZ/eAHW5qGJfJWVQ9aGbNm4r1Tu6 9q0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ic/08LdO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i135si9191019pgc.459.2018.01.30.04.09.05; Tue, 30 Jan 2018 04:09:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ic/08LdO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751858AbeA3MJD (ORCPT + 6 others); Tue, 30 Jan 2018 07:09:03 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:42595 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751832AbeA3MJA (ORCPT ); Tue, 30 Jan 2018 07:09:00 -0500 Received: by mail-pg0-f66.google.com with SMTP id j16so5666354pgn.9 for ; Tue, 30 Jan 2018 04:09:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=rMGVfSsjiBd0lKDI+p2K2Smlggzk9hMIOb8jLFL/buA=; b=Ic/08LdOEj+z2uG4t1jeWoRHT8QET/NA/OxcPNlQuZ8CPZS9NKIubeLfvouPVOCUpT 5wT91bOpRZ8PUimKm1KZRloJmVglT1Z/YSYmaJ/2kb4BpJ3fl8zNF8C6k2W6j9b5lPgj 5jPZ8hbhFq2DrGt/p9BaXo4bSrS8m6CWZUpSQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=rMGVfSsjiBd0lKDI+p2K2Smlggzk9hMIOb8jLFL/buA=; b=MTnzo9p+GBmHzNFjDNNXa4pdFocOG9N+V4Sxu/UkZYrvhV8b7D0b5GqjofTbBLLMCR vf4dKRTmYy5omtboeIG4bLWiEzqaqrRgSO8JxgbmYImCqRF4vn6SOO/AY7O5x3QPo5Tk o/y0Z4Hw+ZWyE0havdy1QHy7mcYVoTsSbsuFueS/0qk/eUO1OXMYKF67VVdgc4blPYMZ l0OzWHczs1gb17sAQPlBz39y+ChClqDvlvsxCX3M4Fy8/Cl6SSgeKSkQk2lDg1kgqzeu awZPuRvbSH6+4LoYmy5at/vsXhI9P7twFnasqEo9Tiip8j8guzWifKNseNk2zYOLvy3a T72A== X-Gm-Message-State: AKwxytewmv2ch+4zJ2D6CfGM1S8LBdB4VnEu137o3Su+VWfW0Wq/TDrD 07SJ52YZ8RKNk52FVE/jIcYLiw== X-Received: by 10.98.246.8 with SMTP id x8mr29807020pfh.234.1517314139818; Tue, 30 Jan 2018 04:08:59 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id y1sm22961534pge.78.2018.01.30.04.08.56 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Jan 2018 04:08:59 -0800 (PST) From: Baolin Wang To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org Subject: [PATCH 2/2] gpio: Add GPIO driver for Spreadtrum SC9860 platform Date: Tue, 30 Jan 2018 20:07:43 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> References: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> In-Reply-To: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> References: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Spreadtrum SC9860 platform GPIO controller contains 16 groups and each group contains 16 GPIOs. Each GPIO can set input/output and has the interrupt capability. Signed-off-by: Baolin Wang --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-sprd.c | 301 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 drivers/gpio/gpio-sprd.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Andy Shevchenko diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d6a8e85..3bece19 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -404,6 +404,13 @@ config GPIO_SPEAR_SPICS help Say yes here to support ST SPEAr SPI Chip Select as GPIO device +config GPIO_SPRD + bool "Spreadtrum GPIO support" + depends on ARCH_SPRD || COMPILE_TEST + select GPIOLIB_IRQCHIP + help + Say yes here to support Spreadtrum GPIO device. + config GPIO_STA2X11 bool "STA2x11/ConneXt GPIO support" depends on MFD_STA2X11 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4bc24fe..5b633a0 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -108,6 +108,7 @@ obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o +obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c new file mode 100644 index 0000000..af59b9f --- /dev/null +++ b/drivers/gpio/gpio-sprd.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Spreadtrum Communications Inc. + * Copyright (c) 2018 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* GPIO registers definition */ +#define SPRD_GPIO_DATA 0x0 +#define SPRD_GPIO_DMSK 0x4 +#define SPRD_GPIO_DIR 0x8 +#define SPRD_GPIO_IS 0xc +#define SPRD_GPIO_IBE 0x10 +#define SPRD_GPIO_IEV 0x14 +#define SPRD_GPIO_IE 0x18 +#define SPRD_GPIO_RIS 0x1c +#define SPRD_GPIO_MIS 0x20 +#define SPRD_GPIO_IC 0x24 +#define SPRD_GPIO_INEN 0x28 + +/* We have 16 groups GPIOs and each group contain 16 GPIOs */ +#define SPRD_GPIO_GROUP_NR 16 +#define SPRD_GPIO_NR 256 +#define SPRD_GPIO_GROUP_SIZE 0x80 +#define SPRD_GPIO_GROUP_MASK GENMASK(15, 0) +#define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_GROUP_NR - 1)) + +struct sprd_gpio { + struct gpio_chip chip; + void __iomem *base; + spinlock_t lock; + int irq; +}; + +static inline void __iomem *sprd_gpio_group_base(struct sprd_gpio *sprd_gpio, + unsigned int group) +{ + return sprd_gpio->base + SPRD_GPIO_GROUP_SIZE * group; +} + +static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, + unsigned int reg, unsigned int val) +{ + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + void __iomem *base = sprd_gpio_group_base(sprd_gpio, + offset / SPRD_GPIO_GROUP_NR); + u32 shift = SPRD_GPIO_BIT(offset); + unsigned long flags; + u32 orig, tmp; + + spin_lock_irqsave(&sprd_gpio->lock, flags); + orig = readl_relaxed(base + reg); + + tmp = (orig & ~BIT(shift)) | (val << shift); + writel_relaxed(tmp, base + reg); + spin_unlock_irqrestore(&sprd_gpio->lock, flags); +} + +static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, + unsigned int reg) +{ + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + void __iomem *base = sprd_gpio_group_base(sprd_gpio, + offset / SPRD_GPIO_GROUP_NR); + u32 value = readl_relaxed(base + reg) & SPRD_GPIO_GROUP_MASK; + u32 shift = SPRD_GPIO_BIT(offset); + + return !!(value & BIT(shift)); +} + +static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1); + return 0; +} + +static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0); +} + +static int sprd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1); + return 0; +} + +static int sprd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value); + return 0; +} + +static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA); +} + +static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value); +} + +static void sprd_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0); +} + +static void sprd_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1); +} + +static void sprd_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1); +} + +static int sprd_gpio_irq_set_type(struct irq_data *data, + unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_EDGE_FALLING: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_EDGE_BOTH: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_LEVEL_HIGH: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1); + irq_set_handler_locked(data, handle_level_irq); + break; + case IRQ_TYPE_LEVEL_LOW: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0); + irq_set_handler_locked(data, handle_level_irq); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void sprd_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + u32 group, n, girq; + + chained_irq_enter(ic, desc); + + for (group = 0; group * SPRD_GPIO_GROUP_NR < chip->ngpio; group++) { + void __iomem *base = sprd_gpio_group_base(sprd_gpio, group); + unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) & + SPRD_GPIO_GROUP_MASK; + + for_each_set_bit(n, ®, SPRD_GPIO_GROUP_NR) { + girq = irq_find_mapping(chip->irq.domain, + group * SPRD_GPIO_GROUP_NR + n); + + generic_handle_irq(girq); + } + + } + chained_irq_exit(ic, desc); +} + +static struct irq_chip sprd_gpio_irqchip = { + .name = "sprd-gpio", + .irq_ack = sprd_gpio_irq_ack, + .irq_mask = sprd_gpio_irq_mask, + .irq_unmask = sprd_gpio_irq_unmask, + .irq_set_type = sprd_gpio_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE, +}; + +static int sprd_gpio_probe(struct platform_device *pdev) +{ + struct gpio_irq_chip *irq; + struct sprd_gpio *sprd_gpio; + struct resource *res; + int ret; + + sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL); + if (!sprd_gpio) + return -ENOMEM; + + sprd_gpio->irq = platform_get_irq(pdev, 0); + if (sprd_gpio->irq < 0) { + dev_err(&pdev->dev, "Failed to get GPIO interrupt.\n"); + return sprd_gpio->irq; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sprd_gpio->base = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!sprd_gpio->base) + return -ENOMEM; + + spin_lock_init(&sprd_gpio->lock); + + sprd_gpio->chip.label = dev_name(&pdev->dev); + sprd_gpio->chip.ngpio = SPRD_GPIO_NR; + sprd_gpio->chip.base = -1; + sprd_gpio->chip.parent = &pdev->dev; + sprd_gpio->chip.of_node = pdev->dev.of_node; + sprd_gpio->chip.request = sprd_gpio_request; + sprd_gpio->chip.free = sprd_gpio_free; + sprd_gpio->chip.get = sprd_gpio_get; + sprd_gpio->chip.set = sprd_gpio_set; + sprd_gpio->chip.direction_input = sprd_gpio_direction_input; + sprd_gpio->chip.direction_output = sprd_gpio_direction_output; + + irq = &sprd_gpio->chip.irq; + irq->chip = &sprd_gpio_irqchip; + irq->handler = handle_simple_irq; + irq->default_type = IRQ_TYPE_NONE; + irq->parent_handler = sprd_gpio_irq_handler; + irq->parent_handler_data = sprd_gpio; + irq->num_parents = 1; + irq->parents = &sprd_gpio->irq; + + ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, sprd_gpio); + return 0; +} + +static const struct of_device_id sprd_gpio_of_match[] = { + { .compatible = "sprd,sc9860-gpio", }, + { /* end of list */ }, +}; +MODULE_DEVICE_TABLE(of, sprd_gpio_of_match); + +static struct platform_driver sprd_gpio_driver = { + .probe = sprd_gpio_probe, + .driver = { + .name = "sprd-gpio", + .of_match_table = sprd_gpio_of_match, + }, +}; + +static int __init sprd_gpio_init(void) +{ + return platform_driver_register(&sprd_gpio_driver); +} +subsys_initcall(sprd_gpio_init); + +static void __exit sprd_gpio_exit(void) +{ + platform_driver_unregister(&sprd_gpio_driver); +} +module_exit(sprd_gpio_exit); + +MODULE_DESCRIPTION("Spreadtrum GPIO driver"); +MODULE_LICENSE("GPL v2");