From patchwork Mon Dec 7 12:15:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 339553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5B67C4361B for ; Mon, 7 Dec 2020 12:18:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7170B2339F for ; Mon, 7 Dec 2020 12:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727759AbgLGMRf (ORCPT ); Mon, 7 Dec 2020 07:17:35 -0500 Received: from esa5.microchip.iphmx.com ([216.71.150.166]:29293 "EHLO esa5.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727058AbgLGMRd (ORCPT ); Mon, 7 Dec 2020 07:17:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1607343454; x=1638879454; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PBMnO1VSHI9r6EHfdysUn/OdEkmam+sImjFCxbEArP0=; b=oe2FPH16itDoHQcosBSIi9GOvIjGgdq7i07Xm6qlweh2ALSzon8Vh//Z FnMi8rhyuH28BYgK7ZkG2+2tTkLDP0PPeeVSZrgW+EVrNrYGbr18YzTzo 5Uyu7GQubjeBuIqGTx9+taxfBVUmItLKTjok00+M28TjWQqaDS9im1Jjv ellc8rubmuM9RkzIvKUsMWh7bL0AYWfC2OQI+6YzU44hSsJecJQtZTY7K Cs5uk5nAcFWF/ii56ewqO/o+i40nHS/UwOiAuw9uaCueORTc7PUlO1oVb 8lrYmYhGsQONBYmfsru+gPa2U70eMpaKaIWnKx3lXADCdTsT8wkEg8WiA w==; IronPort-SDR: mA1y0Ok4sZxyJrRqrHB31EEeDPdNAOKC4jjbBWUttK+BDm4I+y2CnEH1ZMXUiI/YgECj3O5Tw4 SBr423ZKs6Md/CFt4BxdKGXihLDI1O1pnSLtm5Hqhjq9EHmueJWLyR5Na8+0IGXVuewhEVZ80L jDLiSaeFVA3VypsKzWAA0fcVRfvu78WcJUbbTxH5Qw+92N1LF0qk5p1Ac0S3t9siDllj8CMg2s cdtDFb/0vkcpsThde5M7RjTf1yr9eGw/sGI21RaXjOC7zKQ0axntN3pU6Iux0zsVUOPOXVnnmC nd0= X-IronPort-AV: E=Sophos;i="5.78,399,1599548400"; d="scan'208";a="101192012" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Dec 2020 05:15:56 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 7 Dec 2020 05:15:53 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 7 Dec 2020 05:15:47 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v2 1/8] net: macb: add userio bits as platform configuration Date: Mon, 7 Dec 2020 14:15:26 +0200 Message-ID: <1607343333-26552-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> References: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is necessary for SAMA7G5 as it uses different values for PHY interface and also introduces hdfctlen bit. Signed-off-by: Claudiu Beznea Reviewed-by: Andrew Lunn --- drivers/net/ethernet/cadence/macb.h | 10 ++++++++++ drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++++++---- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 1f5da4e4f4b2..7daabffe4318 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -1147,6 +1147,14 @@ struct macb_pm_data { u32 usrio; }; +struct macb_usrio_config { + u32 mii; + u32 rmii; + u32 rgmii; + u32 refclk; + u32 hdfctlen; +}; + struct macb_config { u32 caps; unsigned int dma_burst_length; @@ -1155,6 +1163,7 @@ struct macb_config { struct clk **rx_clk, struct clk **tsu_clk); int (*init)(struct platform_device *pdev); int jumbo_max_len; + const struct macb_usrio_config *usrio; }; struct tsu_incr { @@ -1288,6 +1297,7 @@ struct macb { u32 rx_intr_mask; struct macb_pm_data pm_data; + const struct macb_usrio_config *usrio; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 7b1d195787dc..6d46153a7c4b 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -3913,15 +3913,15 @@ static int macb_init(struct platform_device *pdev) if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { val = 0; if (phy_interface_mode_is_rgmii(bp->phy_interface)) - val = GEM_BIT(RGMII); + val = bp->usrio->rgmii; else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) - val = MACB_BIT(RMII); + val = bp->usrio->rmii; else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) - val = MACB_BIT(MII); + val = bp->usrio->mii; if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) - val |= MACB_BIT(CLKEN); + val |= bp->usrio->refclk; macb_or_gem_writel(bp, USRIO, val); } @@ -4439,6 +4439,13 @@ static int fu540_c000_init(struct platform_device *pdev) return macb_init(pdev); } +static const struct macb_usrio_config macb_default_usrio = { + .mii = MACB_BIT(MII), + .rmii = MACB_BIT(RMII), + .rgmii = GEM_BIT(RGMII), + .refclk = MACB_BIT(CLKEN), +}; + static const struct macb_config fu540_c000_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | MACB_CAPS_GEM_HAS_PTP, @@ -4446,12 +4453,14 @@ static const struct macb_config fu540_c000_config = { .clk_init = fu540_c000_clk_init, .init = fu540_c000_init, .jumbo_max_len = 10240, + .usrio = &macb_default_usrio, }; static const struct macb_config at91sam9260_config = { .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config sama5d3macb_config = { @@ -4459,6 +4468,7 @@ static const struct macb_config sama5d3macb_config = { | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config pc302gem_config = { @@ -4466,6 +4476,7 @@ static const struct macb_config pc302gem_config = { .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config sama5d2_config = { @@ -4473,6 +4484,7 @@ static const struct macb_config sama5d2_config = { .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config sama5d3_config = { @@ -4482,6 +4494,7 @@ static const struct macb_config sama5d3_config = { .clk_init = macb_clk_init, .init = macb_init, .jumbo_max_len = 10240, + .usrio = &macb_default_usrio, }; static const struct macb_config sama5d4_config = { @@ -4489,18 +4502,21 @@ static const struct macb_config sama5d4_config = { .dma_burst_length = 4, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config emac_config = { .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC, .clk_init = at91ether_clk_init, .init = at91ether_init, + .usrio = &macb_default_usrio, }; static const struct macb_config np4_config = { .caps = MACB_CAPS_USRIO_DISABLED, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct macb_config zynqmp_config = { @@ -4511,6 +4527,7 @@ static const struct macb_config zynqmp_config = { .clk_init = macb_clk_init, .init = macb_init, .jumbo_max_len = 10240, + .usrio = &macb_default_usrio, }; static const struct macb_config zynq_config = { @@ -4519,6 +4536,7 @@ static const struct macb_config zynq_config = { .dma_burst_length = 16, .clk_init = macb_clk_init, .init = macb_init, + .usrio = &macb_default_usrio, }; static const struct of_device_id macb_dt_ids[] = { @@ -4640,6 +4658,8 @@ static int macb_probe(struct platform_device *pdev) bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); + bp->usrio = macb_config->usrio; + spin_lock_init(&bp->lock); /* setup capabilities */ From patchwork Mon Dec 7 12:15:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 339554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67639C433FE for ; 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IronPort-SDR: D/hLZsD+sS0lWq+irP4F2zrvqsidTlIiAmkDwnu6uxhtBE80EyS5ilzSM3RzxowME678C2/8HJ VRHXtfLshW+IUqiJNhfuFlzZj70EcNanfIScbLCgtRyLy3KniEqpgwlL1gnONQ1N/6RAL+UfKF DdXTUapMJcrJD2tMZJ8wYzZ7Nv9rw/10hZpVO/lNsCfnimDTd95gSv8NBsDo65eMCPRGii4mh4 gVztrwYiP9d7R6gKM/8/SWkulfseA0xGT+waIvpstBUBvZzDFzEnPqutPD1l5O6y1Kvg3+/FMh X4o= X-IronPort-AV: E=Sophos;i="5.78,399,1599548400"; d="scan'208";a="106497444" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Dec 2020 05:16:00 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 7 Dec 2020 05:16:00 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 7 Dec 2020 05:15:53 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v2 2/8] net: macb: add capability to not set the clock rate Date: Mon, 7 Dec 2020 14:15:27 +0200 Message-ID: <1607343333-26552-3-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> References: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or by the external clock provided by the PHY. The internal IP logic divides properly this clock depending on the link speed. The patch adds a new capability so that macb_set_tx_clock() to not be called for IPs having this capability (the clock rate, in case of generic clock, is set at the boot time via device tree and the driver only enables it). Signed-off-by: Claudiu Beznea Reviewed-by: Andrew Lunn --- drivers/net/ethernet/cadence/macb.h | 1 + drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 7daabffe4318..769694c7f86c 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -699,6 +699,7 @@ #define MACB_CAPS_GEM_HAS_PTP 0x00000040 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 +#define MACB_CAPS_CLK_HW_CHG 0x04000000 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 #define MACB_CAPS_FIFO_MODE 0x10000000 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 6d46153a7c4b..b23e986ac6dc 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -460,15 +460,14 @@ static void macb_init_buffers(struct macb *bp) /** * macb_set_tx_clk() - Set a clock to a new frequency - * @clk: Pointer to the clock to change + * @bp: pointer to struct macb * @speed: New frequency in Hz - * @dev: Pointer to the struct net_device */ -static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) +static void macb_set_tx_clk(struct macb *bp, int speed) { long ferr, rate, rate_rounded; - if (!clk) + if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) return; switch (speed) { @@ -485,7 +484,7 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) return; } - rate_rounded = clk_round_rate(clk, rate); + rate_rounded = clk_round_rate(bp->tx_clk, rate); if (rate_rounded < 0) return; @@ -495,11 +494,12 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) ferr = abs(rate_rounded - rate); ferr = DIV_ROUND_UP(ferr, rate / 100000); if (ferr > 5) - netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", + netdev_warn(bp->dev, + "unable to generate target frequency: %ld Hz\n", rate); - if (clk_set_rate(clk, rate_rounded)) - netdev_err(dev, "adjusting tx_clk failed.\n"); + if (clk_set_rate(bp->tx_clk, rate_rounded)) + netdev_err(bp->dev, "adjusting tx_clk failed.\n"); } static void macb_validate(struct phylink_config *config, @@ -751,7 +751,7 @@ static void macb_mac_link_up(struct phylink_config *config, if (rx_pause) ctrl |= MACB_BIT(PAE); - macb_set_tx_clk(bp->tx_clk, speed, ndev); + macb_set_tx_clk(bp, speed); /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down * cleared the pipeline and control registers. From patchwork Mon Dec 7 12:15:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 339555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94252C2BB3F for ; Mon, 7 Dec 2020 12:17:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BD9F2339D for ; Mon, 7 Dec 2020 12:17:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727569AbgLGMQu (ORCPT ); Mon, 7 Dec 2020 07:16:50 -0500 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:18847 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727531AbgLGMQt (ORCPT ); Mon, 7 Dec 2020 07:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1607343409; x=1638879409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Gy8Pc0VWAdq3BNbu92BtoqbTlIqU+jDmxbRUZaKX4PE=; b=JRa+4HrrM4mNjiXAnGoiUEq1sELMSWgqc80jEMa+dr817JSqTrwol7yU weDuNmeBUCWOf3DGEIsMGFqw7gadapvpL1LJQ5aQrAbgRVzc94aem/JqC 3QG1qWIfj2Lv5/agmdnpye0dwpF8XI0r2Js/fzMsT1DGn3kVaTIjxlNOE GDFxhNaw34lQnD4epY/ES2tPiViuXFQCfqyrWaUAnrQM1GcJrPG50oY+0 v2Ya5q+fDv5EiRPv1kI3KEgNMIOQf76RzbW4H6vlL9KVsPlQOk61/KLBO +Eh7HXGj0vACqs20UEd21+en6eKBoPSUlCJNxstP+CmPBrQozO8sAcKwx Q==; IronPort-SDR: /V9twlE602QPNR69lBGkEvoPJAm3mqAHtSjQZCKSFv3Dc7wV8dY163yPia7wSSteLG8SRMAc33 9aHDRS0p9zENhVOzcaBVIg1BorFFNaXuoIuUP31SJkG0ILM9POagYPY+mBcSARPbAftRHUsSMu iQVMz1PQ62qrychZaNaZ/x9Ofa7JX4tuGXWZ8LZ9q6QlFLi8a0+8AYdr1ioQJqatPtQJnFWouy gblveH1W6wbNFIzkgWm1L/Ah0paywYqrFiCUXec22uuKLg63r45jYDISyZPTTt20nZUcPY84K5 K5w= X-IronPort-AV: E=Sophos;i="5.78,399,1599548400"; d="scan'208";a="98863491" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Dec 2020 05:16:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 7 Dec 2020 05:16:08 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 7 Dec 2020 05:16:00 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v2 3/8] net: macb: add function to disable all macb clocks Date: Mon, 7 Dec 2020 14:15:28 +0200 Message-ID: <1607343333-26552-4-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> References: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add function to disable all macb clocks. Signed-off-by: Claudiu Beznea Suggested-by: Andrew Lunn Reported-by: kernel test robot --- drivers/net/ethernet/cadence/macb_main.c | 62 ++++++++++++++++---------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index b23e986ac6dc..6b8e1109dfd3 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -3694,6 +3694,16 @@ static void macb_probe_queues(void __iomem *mem, *num_queues = hweight32(*queue_mask); } +static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, + struct clk *rx_clk, struct clk *tsu_clk) +{ + clk_disable_unprepare(tx_clk); + clk_disable_unprepare(hclk); + clk_disable_unprepare(pclk); + clk_disable_unprepare(rx_clk); + clk_disable_unprepare(tsu_clk); +} + static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, struct clk **hclk, struct clk **tx_clk, struct clk **rx_clk, struct clk **tsu_clk) @@ -3743,40 +3753,37 @@ static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, err = clk_prepare_enable(*hclk); if (err) { dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err); - goto err_disable_pclk; + hclk = NULL; + tx_clk = NULL; + rx_clk = NULL; + goto err_disable_clks; } err = clk_prepare_enable(*tx_clk); if (err) { dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); - goto err_disable_hclk; + tx_clk = NULL; + rx_clk = NULL; + goto err_disable_clks; } err = clk_prepare_enable(*rx_clk); if (err) { dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); - goto err_disable_txclk; + rx_clk = NULL; + goto err_disable_clks; } err = clk_prepare_enable(*tsu_clk); if (err) { dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err); - goto err_disable_rxclk; + goto err_disable_clks; } return 0; -err_disable_rxclk: - clk_disable_unprepare(*rx_clk); - -err_disable_txclk: - clk_disable_unprepare(*tx_clk); - -err_disable_hclk: - clk_disable_unprepare(*hclk); - -err_disable_pclk: - clk_disable_unprepare(*pclk); +err_disable_clks: + macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, NULL); return err; } @@ -4755,11 +4762,7 @@ static int macb_probe(struct platform_device *pdev) free_netdev(dev); err_disable_clocks: - clk_disable_unprepare(tx_clk); - clk_disable_unprepare(hclk); - clk_disable_unprepare(pclk); - clk_disable_unprepare(rx_clk); - clk_disable_unprepare(tsu_clk); + macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); @@ -4784,11 +4787,8 @@ static int macb_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); if (!pm_runtime_suspended(&pdev->dev)) { - clk_disable_unprepare(bp->tx_clk); - clk_disable_unprepare(bp->hclk); - clk_disable_unprepare(bp->pclk); - clk_disable_unprepare(bp->rx_clk); - clk_disable_unprepare(bp->tsu_clk); + macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, + bp->rx_clk, bp->tsu_clk); pm_runtime_set_suspended(&pdev->dev); } phylink_destroy(bp->phylink); @@ -4966,14 +4966,16 @@ static int __maybe_unused macb_runtime_suspend(struct device *dev) { struct net_device *netdev = dev_get_drvdata(dev); struct macb *bp = netdev_priv(netdev); + struct clk *pclk = NULL, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; if (!(device_may_wakeup(dev))) { - clk_disable_unprepare(bp->tx_clk); - clk_disable_unprepare(bp->hclk); - clk_disable_unprepare(bp->pclk); - clk_disable_unprepare(bp->rx_clk); + pclk = bp->pclk; + hclk = bp->hclk; + tx_clk = bp->tx_clk; + rx_clk = bp->rx_clk; } - clk_disable_unprepare(bp->tsu_clk); + + macb_clks_disable(pclk, hclk, tx_clk, rx_clk, bp->tsu_clk); return 0; } From patchwork Mon Dec 7 12:15:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 339552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E23C1B087 for ; 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IronPort-SDR: 2cRnLYN91b6QJn0p4Dg8Qd9vR2NnlMKdEYJahY0q1e37wdBuH2wMb7hxvDVLM+zqTCvWL9Rgeg KObGtUGlf5FgTuchzJbcMtphHGxxQHVCziqf3/3isiRWNtTr2NLfcatafAqNQI95GoA93i8IXA /GUAlZ7fWIc/ts06voBvjubZFcDVoXv6+va0N1DPh9H/4yf0Y6U8PLRTVZvlfvzQpNBer6JYTc wN3GP2A3rqReJAZ0M7A+62oJVF2txnbPZP4Mu4Mmm1Mx1fK41DJVNkMq+jYs/aW7QzLOcQfPY9 RbQ= X-IronPort-AV: E=Sophos;i="5.78,399,1599548400"; d="scan'208";a="101729141" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Dec 2020 05:16:29 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 7 Dec 2020 05:16:29 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 7 Dec 2020 05:16:21 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v2 6/8] dt-bindings: add documentation for sama7g5 gigabit ethernet interface Date: Mon, 7 Dec 2020 14:15:31 +0200 Message-ID: <1607343333-26552-7-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> References: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add documentation for SAMA7G5 gigabit ethernet interface. Signed-off-by: Claudiu Beznea Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/macb.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 26543a4e15d5..e08c5a9d53da 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -17,6 +17,7 @@ Required properties: Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC. Use "microchip,sama7g5-emac" for Microchip SAMA7G5 ethernet interface. + Use "microchip,sama7g5-gem" for Microchip SAMA7G5 gigabit ethernet interface. Or the generic form: "cdns,emac". - reg: Address and length of the register set for the device For "sifive,fu540-c000-gem", second range is required to specify the From patchwork Mon Dec 7 12:15:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 339551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9EFDC2BBCA for ; Mon, 7 Dec 2020 12:18:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCD78233A0 for ; Mon, 7 Dec 2020 12:18:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727863AbgLGMRv (ORCPT ); Mon, 7 Dec 2020 07:17:51 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:39750 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727838AbgLGMRu (ORCPT ); Mon, 7 Dec 2020 07:17:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1607343469; x=1638879469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=7c4o9HTAPU/FWDNBRxOIP9hZ2d9X8oAOdvZ31rPTtNA=; b=uNVy+iBIMa/xCIZfDOPT5gofwmUOfzhpvFWJg/+aOjj0HajEt3uqmC3E YcKOHf2io9tBDixPO4EmFdCqFxLy/JMANAHUD82TjICxSfAuemvertrHu 88Z5InIWbOrWpLKxgGoBSMTygtRf0WgP4ZvLm2mTCyLhuJa/CvkHlQcVf xQiXe3hF8Npmkd9BikdpOul/HuAZo4HVrFWFyRegYl/wai4pxEm7ezX8d SpkVabvkgwpD8zN2BMt6DWXXcDF+YKx0+P+x+T+0EYGCbxeapfIPD1XzV Lfu8qBVx80aiB2OJ84wyQH5OPcmTgQACbxiqFkkHMeQvUI5oLYoCXxBoo Q==; IronPort-SDR: JpSfP/AgQp80I2E07mROSc85GO+IM9hwMHoqsZw22CNZUSZa2rNq0wbldfGl20okQ6sKRVGJlH L8ic9lS44WkFgjY1jRzRmbTJZcL+MBOwvETWrXcLHviyJJ7Bhg8rO7WSZMvFl0zznu4sqVjDrh d4oMlrBUzPgluv4nzd7+GMgIMFSCa13Ly+nMkkbu1KEekqvzDai/YQt/kAE1WN475DXBIJ00in tBKdxDoZIeVVPwd+/jpBSz5srUkvomlpVvZjn2eJhsr4nBmxQFp99z8KJ4JePOLrjxENiwujr5 oAw= X-IronPort-AV: E=Sophos;i="5.78,399,1599548400"; d="scan'208";a="106497590" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Dec 2020 05:16:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 7 Dec 2020 05:16:43 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 7 Dec 2020 05:16:37 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , , Claudiu Beznea Subject: [PATCH v2 8/8] net: macb: add support for sama7g5 emac interface Date: Mon, 7 Dec 2020 14:15:33 +0200 Message-ID: <1607343333-26552-9-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> References: <1607343333-26552-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for SAMA7G5 10/100Mbps interface. Signed-off-by: Claudiu Beznea Reviewed-by: Andrew Lunn --- drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index ca56476b3a04..bb280c55c4b3 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4574,6 +4574,14 @@ static const struct macb_config sama7g5_gem_config = { .usrio = &sama7g5_usrio, }; +static const struct macb_config sama7g5_emac_config = { + .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN, + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = macb_init, + .usrio = &sama7g5_usrio, +}; + static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,at32ap7000-macb" }, { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, @@ -4592,6 +4600,7 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,zynq-gem", .data = &zynq_config }, { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, + { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, macb_dt_ids);