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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id n7-v6si1301357plp.140.2018.02.08.02.18.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 02:18:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Q+2dSE6c; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 262D322361E63; Thu, 8 Feb 2018 02:12:38 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DDF0022361E4D for ; Thu, 8 Feb 2018 02:12:36 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id s5so4094469wra.0 for ; Thu, 08 Feb 2018 02:18:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=8+UMB6vQPoAMj4NHARqaFmGErRn8XAeW0BXZBOoKTqw=; b=Q+2dSE6cS8qEjkpwW2emdn0fGJI95ZJWhhlQz5ukmg5mCHIyZ5pahOWkZrOtGWI3Nt iWl7wXYoN/ZMsKObYsh0tgqBIDYmcXo2ir/PlOjVqAHpdYyx2xOi+46gQ9XL5j57T+NZ DbSsvfo4Xs4djn3Ub/Zu+KDDGbZLpPlMbAC9g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8+UMB6vQPoAMj4NHARqaFmGErRn8XAeW0BXZBOoKTqw=; b=VEQ+2jBJ8bVWs8mPPkL3sqEf7DvCVGkIcJBL/lQI+cgrihfVkYA4KVxllILLSZb43d eR0fLtQCWC+0uFEis1zLCz1TM/mJ+4VvmsKgFKsHxNb9yhA8tLaHn3qZoqB37HFSDtVb jEU3Z7pdX7ndnqiMMpSA/8+xlitI+NKQYvEWZSbv7VwrMgIGL4m6xILHKmPHxbR3uwNW wYJRsc3giehte2gI3aqc8yPH3Qc9c7BnvkD1IFAnJYDuboTE6R9GJwZeNQ/hI4+yq44x GqybrQf2EjfAP78mgIX54pJahrEsuS+f9p1xsjMWL+t7GJtfSfX58j53kLm4dj48XTYX fx3w== X-Gm-Message-State: APf1xPCiuvHkF9/XPpgx3MiClye2w84ZdHvUA78ABKDOmj8vJ+jJJsJU O75Ze1uuGc6xqFJPbsslnU2PGpsg5CA= X-Received: by 10.223.129.202 with SMTP id 68mr252933wra.4.1518085099574; Thu, 08 Feb 2018 02:18:19 -0800 (PST) Received: from localhost.localdomain ([196.85.252.149]) by smtp.gmail.com with ESMTPSA id l9sm9127655wrl.1.2018.02.08.02.18.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 02:18:18 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 8 Feb 2018 10:18:12 +0000 Message-Id: <20180208101812.4353-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms] Silicon/SynQuacer/PlatformDxe: disable eMMC DDR50 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" We already disable SDR104 support on the SynQuacer eMMC controller to work around the need for a special tuning quirk that is difficult to implement without modifying the generic driver, even in the presence of a SD/MMC override protocol designed to carry such quirks. Unfortunately, as it turns out, DDR50 does not work either with the particular 8 GB Kingston part that has been fitted on the rev0.2/0.3 96board samples. Since the mode UEFI drives the eMMC in is independent from what the OS chooses, and the fact that you would not use eMMC in the first place if performance was a major concern, let's just disable DDR50 as well, and fall back to SDR50 mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c index c40b30929d5d..6875dfe6b319 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -52,6 +52,7 @@ #define SYNQUACER_CLOCK_CTRL_VAL 0xBC01 #define SD_HC_CAP_SDR104 BIT33 +#define SD_HC_CAP_DDR50 BIT34 #define ESD_CONTROL_RESET_DELAY (20 * 1000) #define IO_CONTROL2_SETTLE_US 3000 @@ -95,7 +96,7 @@ SynQuacerSdMmcCapability ( // quirk that is difficult to support using the generic driver. // Capability = ReadUnaligned64 (SdMmcHcSlotCapability); - Capability &= ~(UINT64)SD_HC_CAP_SDR104; + Capability &= ~(UINT64)(SD_HC_CAP_SDR104 | SD_HC_CAP_DDR50); WriteUnaligned64 (SdMmcHcSlotCapability, Capability); return EFI_SUCCESS;