From patchwork Thu Feb 8 19:21:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127731 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793839ljc; Thu, 8 Feb 2018 11:24:26 -0800 (PST) X-Google-Smtp-Source: AH8x226pMU4RdvXKPZ8y5l8XIKN8cUYFjN+4N5gnFDHBKG/vN1Yxf9sPi9ibvGOTga5zp7dN9dur X-Received: by 10.36.68.206 with SMTP id o197mr272331ita.97.1518117866145; Thu, 08 Feb 2018 11:24:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117866; cv=none; d=google.com; s=arc-20160816; b=SEdd/t4hqHyasqgG2tpIzQGWTfLigHfssDlEbaEFf8gcap9uxxyi7Yt2lxTgAtfi4C M5HLX1doJfDrWiAbMNapFPNOqcnFKKLhvmfQYBREYU0Nl+pJIsQd8LgXbSyezSwMSi9m Mqvc7byYdooozyVlIaYWpnsshYt59RQgcOXao2yIYoVscPpr4tcitcXHiMvwMy1AXQIs r939zBG+eRYZiHL6V9HZUOJcYSGJw8lr+6QFGxII4E2Xf2itfVlnAuq2c/+shhsqMEC6 v6hrWM0IoVkBb4dZbmrP/xegM5IqeW1KCopJe+6gbYRbhJBQyVfZTtaBWLam6LngYbIv dang== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=0T8rsxLbZfXxgT34et37/h24MSV4npBV4MViKwTuUrg=; b=jrJUEBrZqU7e4f6pT8MXRg7Ms/8eGFrk6y5oPs4tfupmZVqoHYDWakMh2wKwnCWy2s BjkSFJx3AWXsvD1yPdArpYjGTqhNMdTHhgvG80Y60QJ1aZ8IZ9AsaexiRtiHmyPfiewu 6QaPc4x6PepYALlYnu0quHkgAbnSG98NzUbevfxGqVocDUNEnl9d1+bfJlL3vARpewTS F4pICWzdz0rjhTVp1VgqnHz4DF1Tqi5jfdwsE08fHu6gWlB6odP0NMSQ/CJwRUVbhWlE NTfoBA8a3MOJU/Kt3G0fvit8UonteILe8WbkPI7w0Z67q0a3mrRZCSPxNPyPbhNZq688 /aQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p90si559569ioo.304.2018.02.08.11.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlx-0006By-6b; Thu, 08 Feb 2018 19:22:17 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlv-0006BW-OJ for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:15 +0000 X-Inumbo-ID: 4d5dc424-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 4d5dc424-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:21:46 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0FD11435; Thu, 8 Feb 2018 11:22:12 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A21083F24D; Thu, 8 Feb 2018 11:22:11 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:49 +0000 Message-Id: <20180208192203.9556-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 01/15] xen/arm: psci: Rework the PSCI definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some PSCI functions are only available in the 32-bit version. After recent changes, Xen always needs to know whether the call was made using 32-bit id or 64-bit id. So we don't emulate reserved one. With the current naming scheme, it is not easy to know which call supports 32-bit and 64-bit id. So rework the definitions to encode the version in the name. From now the functions will be named PSCI_0_2_FNxx where xx is 32 or 64. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/platforms/seattle.c | 4 ++-- xen/arch/arm/psci.c | 10 +++++----- xen/arch/arm/vpsci.c | 22 +++++++++++----------- xen/include/asm-arm/psci.h | 37 +++++++++++++++++++++---------------- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seattle.c index 22c062293f..893cc17972 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initconst = */ static void seattle_system_reset(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } static void seattle_system_off(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 1508a3be3a..5dda35cd7c 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -31,9 +31,9 @@ * (native-width) function ID. */ #ifdef CONFIG_ARM_64 -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64_##name #else -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32_##name #endif uint32_t psci_ver; @@ -48,13 +48,13 @@ int call_psci_cpu_on(int cpu) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } int __init psci_is_smc_method(const struct dt_device_node *psci) @@ -144,7 +144,7 @@ int __init psci_init_0_2(void) } } - psci_ver = call_smc(PSCI_0_2_FN32(PSCI_VERSION), 0, 0, 0); + psci_ver = call_smc(PSCI_0_2_FN32_PSCI_VERSION, 0, 0, 0); /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ if ( psci_ver != PSCI_VERSION(0, 2) && PSCI_VERSION_MAJOR(psci_ver) != 1 ) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 03fd4eb5b5..6ab8ab64d0 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -243,35 +243,35 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) */ switch ( fid ) { - case PSCI_0_2_FN32(PSCI_VERSION): + case PSCI_0_2_FN32_PSCI_VERSION: perfc_incr(vpsci_version); PSCI_SET_RESULT(regs, do_psci_0_2_version()); return true; - case PSCI_0_2_FN32(CPU_OFF): + case PSCI_0_2_FN32_CPU_OFF: perfc_incr(vpsci_cpu_off); PSCI_SET_RESULT(regs, do_psci_0_2_cpu_off()); return true; - case PSCI_0_2_FN32(MIGRATE_INFO_TYPE): + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: perfc_incr(vpsci_migrate_info_type); PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_type()); return true; - case PSCI_0_2_FN32(SYSTEM_OFF): + case PSCI_0_2_FN32_SYSTEM_OFF: perfc_incr(vpsci_system_off); do_psci_0_2_system_off(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(SYSTEM_RESET): + case PSCI_0_2_FN32_SYSTEM_RESET: perfc_incr(vpsci_system_reset); do_psci_0_2_system_reset(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(CPU_ON): - case PSCI_0_2_FN64(CPU_ON): + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: { register_t vcpuid = PSCI_ARG(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -282,8 +282,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(CPU_SUSPEND): - case PSCI_0_2_FN64(CPU_SUSPEND): + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: { uint32_t pstate = PSCI_ARG32(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -294,8 +294,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(AFFINITY_INFO): - case PSCI_0_2_FN64(AFFINITY_INFO): + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: { register_t taff = PSCI_ARG(regs, 1); uint32_t laff = PSCI_ARG32(regs, 2); diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index 3c44468e72..becc9f9ded 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -23,22 +23,27 @@ void call_psci_system_off(void); void call_psci_system_reset(void); /* PSCI v0.2 interface */ -#define PSCI_0_2_FN32(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_32, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN64(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_64, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN_PSCI_VERSION 0 -#define PSCI_0_2_FN_CPU_SUSPEND 1 -#define PSCI_0_2_FN_CPU_OFF 2 -#define PSCI_0_2_FN_CPU_ON 3 -#define PSCI_0_2_FN_AFFINITY_INFO 4 -#define PSCI_0_2_FN_MIGRATE_INFO_TYPE 6 -#define PSCI_0_2_FN_SYSTEM_OFF 8 -#define PSCI_0_2_FN_SYSTEM_RESET 9 +#define PSCI_0_2_FN32(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) +#define PSCI_0_2_FN64(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) + +#define PSCI_0_2_FN32_PSCI_VERSION PSCI_0_2_FN32(0) +#define PSCI_0_2_FN32_CPU_SUSPEND PSCI_0_2_FN32(1) +#define PSCI_0_2_FN32_CPU_OFF PSCI_0_2_FN32(2) +#define PSCI_0_2_FN32_CPU_ON PSCI_0_2_FN32(3) +#define PSCI_0_2_FN32_AFFINITY_INFO PSCI_0_2_FN32(4) +#define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) +#define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) +#define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ #define PSCI_0_2_AFFINITY_LEVEL_ON 0 From patchwork Thu Feb 8 19:21:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127730 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793835ljc; Thu, 8 Feb 2018 11:24:25 -0800 (PST) X-Google-Smtp-Source: AH8x227EjGAs3jTIecy8AKJVvxuTH5WI/iODnQp4oR1NbHBtMC9iDUjYWNt5yHqUaZLKtMTeXt4z X-Received: by 10.36.65.222 with SMTP id b91mr342208itd.66.1518117865784; Thu, 08 Feb 2018 11:24:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117865; cv=none; d=google.com; s=arc-20160816; b=UIqXR6PSwY4SF9Bgy+rsqPQk8DOluWherPSWqXAvetUP1o14Lndc16Rw1I82nvVsVH nCv2Y2H+EY006QghmwEDgVuB/3QDNjXOx9osfd4o3E69nQvG+J88JLsjxzwXJwmYYpZj XhAokgr8CPHtgiCv70RO5w8iEQVzg88NK8IOL4iaSPpSUQ2ydM572kaPvL0/0efBXwEm x4Iki0lN16UP6oySbml/RCs3rEJ88+HNPq9C/6yCbWqs6QJvhG/MmqFn2M9YdDK+TAkt FncRfz54zhsKeECghP8hySocQni14s4Z1Fkwi7VVCYWdWOTiksE2SzDhRwljw2N4KonC m+uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=FZxjsQFsbiAtzWxtINx4WhC2CmAFCF3j35mu4TIwb/o=; b=q7oh7IzAFHaVyqWqmQZJdRBFAfBVFXDgCM/qQp53VQ2RdWaPefqYPYhXejMaMc2gIj rXYfaILtEunwZLrTPInffNwD1xfhoMV4TWyyKGySZhVeqsHDE1i9sjwIO1YeDAh6HfsA cZWtfoaOP0KjFkqk8UyFbRDQ7hB8TJxojxbTX0sqDEhxkC7oJG/GdKGsiPDWvvX2nHaJ Cv4E79YxcZ708ttEnCo0N155h+QZ9VayAli+UMysy4ZVdrH0QedXV4LSPdt0i7ssF+Bw hW5SQlLgWrLiPFo1JjD6ogyABg0t21Tr+VIjt7KKsvze6X5NCW2QsxYPdLKxAB/6+bwi UfmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c3si459231iob.190.2018.02.08.11.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm2-0006GX-Cl; Thu, 08 Feb 2018 19:22:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm0-0006BV-HJ for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:20 +0000 X-Inumbo-ID: 7fa69ec2-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 7fa69ec2-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:10 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75BE980D; Thu, 8 Feb 2018 11:22:14 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F02333F24D; Thu, 8 Feb 2018 11:22:12 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:50 +0000 Message-Id: <20180208192203.9556-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Wei Liu , Ian Jackson , andre.przywara@linaro.org, Julien Grall , volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com Subject: [Xen-devel] [PATCH v2 02/15] xen/arm: vpsci: Add support for PSCI 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, Xen provides virtual PSCI interface compliant with 0.1 and 0.2. Since them, the specification has been updated and the latest version is 1.1 (see ARM DEN 0022D). >From an implementation point of view, only PSCI_FEATURES is mandatory. The rest is optional and can be left unimplemented for now. At the same time, the compatible for PSCI node have been updated to expose "arm,psci-1.0". Signed-off-by: Julien Grall Cc: Wei Liu Cc: Ian Jackson Cc: mirela.simonovic@aggios.com Reviewed-by: Volodymyr Babchuk Acked-by: Wei Liu --- We may want to provide a way for the toolstack to specify a PSCI version. This could be useful if a guest is expecting a given version. Changes in v2: - Return v1.1 on GET_VERSION call as claimed by this patch - Order by function ID the calls in FEATURES call --- tools/libxl/libxl_arm.c | 3 ++- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/vpsci.c | 39 ++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/psci.h | 1 + xen/include/asm-arm/vpsci.h | 2 +- 6 files changed, 44 insertions(+), 3 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..86f59c0d80 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -410,7 +410,8 @@ static int make_psci_node(libxl__gc *gc, void *fdt) res = fdt_begin_node(fdt, "psci"); if (res) return res; - res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); + res = fdt_property_compat(gc, fdt, 3, "arm,psci-1.0", + "arm,psci-0.2", "arm,psci"); if (res) return res; res = fdt_property_string(fdt, "method", "hvc"); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 155c952349..941688a2ce 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -637,6 +637,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent) { int res; const char compat[] = + "arm,psci-1.0""\0" "arm,psci-0.2""\0" "arm,psci"; diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 6ab8ab64d0..e82b62db1a 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -106,7 +106,11 @@ static int32_t do_psci_cpu_off(uint32_t power_state) static uint32_t do_psci_0_2_version(void) { - return PSCI_VERSION(0, 2); + /* + * PSCI is backward compatible from 0.2. So we can bump the version + * without any issue. + */ + return PSCI_VERSION(1, 1); } static register_t do_psci_0_2_cpu_suspend(uint32_t power_state, @@ -191,6 +195,29 @@ static void do_psci_0_2_system_reset(void) domain_shutdown(d,SHUTDOWN_reboot); } +static int32_t do_psci_1_0_features(uint32_t psci_func_id) +{ + /* /!\ Ordered by function ID and not name */ + switch ( psci_func_id ) + { + case PSCI_0_2_FN32_PSCI_VERSION: + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN32_CPU_OFF: + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN32_SYSTEM_OFF: + case PSCI_0_2_FN32_SYSTEM_RESET: + case PSCI_1_0_FN32_PSCI_FEATURES: + return 0; + default: + return PSCI_NOT_SUPPORTED; + } +} + #define PSCI_SET_RESULT(reg, val) set_user_reg(reg, 0, val) #define PSCI_ARG(reg, n) get_user_reg(reg, n) @@ -304,6 +331,16 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; } + + case PSCI_1_0_FN32_PSCI_FEATURES: + { + uint32_t psci_func_id = PSCI_ARG32(regs, 1); + + perfc_incr(vpsci_features); + PSCI_SET_RESULT(regs, do_psci_1_0_features(psci_func_id)); + return true; + } + default: return false; } diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index a7acb7d21c..87866264ca 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -31,6 +31,7 @@ PERFCOUNTER(vpsci_system_off, "vpsci: system_off") PERFCOUNTER(vpsci_system_reset, "vpsci: system_reset") PERFCOUNTER(vpsci_cpu_suspend, "vpsci: cpu_suspend") PERFCOUNTER(vpsci_cpu_affinity_info, "vpsci: cpu_affinity_info") +PERFCOUNTER(vpsci_features, "vpsci: features") PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index becc9f9ded..e2629eed01 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -40,6 +40,7 @@ void call_psci_system_reset(void); #define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) #define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) #define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) +#define PSCI_1_0_FN32_PSCI_FEATURES PSCI_0_2_FN32(10) #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) diff --git a/xen/include/asm-arm/vpsci.h b/xen/include/asm-arm/vpsci.h index 035a41e812..0cca5e6830 100644 --- a/xen/include/asm-arm/vpsci.h +++ b/xen/include/asm-arm/vpsci.h @@ -23,7 +23,7 @@ #include /* Number of function implemented by virtual PSCI (only 0.2 or later) */ -#define VPSCI_NR_FUNCS 11 +#define VPSCI_NR_FUNCS 12 /* Functions handle PSCI calls from the guests */ bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid); From patchwork Thu Feb 8 19:21:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127725 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793645ljc; Thu, 8 Feb 2018 11:24:08 -0800 (PST) X-Google-Smtp-Source: AH8x225amwZcw+HegE6a5ZmNYXw6fPq0CLKY4IKVcPu8rjMVILTyD7+07JbpIDhGbZbR4lwlpBcQ X-Received: by 10.107.114.1 with SMTP id n1mr122481ioc.151.1518117848222; Thu, 08 Feb 2018 11:24:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117848; cv=none; d=google.com; s=arc-20160816; b=hZ9HrsKaMf0c32k6eowwhRdw0SzyX7ewNHWV2Xi1r0SUrf8Jriv9acAYKEQf7DMi+S TfsdWGFn79K/Evn1h9/c9KJSihMw5q8/34FBFfgVCZILO5Rw0uUNYEmXj4eyD8x+MsjM ZL9nG6umYD4VOJPGCqhJ0RMOdLP9vYazzeqFNx2j8TeMcm2b0ctzwDkOsFK5ydygdufy Esz3mrsHwxo3oXaCyOOsHHVHNjzjEIDm26aNlLVXWCmTjdbSGzAqDZo34yZwdFNdI4CD wvNkYgT6Je2zs16qs5glcNayko66E7EdpUONabCwPTB157ehv2jndZ/Eznv9/G2omsNR oR6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=Z1Y+ADJyv3KK6zgChB950322LLPZEMieQXRR8jUUxW0=; b=ugrgBh+3wCkKjjuj3o1A0elf6ukuauC4G19AYUktq+tqLLPqFhswBxkW1s6abo9Rr8 2K2fM2OPCeEUKhHtIbHWuU8jkIJapQvfDslfYNPi3jj7VgJQr7OU5VX9duFkHeBvE8yQ A1daRNFszvv0iNZRJMKo161tCCyGcUT2nE5XN6o1dihuFrMHGGBhtbMtuUpxQKCJpnf3 +ByDkOz2V6kC6CXmh7AMwZKvVqWjVKianh6aMstN7saMlY+2SPW72eY4Iz77LXUtnJ+R asw9le1sBKK0xpYwag1+728lJbr7fY05MCh515J6hIPidd4h1o4/OUMLIk5vJpfuXMZI i/HA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a39si436896itj.83.2018.02.08.11.24.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlx-0006CG-DK; Thu, 08 Feb 2018 19:22:17 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlx-0006Bk-1J for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:17 +0000 X-Inumbo-ID: 4f2fe361-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 4f2fe361-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:21:49 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C348F164F; Thu, 8 Feb 2018 11:22:15 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B43D83F24D; Thu, 8 Feb 2018 11:22:14 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:51 +0000 Message-Id: <20180208192203.9556-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 03/15] xen/arm: vsmc: Implement SMCCC 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. See "Firmware interfaces for mitigating CVE-2017-5715" ARM DEN 00070A. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Add a humand readable name for the specification --- xen/arch/arm/vpsci.c | 1 + xen/arch/arm/vsmc.c | 23 +++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 15 +++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index e82b62db1a..19ee7caeb4 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -212,6 +212,7 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) case PSCI_0_2_FN32_SYSTEM_OFF: case PSCI_0_2_FN32_SYSTEM_RESET: case PSCI_1_0_FN32_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FID: return 0; default: return PSCI_NOT_SUPPORTED; diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 3d3bd95fee..a708aa5e81 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -81,6 +81,26 @@ static bool fill_function_call_count(struct cpu_user_regs *regs, uint32_t cnt) return true; } +/* SMCCC interface for ARM Architecture */ +static bool handle_arch(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + switch ( fid ) + { + case ARM_SMCCC_VERSION_FID: + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + return true; + + case ARM_SMCCC_ARCH_FEATURES_FID: + /* Nothing supported yet */ + set_user_reg(regs, 0, -1); + return true; + } + + return false; +} + /* SMCCC interface for hypervisor. Tell about itself. */ static bool handle_hypervisor(struct cpu_user_regs *regs) { @@ -188,6 +208,9 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { switch ( smccc_get_owner(funcid) ) { + case ARM_SMCCC_OWNER_ARCH: + handled = handle_arch(regs); + break; case ARM_SMCCC_OWNER_HYPERVISOR: handled = handle_hypervisor(regs); break; diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 62b3a8cdf5..431389c118 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + /* * This file provides common defines for ARM SMC Calling Convention as * specified in @@ -100,6 +103,18 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_##owner, \ 0xFF03) +#define ARM_SMCCC_VERSION_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x0) \ + +#define ARM_SMCCC_ARCH_FEATURES_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x1) + /* Only one error code defined in SMCCC */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) From patchwork Thu Feb 8 19:21:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127728 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793824ljc; Thu, 8 Feb 2018 11:24:25 -0800 (PST) X-Google-Smtp-Source: AH8x226vKjpAgEwhj3Nx0RdPspDddhXuX6gJV2bt4AVZkbCt/AvcyofUgeC4uCTSHNXVnUzaQG2r X-Received: by 10.36.162.13 with SMTP id j13mr332964itf.74.1518117865125; Thu, 08 Feb 2018 11:24:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117865; cv=none; d=google.com; s=arc-20160816; b=NSJM6fIr8csjuzmiIEp8+QB2JW1LtHso1ztga4bc8cKf5CjrIDYnQ4DpTPLVWKcHeQ cKWm2iWVO86kh9m2rSIk2LJoSKOt5+OpmUJXssQAIzdie+CW2fodjEuXfVJaFhNBeTyf 78QuNOk1a3rzUbRu4/20uVxkWIefTT3gwzmDb1q/JONT4LD55I1gc55UjjntF+HTDmPn nfzIaVDSXVzYkdrc68E9SKzeU11gwROKF+D7aadAgqxP+pYaD9ByL82UrKTiUr7osAa9 RH4JDOrZigTKI2e7UuuEbi4loQBgV1XlDoKLGWSB1K7WpMxGwHEy4Ad0vu+50clqaZIK NJpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=zljNB1kl8ABmNCpCFlErDhQ0trGt6pJaAj8I8J5nEQ4=; b=eqfpXmLMUOqOYnntzjUa9G92ysb3Aai8gYcv1l7xXiT6TDzNw+TPTaPl4jmUrQRMer gtMMwdUnkLi33TnPUe7KqXjIdUst+eFHrCAFp/PlK8coDfTfMQ5IVexHmeE7a8dUnkB6 hjWTrawe0Y/kCpJmmOh6V6M6ycC1yIXKbK0RFu1m+i6RiayfwABmAJcmQLIuTeuP/BzG SWQvj/ZgmUHqquXIky/aZAWAMQSEE72JZKiJ44S9ISHyP8oUHwYSaOYTCw6aCACYKlNZ u2Srkdw8A+hN3LIgwhS5DarmyYGa0MxeBaZs0YjP8TvFh/Fa1SKVtdNTORd2AvB1cj7g 9Gsg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g20si435465iob.314.2018.02.08.11.24.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlz-0006Dr-N8; Thu, 08 Feb 2018 19:22:19 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrly-0006Cl-CC for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:18 +0000 X-Inumbo-ID: 4ff91db6-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 4ff91db6-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:21:50 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1CFA31435; Thu, 8 Feb 2018 11:22:17 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DCD53F24D; Thu, 8 Feb 2018 11:22:15 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:52 +0000 Message-Id: <20180208192203.9556-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 04/15] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index a708aa5e81..144a1cd761 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, -1); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = -1; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 431389c118..b790fac17c 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* Only one error code defined in SMCCC */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) From patchwork Thu Feb 8 19:21:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127726 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793802ljc; Thu, 8 Feb 2018 11:24:22 -0800 (PST) X-Google-Smtp-Source: AH8x226a61V0z5PgdjcPCB9BUkjMICvvQkMleucC6KBHEk43IWD+3tu7SK/3kF3vghS7KDuepeca X-Received: by 10.107.79.25 with SMTP id d25mr136073iob.270.1518117862617; Thu, 08 Feb 2018 11:24:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117862; cv=none; d=google.com; s=arc-20160816; b=y3nhOyk1MpRTzG8PA3PRhSx6pb7MhQ4yycdZMfCnnZE7+BAwrjamQDxSembxerp3Rr mTs6pcPdE2JkcBX8+tFBhz+uXkKPW694LeuztcNFqwaj3zFpKXVQtkQLQkzX0svy7+Zm JlI1Phs5KoUI8+bIRPGs3BtQeUwg59mCjuWmCcHw/2xC3pJ9yvyiwa0Uqt2YSUymVv85 1s91lm4j98TJ6L7ONy8J9lPPXhabxodcnbrzICf91OmZK7Fs3ZY5kY5w2O62uekejf5e bjjy+L8y4yo5uPzZmr0c2QFMnXmZyrVI88MEqXqVV7FEnYCf0MjywyhelGJ/6m94cMU7 jk1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=vLgUpdt4o1DKUo7sa2sxFEFNGK2lxd5L1wqXBhaPj5o=; b=Ha0GZCtD8A+51qgPmLa3gQAsXzTGkPaF/7Ca1ub8+Vr4zIqTkt4m6TZw1NfU89QMv9 gHLAXlZUKbvmdHO8bwVEsEJ5matbWEEUPsHmRh6ABXfd22SsDj5GuegPx4zXZ8dN3Ier 1n3HUrHGecIDzAv7kjOcR7I8vntt5SsqX7P42SFM87olcnjt29hVOlqNZcMzQnCnCCZe lPqY4gV1AYTgJAm2RnFrbgY/SqJyFyRJFFdasIKd/1kvJd/x8/QaDTeh2Q7HwKsnvyD3 LSxzUWLghYrgaUybBMx74PTUGW1QxYdnNAGpvFY9rNik0htAI+okmJITtv2ni814XGRz vMZQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 192si469893ioz.151.2018.02.08.11.24.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm0-0006Ev-Ub; Thu, 08 Feb 2018 19:22:20 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrlz-0006Dj-KY for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:19 +0000 X-Inumbo-ID: 50c37992-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 50c37992-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:21:51 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6AD5280D; Thu, 8 Feb 2018 11:22:18 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5BB173F24D; Thu, 8 Feb 2018 11:22:17 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:53 +0000 Message-Id: <20180208192203.9556-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 05/15] xen/arm: Adapt smccc.h to be able to use it in assembly code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/include/asm-arm/smccc.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index b790fac17c..d24ccb51d8 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -25,18 +25,20 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0U -#define ARM_SMCCC_FAST_CALL 1U +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 -#define ARM_SMCCC_CONV_32 0U -#define ARM_SMCCC_CONV_64 1U +#define ARM_SMCCC_CONV_32 _AC(0,U) +#define ARM_SMCCC_CONV_64 _AC(1,U) #define ARM_SMCCC_CONV_SHIFT 30 -#define ARM_SMCCC_OWNER_MASK 0x3FU +#define ARM_SMCCC_OWNER_MASK _AC(0x3F,U) #define ARM_SMCCC_OWNER_SHIFT 24 -#define ARM_SMCCC_FUNC_MASK 0xFFFFU +#define ARM_SMCCC_FUNC_MASK _AC(0xFFFF,U) + +#ifndef __ASSEMBLY__ /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) @@ -62,6 +64,8 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +#endif + /* * Construct function identifier from call type (fast or standard), * calling convention (32 or 64 bit), service owner and function number. From patchwork Thu Feb 8 19:21:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127737 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793979ljc; Thu, 8 Feb 2018 11:24:38 -0800 (PST) X-Google-Smtp-Source: AH8x227OeI1XgNQlkjhGDdjRCKc4fAiEeA3Q8xkgMbmZQC0PBvUFQVFlckeBKMZN+Kt8w9BIFeUR X-Received: by 10.36.65.8 with SMTP id x8mr332812ita.34.1518117877943; Thu, 08 Feb 2018 11:24:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117877; cv=none; d=google.com; s=arc-20160816; b=P1CXRYA4ixIeL48aNh6mju2JJW2UIU4b7XSkluRdmAbd4v3kp5/qEawkxCwTNk5Tyu Q4ZrMqwU3dDR6RDZ+I5599sAClQpL7t4qOSk+tdIh9LNnqxdor+HN3xfQ3NCVjE+E3Gx 0cgl64afnS46jXvfa3QlaKyUbUxallSeE1yLyQ0we7vOIJFTZ5c2fk3tZnSDwEI76JYt K/xj0GrflPmXiujzY6i+q8azwwIln8L9YC9LnJZJrgiyJTUZt2l6EG+3PBQh8G8YQhy3 kkZ461phEuEyY4HvINALaef/s88fuWp0WVaNIEN8qCDgR0u1sjrVfIftzCsRBIO2m3U7 uyIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=cuHYgprJS0bkCxydXSWVkU8odAniDxbabZW/3kkZ8Ps=; b=wMebcAGVuOdhZZ/E/yD0/1yZ9kG2vBA3JssYrE0nsSXKXnkLnJ6gFb1/0K8kKLDrP8 tApn8LBTVSlKl69JJ99DKbAAvkSlvA1Mb0ITPA2AXBIFKgwOPh2GcHjvkxUR3o02Mqew c/07PGGEKvYOqaWYP1kOVk5acK2WQ9eT4v48+2y/hxcJjrCFJEMKvPqKQjcgwXW0PXzJ bGpJatoJKSD5UiVrBp6u/zRTir7hebro5C6T7wK3d10D8I3f2BfUDhGKK7oCQGsihlOt luL1s40664UdqBCjE4VoAf8ab6uYp+wZSftmdwJ1x7Qdz7GGL+rBHOYqL9ZtNMu1C8/F I/PQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e3si456176ith.66.2018.02.08.11.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm6-0006Jn-KG; Thu, 08 Feb 2018 19:22:26 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm6-0006FC-5J for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:26 +0000 X-Inumbo-ID: 82ca0ac6-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 82ca0ac6-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:15 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B8629164F; Thu, 8 Feb 2018 11:22:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A96F73F24D; Thu, 8 Feb 2018 11:22:18 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:54 +0000 Message-Id: <20180208192203.9556-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 06/15] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advance. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/arm64/entry.S | 56 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..67f96d518f 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1 (default 1). If 0, + * we rely on the on x0/x1 to have been saved at the correct position on + * the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,45 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, x0 + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03 From patchwork Thu Feb 8 19:21:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127729 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793830ljc; Thu, 8 Feb 2018 11:24:25 -0800 (PST) X-Google-Smtp-Source: AH8x225JKC6eNW9yLEofXHZkRg6qYtkLe5MNw8NMklGCuoKYKGhO5vLdrW3k2/wZsCFVl4xbFGYp X-Received: by 10.107.53.164 with SMTP id k36mr147790ioo.292.1518117865533; Thu, 08 Feb 2018 11:24:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117865; cv=none; d=google.com; s=arc-20160816; b=JJvQLDfYmLzjgbNfhPbq8hsTT56DyD3XD2GlebwBDpmmIRSAPAsPY3hdYl1mHyEVNQ qYdTDHj3q2pOxVYF8JfGO1r8pZ98Z8yjbIlm/1PSQ5s0XLrE4SxsZaRg1xSm7JIhOoF8 dCZX0GeIZ0But19SnllP4qiM6pBvxsieMHXcpU7aZJqT4CnlxfE3MuF/UslpeIXgCqXP PvW5dq5/BBGyTVRPHwoWrkAG6ne43vSxnfQyCNpmHfG2J/Sr2l9MJqCLGPHaI6da4p/y PYqGHoUeKVv5Wa63gpZ1YHXOJ/ggUYhwUhCUELsJ5F+IpfbwAr3XSVVMHvPGZ4NlPuqM HnZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=gGqqNb797kmxgSBpGqNaWBC+DsJcHJivLvDL1o6V4W0=; b=BBJ7489VwAXPsfflf7+dOku7/SkR7d1Hr/6Jd+wtmjwcSLaX5iyLv+fMdEoNv5+fiE oU0MgTrVU+J/PmAGimAicKLAEZzPYGFEqeKbTeA5w22RSUDWTfMIwSQZt4f3NXdJxe1q 8uCIQMssrFiGl32rt3wAWDiMbq6CWFONUe+oapiurcupZF1nHB9FZw3tRmkIW1MUUjaQ 9duG75CzHkxeHw1BsHydxJn7HZzlars9lodWkh++1+cTYQoKmA/yfihcS08yssAMKW8R ksbF672QbdcRGPExngsYfH6sujIE88QDUGrCcsRqYIFv6EESAZ03DOlz30pmxh2yq7NR bdGQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r132si431100itd.136.2018.02.08.11.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm7-0006L7-RQ; Thu, 08 Feb 2018 19:22:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm7-0006GN-5J for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:27 +0000 X-Inumbo-ID: 83932795-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 83932795-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:16 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11C3380D; Thu, 8 Feb 2018 11:22:21 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 02D163F24D; Thu, 8 Feb 2018 11:22:19 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:55 +0000 Message-Id: <20180208192203.9556-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 07/15] xen/arm64: Print a per-CPU message with the BP hardening method used X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This will make easier to know whether BP hardening has been enabled for a CPU and which method is used. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Patch added --- xen/arch/arm/cpuerrata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 9c7458ef06..6704648b26 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start, static bool __maybe_unused install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, const char *hyp_vec_start, - const char *hyp_vec_end) + const char *hyp_vec_end, + const char *desc) { static int last_slot = -1; static DEFINE_SPINLOCK(bp_lock); @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, if ( !entry->matches(entry) ) return true; + printk(XENLOG_INFO "CPU%u will %s on exception entry\n", + smp_processor_id(), desc); + /* * No need to install hardened vector when the processor has * ID_AA64PRF0_EL1.CSV2 set. @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data) */ if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); + __psci_hyp_bp_inval_end, + "call PSCI get version"); else if ( !warned ) { ASSERT(system_state < SYS_STATE_active); From patchwork Thu Feb 8 19:21:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127727 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793807ljc; Thu, 8 Feb 2018 11:24:23 -0800 (PST) X-Google-Smtp-Source: AH8x225TNnxOF/fQTJR5u71PJdBwis6DQsYUXdLE+0AXwvKNnxOmpz22BQz5YJpZEl8ErG03+Ad5 X-Received: by 10.107.36.195 with SMTP id k186mr122718iok.131.1518117862939; Thu, 08 Feb 2018 11:24:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117862; cv=none; d=google.com; s=arc-20160816; b=O0UbxZEvHaEGZF7HcksPKKzulXCkJtV9uo5jxm/SK6Rj0BY0uzelT3GgcfaEHgiNAV XNgWHCAuEV8F4b+4qK6+h4cv7EmXnU/eAW8VgpxN6FvpGB/FszAMXc0mlUOHdFW8/Y2/ yLPpqkc2xfXXNmpO+Up0eOYfJ0nUNxHg9WwbMAKa+qsldwYqFI3h4mN1j9PLj6AHH+qc SdDMIMc54uHcRptrBWP9afhjw1nSdH0tWry6E3W9HtkoBxGACh01nSaGULTT5g3vaeFa /XDY9S8kqnZAcZ2K23bgdYl8QDZQO3RSp87hcIQOGDulFQ4APCsHCJ/vzGm8FjKBSjZt da+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=SMikpk39pK6uJyJnjpr3J01L4PuNanVlNqtkmjWEJ/A=; b=qjID/CCjmwnS1SKjC6SjymEVyYAJoJyWkHuGwWLBVdI0cgESotR0mYRv+TfghEJjs2 7dVKYVMxm9xOMveo2QM/kggvknBVQi74uu7DpbojrwUh/zAXyUQu+CcFXXrKPntNYzZG 6YRgN1ckwThYNpX8GvQ81D8m9SAqF1GSCUy0hcJVwR/6l94ajGiuewEuvOE73WcAgYL1 3vMwssiq7g/w4vliO9zsWy3wJa/ljS2h2t3TmZD5iVQ/6l4SuSJNCeSl7xs2crhvT33B haLZoVrs1p6M1sy0gCYnhWUaz+LmDbNcVRsm4Ow24KI/0Ok7ziBQlT3Wv1pzZXHEivG4 mIMg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z22si461590ioi.297.2018.02.08.11.24.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm9-0006NB-5n; Thu, 08 Feb 2018 19:22:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm8-0006HU-5S for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:28 +0000 X-Inumbo-ID: 845f13f7-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 845f13f7-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F3611435; Thu, 8 Feb 2018 11:22:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 505213F24D; Thu, 8 Feb 2018 11:22:21 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:56 +0000 Message-Id: <20180208192203.9556-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 08/15] xen/arm: smccc: Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} to easily convert between a 32-bit value and a version number. The encoding is based on 2.2.2 in "Firmware interfaces for mitigation CVE-2017-5715" (ARM DEN 0070A). Also re-use them to define ARM_SMCCC_VERSION_1_0 and ARM_SMCCC_VERSION_1_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index d24ccb51d8..caa2c9cc1b 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,8 +16,20 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ -#define ARM_SMCCC_VERSION_1_0 0x10000 -#define ARM_SMCCC_VERSION_1_1 0x10001 +#define SMCCC_VERSION_MAJOR_SHIFT 16 +#define SMCCC_VERSION_MINOR_MASK \ + ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) +#define SMCCC_VERSION_MAJOR_MASK ~SMCCC_VERSION_MINOR_MASK +#define SMCCC_VERSION_MAJOR(ver) \ + (((ver) & SMCCC_VERSION_MAJOR_MASK) >> SMCCC_VERSION_MAJOR_SHIFT) +#define SMCCC_VERSION_MINOR(ver) \ + ((ver) & SMCCC_VERSION_MINOR_MASK) + +#define SMCCC_VERSION(major, minor) \ + (((major) << SMCCC_VERSION_MAJOR_SHIFT) | (minor)) + +#define ARM_SMCCC_VERSION_1_0 SMCCC_VERSION(1, 0) +#define ARM_SMCCC_VERSION_1_1 SMCCC_VERSION(1, 1) /* * This file provides common defines for ARM SMC Calling Convention as From patchwork Thu Feb 8 19:21:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127739 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1794025ljc; Thu, 8 Feb 2018 11:24:41 -0800 (PST) X-Google-Smtp-Source: AH8x227DCrKScBFmfVDU582HBzqvt/iQC8uFwGoqzvSYj1KN+iK7bgXxwsYuqmwoNPxsrhjfc5YZ X-Received: by 10.36.7.209 with SMTP id f200mr293473itf.124.1518117881359; Thu, 08 Feb 2018 11:24:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117881; cv=none; d=google.com; s=arc-20160816; b=020pAm7/Q5LA98u1TOMlfzITLFVAIsah4FpezefDBk6K45DivzmCClonSYABcUiQun sy1O+cWjoO9nVX7z4pdjAX682B0qI6G6rWZUbvJM/8bmsZDm8NPuUYYlQ9fmA7mgNI1l idcz5/eeuu0/xoyUQPl5sS06QF+9duvO3aAeJxJ1wgtMXa9s44uoJDvLH8mxLURC0azX sn2/96WPDoqbY8paJ4rkHbUkFMzSY/OZSmbbIVIV3nSLnWCQKaxb0xBp6ZOT2rdjRMvG IUXpHjPjpYS7GnT3CHUx9B1ulzRZ0EA0MIH1Dt6s4HAPtbgFo+Lfl7ONmhqp43tE9BRt X1DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=nGBXJ5BobD7ElPmgoA83o31UMx6h3h/koQOPQD1ZnUo=; b=QbiX5vkspYT141ixNFLgDKe4pcN6OBHA0P8XC0r0wiTvYXh1abAxG4sMxhU32GAxoo NLe+1nrZJGHhYFFRl5sgO5hOC6u2XpiBCwLhaJG17205ei8hd/mAY0qeqW8leHgREMKa dZUSpBShwyOgO2OnmS+FYU4JbJlCIxVSFyXFKzs+sSMToM/onq48Y/28uL41Espd+aYR 3U93/3Xci7c6nJWptoIK70mMso3kY27qIUdk1lH3fGykNbrkRzk6ckuWfBKfXx7zR415 f7tp6l/ckbuXsj4Ofqh9Rj8aQDkJ4Xy5g4vhJfdlwHXlmK2c+nuU+UHDKlVkEab7s2Si ofRg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v188si442496itb.98.2018.02.08.11.24.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmW-0006qI-Im; Thu, 08 Feb 2018 19:22:52 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmU-0006k3-Tj for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:50 +0000 X-Inumbo-ID: 85255858-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 85255858-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:19 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ACE0680D; Thu, 8 Feb 2018 11:22:23 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9DC303F24D; Thu, 8 Feb 2018 11:22:22 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:57 +0000 Message-Id: <20180208192203.9556-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 09/15] xen/arm: psci: Detect SMCCC version X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or earlier) and the function return an error, then we considered SMCCC 1.0 is implemented. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/psci.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 5 ++++- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 5dda35cd7c..bc7b2260e8 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -37,6 +37,7 @@ #endif uint32_t psci_ver; +uint32_t smccc_ver; static uint32_t psci_cpu_on_nr; @@ -57,6 +58,14 @@ void call_psci_system_reset(void) call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } +static int __init psci_features(uint32_t psci_func_id) +{ + if ( psci_ver < PSCI_VERSION(1, 0) ) + return PSCI_NOT_SUPPORTED; + + return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); +} + int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; @@ -82,6 +91,24 @@ int __init psci_is_smc_method(const struct dt_device_node *psci) return 0; } +static void __init psci_init_smccc(void) +{ + /* PSCI is using at least SMCC 1.0 calling convention. */ + smccc_ver = ARM_SMCCC_VERSION_1_0; + + if ( psci_features(ARM_SMCCC_VERSION_FID) != PSCI_NOT_SUPPORTED ) + { + uint32_t ret; + + ret = call_smc(ARM_SMCCC_VERSION_FID, 0, 0, 0); + if ( ret != ARM_SMCCC_NOT_SUPPORTED ) + smccc_ver = ret; + } + + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", + SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); +} + int __init psci_init_0_1(void) { int ret; @@ -173,7 +200,12 @@ int __init psci_init(void) if ( ret ) ret = psci_init_0_1(); - return ret; + if ( ret ) + return ret; + + psci_init_smccc(); + + return 0; } /* diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index caa2c9cc1b..bc067892c7 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -52,6 +52,8 @@ #ifndef __ASSEMBLY__ +extern uint32_t smccc_ver; + /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) { @@ -137,8 +139,9 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x8000) -/* Only one error code defined in SMCCC */ +/* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) +#define ARM_SMCCC_NOT_SUPPORTED (-1) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Thu Feb 8 19:21:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127740 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1796973ljc; Thu, 8 Feb 2018 11:28:58 -0800 (PST) X-Google-Smtp-Source: AH8x224NF9GK5X4qxgMChVpK04YzSly8KNO3ulIzGTlZZubUYJ6uTJ+GpCHbuswnPGG5ynPMke2A X-Received: by 10.36.190.4 with SMTP id i4mr346753itf.20.1518118138840; Thu, 08 Feb 2018 11:28:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518118138; cv=none; d=google.com; s=arc-20160816; b=B7yqRaEOoT4egUx5tDdrfIe/ORzQ/gAP15piX9io1Zx0Z0xOlHBaThI41DcRT3R+Be MDPk8BjkY7r71ZFSycZtpMrDKOWInhzpz2ogP3PEqBQshhLRqlzOMLfW6gOG6o1olPys awc1WB0fe7z4AmkGuZsWQ5+avD4zj90N1krpCGrukM3IfIIY7+uJoT0Xgh94YztLaM86 jEc++yKfCOIxfwT1L4x2wln4FV3TTy25aMXlI/ikQBGhEhNGnR8Zc1rl/OcYgpR3Ltsy I1ZzTeOwsbOz/Yrg6DN/OY+suGu0ipYGvyj2C7TWFI/EWOtZbpvX4LAt7NZGuyt0VgW9 KV+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=RbgpMK4oPVMVlrn9q/08wx2jZAC/Wap3/PtHoTQCp1k=; b=noSRYTR9lMnHNeu7ck6KNXYjqX9r9k8wNi3Ar+qGEF9Lc3Ha19vXHIl7ra2OfooFuE d0EqAHc6COxQN1wrijAHulidCaiNEAtRMopgXl9FkyEKtAPqnPrQPXH/4yu83ndszQx8 +9biPWa1WdmsbdJ9TBwZqsep0oXQE5HQt5qt6p+Wz5jJbIKN6LiMGko6/t0St8/7CAte 2aEaN7Myt9ltzQaRZ12PVawVk66JYk+y4blq8nbvoR5TV63lajW32Zy+DO6wNlIEDvVy j+FO11rlEBDxfLjLACCgYnnw65DVgMrJNTlsxCW/kRi3s3SrIBe7NK63pKxZ/94rxsKI F6zA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z3si482458iof.273.2018.02.08.11.28.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:28:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrqA-00081O-69; Thu, 08 Feb 2018 19:26:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrq9-000814-7U for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:26:37 +0000 X-Inumbo-ID: 85eecef4-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 85eecef4-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 064A61435; Thu, 8 Feb 2018 11:22:25 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB8203F24D; Thu, 8 Feb 2018 11:22:23 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:58 +0000 Message-Id: <20180208192203.9556-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 10/15] xen/arm: smccc: Implement SMCCC v1.1 inline primitive X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that woudl otherwise be clobbered by SMCCC v1.0. This patch has been adapted to Xen from Linux commit f2d3b2e8759a. The changes mades are: - Using Xen coding style - Remove HVC as not used by Xen - Add arm_smccc_res structure Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Julien Grall --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index bc067892c7..154772b728 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -78,6 +78,125 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +/* + * struct arm_smccc_res - Result from SMC call + * @a0 - @a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/* SMCCC v1.1 implementation madness follows */ +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register uin32_t r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register uint32_t r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + * + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define arm_smccc_1_1_smc(...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile("smc #0\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if ( ___res ) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while ( 0 ) + #endif /* From patchwork Thu Feb 8 19:21:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127736 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793969ljc; Thu, 8 Feb 2018 11:24:37 -0800 (PST) X-Google-Smtp-Source: AH8x225aZ18uIS+nifoTYbO2+jzHQv5ajOUiI1VVdOOFYJIrakuAyXfwODnFOW0bxk6Ve3GOlitA X-Received: by 10.107.176.14 with SMTP id z14mr164666ioe.8.1518117877314; Thu, 08 Feb 2018 11:24:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117877; cv=none; d=google.com; s=arc-20160816; b=QesBiIW4v51SHcZzuXEy3snZM210rMOZxMRuIqELuFPgMZ5aiPukPSVr3lKdRrp25f giKjc4KtZUc8+OnAYFMFGBxH1tR0484DsQpO0Aw0Kjd0F5zOuMB+5jU02BZqa/NlLSGg YOLqXIJk9TmES5LaQwWgWH4ER+6kS42UN4j2Q8zU8+q3UVf3IOKcLnp5Mv7AGCKvhmqx ImllM5mjuZJK5ClNQXKClyrbp0cvuqT7w6bFQ0GgInpEW7/2TJwqQ7nahNgYHe51RJbM b9dmRgpIOJPzO4Tz4h8jOHXOu108tOzQvoT16o0OnmgNnUqebODLK9Qo/+Pb2H5PJNMo NpHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=6dITXwq/9wmioU7fyGAMQEQmD+ctWIVBZBFD54oTagM=; b=kTF2Y3BGyMVFBx9s3BtkfZ0pBNERcnum0tPNuYrSUJyx4VTX2x54Fza1hSvTmuriVv P8c5JpZF7rFtXeQFytiuPvmE9Ze8EjIBwafL4Q0zW8EPgyO3Tce0wJQ2JOZiW7ywXRxF S1Vl6ioH3TK9P8Yc8V5j3K6cvvz1aSyUynDwEV8dtfJ0Jr8ztkDW/cPYfsHORSQjKgH4 BDWMpZpLZ8zvaRG2ELs1L+4CyQ9VhKPTjRf1kl0zEyFSc9+QOxqMLz4C/HqlmSoTsSNw mLRLHcFvPkgpj+9WjNxZFxXXR+9gg/WYn0kq0MJGd/yDLcfM4UhdA4FGks0eHJOl8bMS aYzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n74si513108iod.222.2018.02.08.11.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmE-0006V3-2A; Thu, 08 Feb 2018 19:22:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmD-0006MR-AN for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:33 +0000 X-Inumbo-ID: 86bd5a50-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 86bd5a50-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:22 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5436680D; Thu, 8 Feb 2018 11:22:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 451473F24D; Thu, 8 Feb 2018 11:22:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:59 +0000 Message-Id: <20180208192203.9556-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 11/15] xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 12 ++++++++++++ xen/arch/arm/cpuerrata.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 1 + 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 4b7f1dc21f..ef237de7bd 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -16,6 +16,8 @@ * along with this program. If not, see . */ +#include + .macro ventry target .rept 31 nop @@ -81,6 +83,16 @@ ENTRY(__psci_hyp_bp_inval_start) add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) +ENTRY(__smccc_workaround_1_smc_start) + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_1_smc_end) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 6704648b26..6557577bcb 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -147,6 +147,34 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, return ret; } +extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; + +static bool +check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +{ + struct arm_smccc_res res; + + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return false; + + if ( smccc_ver < SMCCC_VERSION(1, 1) ) + return false; + + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + if ( res.a0 != ARM_SMCCC_SUCCESS ) + return false; + + return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); +} + extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; static int enable_psci_bp_hardening(void *data) @@ -154,12 +182,14 @@ static int enable_psci_bp_hardening(void *data) bool ret = true; static bool warned = false; + if ( check_smccc_arch_workaround_1(data) ) + return 0; /* * The mitigation is using PSCI version function to invalidate the * branch predictor. This function is only available with PSCI 0.2 * and later. */ - if ( psci_ver >= PSCI_VERSION(0, 2) ) + else if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end, "call PSCI get version"); diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 154772b728..8342cc33fe 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -261,6 +261,7 @@ struct arm_smccc_res { /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) +#define ARM_SMCCC_SUCCESS (0) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Thu Feb 8 19:22:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127738 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793984ljc; Thu, 8 Feb 2018 11:24:38 -0800 (PST) X-Google-Smtp-Source: AH8x2254sw2KRnzXcZaqtytatmEaXbrFOgju5C1bEl9bNTGgiZHJM9PnpLdM2XUbxs6c9WsTksA7 X-Received: by 10.107.168.25 with SMTP id r25mr169567ioe.16.1518117878516; Thu, 08 Feb 2018 11:24:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117878; cv=none; d=google.com; s=arc-20160816; b=pUZCU5htTbGpE+TghTyQWlY0RJ1633utE7R8ok6KDVgDuAzs8PJea7urIO3ZpgY89t Tb6Z9vwbrZUkPe1t9D7Pv70HmOAldPYALQqMvWonFXaLAZp1Erfu9r0g52DqixElqC8e 4kP4+TWfHmUOoeZIQuGagaARuHeDMB55pAKheJRHIzdxpZezUP8lqp0SLMXPnQbwusA8 7DYd1vVuar2NZOFLUOkHSoRqq0HeqBx2IDLzIhGTnSLqw92otewUayBwKuZve0Fc0xS8 tVzlQ99eZA+4/dhHZ1LMQvEcSQ/irxzoUDpy9UUlhUWxGnWADIWsj/a8bxVpWInlnK8u TfsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=KCDUvVk3IeyPKYNmfLSgDIS0OMC2g7u9CFZ4WtaVoRc=; b=yKaTA4ujRa7HWu6i5qrtRrOcsxRV31YmsgnIFjlw42U0d/i11vRb4tJ7OkReapcbC1 AML23sVv9uddKxjuXOamQecLDdDeak0NTRiGLgb7m25FTBRrWrHEZxnva1yEe8TWTYQp 3ppz6khjf7Li6Kswp902jrQtlxENrf4v0oK/NAvIzV5sF61i4yJzdTXuzkeCMYz2Vnfi X7m+rDgizt5Q5JzWrjL64xzmkSLBPbSK3YApWW1hZjEnCZmIGH3xKTC3hwL8/chf/Ndz nvFknn0raDPg21ifRhWGkQWVBa/B4iZhgL0Bz2M5elqH7e9uEz6XBRZKbPtdOtivOQKC PdKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f125si463756iof.290.2018.02.08.11.24.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmA-0006Or-Cm; Thu, 08 Feb 2018 19:22:30 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrm8-0006Mn-VP for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:28 +0000 X-Inumbo-ID: 56423895-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 56423895-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:22:00 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A226E1435; Thu, 8 Feb 2018 11:22:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 92EA73F24D; Thu, 8 Feb 2018 11:22:26 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:22:00 +0000 Message-Id: <20180208192203.9556-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 12/15] xen/arm64: Kill PSCI_GET_VERSION as a variant-2 workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. This is aligned with the Linux commit 3a0a397ff5ff. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 25 ---------------------- xen/arch/arm/cpuerrata.c | 54 +++++++++++++++++------------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index ef237de7bd..6270b10c4f 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -58,31 +58,6 @@ ENTRY(__bp_harden_hyp_vecs_start) .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) - ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) stp x2, x3, [sp, #(8 * 0)] diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 6557577bcb..af453710e4 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -149,10 +149,11 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; -static bool -check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { struct arm_smccc_res res; + static bool warned = false; + const struct arm_cpu_capabilities *entry = data; /* * Enable callbacks are called on every CPU based on the @@ -160,47 +161,30 @@ check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) * entry. */ if ( !entry->matches(entry) ) - return false; + return 0; if ( smccc_ver < SMCCC_VERSION(1, 1) ) - return false; + goto warn; arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); if ( res.a0 != ARM_SMCCC_SUCCESS ) - return false; - - return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, - __smccc_workaround_1_smc_end, - "call ARM_SMCCC_ARCH_WORKAROUND_1"); -} + goto warn; -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); -static int enable_psci_bp_hardening(void *data) -{ - bool ret = true; - static bool warned = false; - - if ( check_smccc_arch_workaround_1(data) ) - return 0; - /* - * The mitigation is using PSCI version function to invalidate the - * branch predictor. This function is only available with PSCI 0.2 - * and later. - */ - else if ( psci_ver >= PSCI_VERSION(0, 2) ) - ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end, - "call PSCI get version"); - else if ( !warned ) +warn: + if ( !warned ) { ASSERT(system_state < SYS_STATE_active); - warning_add("PSCI 0.2 or later is required for the branch predictor hardening.\n"); - warned = true; + warning_add("No support for ARM_SMCCC_ARCH_WORKAROUND_1.\n" + "Please update your firmware.\n"); + warned = false; } - return !ret; + return 0; } #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ @@ -316,22 +300,22 @@ static const struct arm_cpu_capabilities arm_errata[] = { { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR From patchwork Thu Feb 8 19:22:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127734 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793924ljc; Thu, 8 Feb 2018 11:24:34 -0800 (PST) X-Google-Smtp-Source: AH8x2262Gn0DW7hiDypBVsP2MEccbaNzld9bf14zhuZ01NYJomWXLF9yoqJlcxnBWNMJr4QedC6R X-Received: by 10.107.232.4 with SMTP id f4mr121692ioh.171.1518117873956; Thu, 08 Feb 2018 11:24:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117873; cv=none; d=google.com; s=arc-20160816; b=mSATg89BkzYEDW4PvB8iXCp8jiz/w1gDIXp3EDPea5uaBibCw23LSdUCW8p6zj/q8A vYufDk3DjvnsOIG7AZS8BPTTWZjzHGoGR+vcl5HvSaw69AL4AaAvMOnYniNJ2Y9cbqSe if6OqBU8djEZR/UaJj3fiCrEpCsJP5bDaLBcpPvylICwOBdbI34RBhXgalIdV53XmSFZ xtYNTIM81bWgn+Yax15pQNBikYur6uEIyjoxUBANxDQr0/9bTUiiMBFt3AAjgQD8gALD iESEJS99rdePaL4MQ4Y1ILNF3foaFougE5QJ5KBk5pPK5oyb7QpQBIwCvMEjy7bTA5aA Omqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=XZh2KG7+YWE1uTP1an54DbDQaurz7Y3NGsUEbbWIgpw=; b=eTEfw48fU/Ufnn3N4aFkwgIQqGOLjHqVHF9BM3+aquH6c9F6nCFA8A52JO0tfDNSE/ 0n8uMg+SdnHdUftS8s8dE8sDllF5ZKINqt/Ru5pNzORk6pG5WzFyvzgp2woHdLtFvX4O 0ckgZc2O8dB12dwYSecitj3vtXHf/WS0fdWJ1fVdIHm4MgoZIFYXYV7/6xjTxp5BtqfG aS1ddY6RYFnv4ie9YnJKCl4CzTWJo0xxRmSKqCKe+awUjcvYqf/VNG0rc4lb1/xqM5b8 RNIB1co6ggWPTaWEDth0ReqZwS29lkIm7NdbduQTd4hzs+Np6NZfkYOuPc4wvV8OZZtw irWg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 16si446154ios.249.2018.02.08.11.24.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmC-0006SI-Jw; Thu, 08 Feb 2018 19:22:32 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmB-0006Q6-9S for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:31 +0000 X-Inumbo-ID: 570b3906-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 570b3906-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:22:02 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EFDF980D; Thu, 8 Feb 2018 11:22:28 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E0EC83F24D; Thu, 8 Feb 2018 11:22:27 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:22:01 +0000 Message-Id: <20180208192203.9556-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 13/15] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- The reviewed-by was kept despite move this patch towards the end of the series because there was no clash with the rest of the series. Changes in v2: - Move the patch towards the end of the series as not strictly necessary for SP2. - Add Volodymyr's reviewed-by --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 19ee7caeb4..7ea3ea58e3 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -137,8 +146,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = { From patchwork Thu Feb 8 19:22:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127735 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793943ljc; Thu, 8 Feb 2018 11:24:35 -0800 (PST) X-Google-Smtp-Source: AH8x226EbiiWvMnEI0CpLYXJ7JyqSC5Rimi+kRKkC5dTmJq7wESqN1vl2FkRPTFFHjBzLDFo+yWg X-Received: by 10.36.1.70 with SMTP id 67mr312819itk.104.1518117874563; Thu, 08 Feb 2018 11:24:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117874; cv=none; d=google.com; s=arc-20160816; b=Dh0RfjE0Ndhb6VZGUsIxgS+yE61awXyP+Co66c/SYH9WOVHuXJYJTZ5MTOzK1G2AFC sofdKPsxD9o5v3JZ6kgX2T9HJibm3I28gny/Gc4vjraAUGZfI3D/Cr1eSEWtiHB1d1eC Ax4ORzjgtxhI2giwCXNZgqMfXUnGQvKEZYP22gWQf4QPJURoK1BJpxkoOSytYMLIM0v3 +tDtGCuQnBfp2NHMNA2Gnarbn4tOOQhZFIM+8AW8hjHjHnds0rS1ev66OTFzZgrED6rR zp+nMkoOgf8dv9v/9CqrLqiwmGBvhQ7vMAV+Ym3LUU8lXcseTbm7kMXNLT/dJVby6gnS +DdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=aoXQzl5RdhkDF9mvURsznxl5SFlPet+t5EkJBoZVP/I=; b=OdYXvbEWQOuS8G3gZ3ok5zHav8k/+Ugxv+bU3rtVXa9Ipl8SYFxqnMIqxEhh5KaNko f1I+a8U8UU4gnHtgoEcO9Uh+h8VYLEQl10pMwr+BNXitsaeMIOEF5zypQ+kCdNXmBQuM ND9h3wnqBV3UVXKlHXPJoGMAET7gK+b0LEr94aZ3j1hsdjNVZspyjJafbLSxuVUGwEvV fhUk4LC6mrS7O3ZP2aGqBkL5WEsL8YpLN82BJZdCWqc2o0j6ZD573gLqLFWp3epfv3sf WsXNKmbl95sSUJtyl6QnYO5dVoshePDo1qbsEikIag0RgH22ilB+92n97PNfRDZswBuj XYZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t189si481907iod.24.2018.02.08.11.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmI-0006aW-AX; Thu, 08 Feb 2018 19:22:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmH-0006RT-0f for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:37 +0000 X-Inumbo-ID: 89138e1f-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 89138e1f-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49AC51435; Thu, 8 Feb 2018 11:22:30 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A7D93F24D; Thu, 8 Feb 2018 11:22:29 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:22:02 +0000 Message-Id: <20180208192203.9556-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 14/15] xen/arm: psci: Consolidate PSCI version print X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen is printing the same way the PSCI version for 0.1, 0.2 and later. The only different is the former is hardcoded. Furthermore PSCI is now used for other things than SMP bring up. So only print the PSCI version in psci_init. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Patch added --- xen/arch/arm/psci.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index bc7b2260e8..7a8cf54e6d 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -136,8 +136,6 @@ int __init psci_init_0_1(void) psci_ver = PSCI_VERSION(0, 1); - printk(XENLOG_INFO "Using PSCI-0.1 for SMP bringup\n"); - return 0; } @@ -183,9 +181,6 @@ int __init psci_init_0_2(void) psci_cpu_on_nr = PSCI_0_2_FN_NATIVE(CPU_ON); - printk(XENLOG_INFO "Using PSCI-%u.%u for SMP bringup\n", - PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); - return 0; } @@ -205,6 +200,9 @@ int __init psci_init(void) psci_init_smccc(); + printk(XENLOG_INFO "Using PSCI v%u.%u\n", + PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); + return 0; } From patchwork Thu Feb 8 19:22:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127733 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793876ljc; Thu, 8 Feb 2018 11:24:29 -0800 (PST) X-Google-Smtp-Source: AH8x225TFr51LR9NMFJIs5Rc9G+vu/wwIVdt22QrivTzPB5xWGCqtTrVhSqC5QbEC857qx1bV4j9 X-Received: by 10.107.2.150 with SMTP id 144mr335868ioc.283.1518117869401; Thu, 08 Feb 2018 11:24:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117869; cv=none; d=google.com; s=arc-20160816; b=SE9G8Dlai3D37FpMSjcOz788wXThwvVg7zHVYAVfRrMUI0RnQMI/FhSR5+rXcpLnrf DpDujxfVre5b0+fgN1oKj8sB3Hx8U+7Kn2sRymL3jTGipe1yNeaZbxuKo09bGGAXnFc0 u9BFas0UA+LllktLfWDGwkV5yfdfyGWv2JoSVvl7yc8jboI42Ou1vHBkyYt+4atOZEzX CA4YhCUpn1W7+gapAbOoLpMMp9NFC9LqX/3Z72N9pXdGR4VpSXsBFGtxjieFn/sf4xnM fXZ1p1zhEsJoBMLhUR0cfD+Qu4Fbe+0e8XUglk7C1pOKHfwF/14OrqoYbQL2FgtfPPHX PRwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=N5G6Sk4ai9h+d2Sy20E1LWBw5XAPh62wkCirwevxRZM=; b=lgpy2vm7QXYkWQCIwgdRz75gaU+bsJpnbxXj6Em/ygxZBm651d9eSL2i4AM7sU4l8N JTaJRX213O4JAEsJ37e/6D9IiaAQoiVaQYJ8xW//eKhGv4NGE/OmtwT1iSq1W2gmd3Yw HxbPWTLkixI3d2WxvUi4OsI3PIwtrrBnOxc2KHq3vHbqEGWsGt3z+I6W5xo2qoRs8vlX Xz4guXHgyiofL1SdZgGf1peguBMAITEHaZpdpk2J2DzjcuSUxxzWRrAVHtzluAswcuWN sHK4CMEd2SSf/b1VIM2c85F6Mdq8693mTddsz2jbzoPNQu2tBqopqNOwBcIBiDbWAGN3 RFpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q204si444053itd.36.2018.02.08.11.24.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmD-0006UU-RU; Thu, 08 Feb 2018 19:22:33 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmC-0006SR-Pt for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:32 +0000 X-Inumbo-ID: 589e9890-0d05-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 589e9890-0d05-11e8-ba59-bc764e045a96; Thu, 08 Feb 2018 20:22:04 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9754380D; Thu, 8 Feb 2018 11:22:31 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8847D3F24D; Thu, 8 Feb 2018 11:22:30 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:22:03 +0000 Message-Id: <20180208192203.9556-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 15/15] xen/arm: psci: Prefix with static any functions not exported X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A bunch of PSCI functions are not prefixed with static despite no one is using them outside the file and the prototype is not available in psci.h. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Patch added --- xen/arch/arm/psci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 7a8cf54e6d..5d94a9a9ae 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -66,7 +66,7 @@ static int __init psci_features(uint32_t psci_func_id) return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); } -int __init psci_is_smc_method(const struct dt_device_node *psci) +static int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; const char *prop_str; @@ -109,7 +109,7 @@ static void __init psci_init_smccc(void) SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } -int __init psci_init_0_1(void) +static int __init psci_init_0_1(void) { int ret; const struct dt_device_node *psci; @@ -139,7 +139,7 @@ int __init psci_init_0_1(void) return 0; } -int __init psci_init_0_2(void) +static int __init psci_init_0_2(void) { static const struct dt_device_match psci_ids[] __initconst = {