From patchwork Thu Dec 24 11:16:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351890 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933192jai; Thu, 24 Dec 2020 03:19:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJwmBbXMLoaI96iJWatEG8MB1yIu/+4JjC9aymnLE4nSudiu9e5NkLmQJL2hP/SuTza7eWPX X-Received: by 2002:a05:6402:b9a:: with SMTP id cf26mr27860558edb.372.1608808742506; Thu, 24 Dec 2020 03:19:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808742; cv=none; d=google.com; s=arc-20160816; b=HTG+oFPxe//LcKZa4GvY4wyMNjlgwA9kkeRLz6TwkSMUusFAR/jxM4fQu8+UHvZDMb eoRucBfrWvKBxuOQshX243mXVBdU5LzeobVr8zrcgsQYtxVST7k+KcAZru0kyP/H0/6B Q6uxNgWw1W4UC/MOB4FtLofQF6ZjU0/AjD9euLuQEuDYrOb94POWPUZy9jh39LlHTIRt Ai9vkWtFflyZN5EtDJFyajfkHp5wIXqdAY0G1wh6tjOuB7lKiHDrWF1fvLIwlhGaj5QB n+Bt7njMm5pUpYJJKjhSEZ+AGMqyY8CTyq0alSLP9nMrqSe6tGjIoTg5RENk2/kRMD00 iBlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=HHTvmMjtTJRPNFpN3zkcx0PIiGXY1RMP1eK0a1ouBO4=; b=aK9+BTLSeezP1BlIfG3/5piGfyvV3IZ0XNhHRptdePQ0HKSbn9osLOZnWI3WXmiM6R TI1qE8paVi/ynlQDjUbZOtSwWeEPsweEqkS8tqow3i7ZfI+5c63rc9WXhzR/A3nkA9VC EnLj/DempCB5j0IYg/vghr2tZvJn4L1g/3peG/cRAIHqikIDG8UA8p25bC3c+DGM2GMI L9n1PIjlq/qrHvVP1BigecCPc4pTXeqAlsC3VjrXHCTZ2O3HMQ7Pf+sBthFslYV6NUVq ZUDFVzpg9f/wvIx6f2Vdpriuif9TzOrHE7MdsAiv1himWmrPWtH9KPVFLOD7Y2Q0DFnU R/VQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IuObjeay; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.19.02; Thu, 24 Dec 2020 03:19:02 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IuObjeay; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727861AbgLXLSd (ORCPT + 7 others); Thu, 24 Dec 2020 06:18:33 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37706 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728702AbgLXLS1 (ORCPT ); Thu, 24 Dec 2020 06:18:27 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGinB041728; Thu, 24 Dec 2020 05:16:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808604; bh=HHTvmMjtTJRPNFpN3zkcx0PIiGXY1RMP1eK0a1ouBO4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IuObjeaylDSr3Zi0pZgHVlrtWCWQn7wHfQo257nV/82cWfSU3oE7sZfCu83NlwwXq sd4gr+MdZV2Wi50fmuNNwkcTY/n2GCFHbwOLG27XIjswlaLfXHoUdyj4sbpejwmW8c UFyQvSuWcakZrcky6mVixOuDRHFEwtEUUwTYhXxs= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBGiP4059650 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:16:44 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:43 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:43 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWG7116630; Thu, 24 Dec 2020 05:16:38 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , , Subject: [PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence Date: Thu, 24 Dec 2020 16:46:13 +0530 Message-ID: <20201224111627.32590-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I Cc: # v5.4+ --- drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 26a0badabe38..19f32ae877b9 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy) u32 val; int ret; + ret = reset_control_deassert(sp->phy_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY out of reset\n"); + return ret; + } + /* Take the PHY lane group out of reset */ ret = reset_control_deassert(ins->lnk_rst); if (ret) { @@ -616,7 +622,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - reset_control_deassert(sp->phy_rst); return PTR_ERR_OR_ZERO(phy_provider); put_child: From patchwork Thu Dec 24 11:16:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351882 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933103jai; Thu, 24 Dec 2020 03:18:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJx3XayM4vSscJwfRX0Z/hwG+lAmg7/rtIz3ct/ObKyIMs5tWRF3FeK/uANq9ugt8Gq64FOH X-Received: by 2002:a17:906:f949:: with SMTP id ld9mr21644440ejb.401.1608808735088; Thu, 24 Dec 2020 03:18:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808735; cv=none; d=google.com; s=arc-20160816; b=GskTLmZ0so2j3w8sVikAmkmPI0QMo9893p9wdxlw337aq8MZnBfwrXFOf3aKq/3ody IWNcJxpDJb3BWWXhuEJRHCyAKVam/ALijJLhd+0HJVtQNorDHqQSd+Ko+2ud7Hpo8Ir2 6qDTxKxRc+DY/1iPFh39CMA/M1Otnn/lFeRW9fwvsu0ENlNFgFL1bTwfZNzpKBKob8gl z7cKqoenCLbwZLIRXFqBft8xxCWVBTGPnYd6J71E5QwYkhzI8SsyS3ISbKGgoluBWniB P7yMvG6cqEF6USqrou5gINPkBIYNr1722yfHA7ouUI9nxe0hABIFfmjRQPTLRqGRy35J L/9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; b=By+wgELUzxhSSFOLj97ay44kdke85IBX1Awu2rNs3fmL1GVGcb9+8dv4ujQ1HwfUSB L6eJpyWdUyHpts0h9ggtCD55ip3UApUYmsR/7/r6GrwnsUq7RSJJ6uF1TEBkayJrUk13 sSodfVkFUiyDBCxKPtI+8lZDTc0aIYpeHkcfj/WKQjCNsv6NC6qkZ/yCXPMZoWVorFwo AZ5QprBGT4cfX4vWjnt5IVLRyy5llFe2tK3R1Uv7skZ1D+SOLQGwCKetLRSJCwUuZzbg GLkgZIrLWrl54eWrvUevU/roq6JK7PnP2v58Vdsr8thw3IGmR+5A2WTR1QY2GrQs2Aic bPcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rXW67rXR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.18.54; Thu, 24 Dec 2020 03:18:55 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rXW67rXR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728082AbgLXLRn (ORCPT + 7 others); Thu, 24 Dec 2020 06:17:43 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37730 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726746AbgLXLRm (ORCPT ); Thu, 24 Dec 2020 06:17:42 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGtHP041757; Thu, 24 Dec 2020 05:16:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808615; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rXW67rXRnHaMt4WjB1qg4HF46eqsx7B9/GRjg6AsCqFRjjDjOYg455aUauB1cguhn LdGhhWna+8ygASCEF4324DTetGjR4qP2+cDW2+J/3syo0qMJyZR63d9WA+DI6oy2x1 IHDvinpNqyMBS6PMogyqRe+ubKbhcpr7xCJOqd0Q= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBGtkx059768 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:16:55 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:55 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:55 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWG9116630; Thu, 24 Dec 2020 05:16:51 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Date: Thu, 24 Dec 2020 16:46:15 +0530 Message-ID: <20201224111627.32590-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the PLLs within SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-sierra.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index d210843863df..f574b8ed358c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -49,12 +49,14 @@ properties: const: serdes clocks: - maxItems: 2 + maxItems: 4 clock-names: items: - const: cmn_refclk_dig_div - const: cmn_refclk1_dig_div + - const: pll_cmnlc + - const: pll_cmnlc1 cdns,autoconf: type: boolean @@ -107,6 +109,58 @@ patternProperties: additionalProperties: false + "^refrcv1?$": + type: object + description: | + Reference receivers that enables routing external clocks to the alternate + PLLCMNLC. + properties: + clocks: + maxItems: 1 + description: Phandle to clock nodes representing the input to the + reference receiver. + + clock-names: + items: + - const: pll_refclk + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^pll_cmnlc1?$": + type: object + description: | + SERDES node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + clock-names: + items: + - const: pll_refclk + - const: refrcv + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + required: - compatible - "#address-cells" @@ -130,10 +184,39 @@ examples: reg = <0x0 0xfd240000 0x0 0x40000>; resets = <&phyrst 0>, <&phyrst 1>; reset-names = "sierra_reset", "sierra_apb"; - clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>, <&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; #address-cells = <1>; #size-cells = <0>; + + serdes_refrcv: refrcv { + clocks = <&pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_refrcv1: refrcv1 { + clocks = <&pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_pll_cmnlc: pll_cmnlc { + clocks = <&pll0_refclk>, <&serdes_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc>; + assigned-clock-parents = <&pll0_refclk>; + }; + + serdes_pll_cmnlc1: pll_cmnlc1 { + clocks = <&pll1_refclk>, <&serdes_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc1>; + assigned-clock-parents = <&pll1_refclk>; + }; + pcie0_phy0: phy@0 { reg = <0>; resets = <&phyrst 2>; From patchwork Thu Dec 24 11:16:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351883 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933126jai; Thu, 24 Dec 2020 03:18:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpc2Q3GwkhIW08ZuQGK2DPA29OOkBETmhH+J9yJ6ttHZOJDlGQNXHlPuUTIAiAYbJfX3Cf X-Received: by 2002:aa7:c84c:: with SMTP id g12mr27779815edt.193.1608808736644; Thu, 24 Dec 2020 03:18:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808736; cv=none; d=google.com; s=arc-20160816; b=ycBZ8LRHjyDXjAbCEhesnyYUb3u044F9J/g8jv32z7IAY2MxJSqKC/VnagnZ2KpN8j Cwqxx2Va0ClbJfMUcXR7Gl0XBnN1JDFSG1idTfI93Zl3UYdnTHA7s013EUjeqkLkCa0c RTDaJ0rbjIAqaapooGix3VX/Uh6iuq81xjZIC7qobwtpeEQkT0ivd7xNNxEYPEk93zWR bmKlNDmA1/EjEp741XJsGvQjC5ZZ4OhBJKqBlWr+NBu5AO/qh5gtyP1Bpue1qg02+ggS ppCmSXgdHqEmOqt3cYO6GOgi+/FBVm1dJKmzumyBE085W7BTiqLKv0Bp/HlATpV9IZoK KIsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FjCTHLq/sEj9KXmxRwSejCjWFaAdBEX/mJW7iTNR8qs=; b=K6uuufoorbTz3/Y3e0IGgqdVc8dFQJEddbnsXUVnHUA07g/EC2XrY7xNmMLuVdoksh DR1QPOtX3dt2sfs3rVg9x1/Ts4lCtthCE9DfSUEamaXe8AhAY0QLBP5ctlteuMZr+/IL qq08gc20Ez3YAIduENJLZgzAw4iyq5mN/1SUBwrt48+k7vo1dqsRaMYVivzKO6yCDFb1 1p5bKvPrVf5mV1qpp7DnFEdR3BxmsLyqfLH+sa72cgFi5PNiR8OkX9xyz3I7CBT7FwPf rP5VfdyXctNhBUMS7OdqwwGj9m60ybLIGUjxmgjacxRMul0htn0tV70L8iqx8OTqxQr+ IAWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X3+dSNCP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.18.56; Thu, 24 Dec 2020 03:18:56 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X3+dSNCP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728341AbgLXLRr (ORCPT + 7 others); Thu, 24 Dec 2020 06:17:47 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35612 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726746AbgLXLRq (ORCPT ); Thu, 24 Dec 2020 06:17:46 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBH0Tp076156; Thu, 24 Dec 2020 05:17:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808620; bh=FjCTHLq/sEj9KXmxRwSejCjWFaAdBEX/mJW7iTNR8qs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X3+dSNCPUoYrOSo+cUtMslyKIXOcB/rqFWb59dEjOAR7Y25Q7KVS5t0yeMy59nyne bwDSu9xokFEVMA2Ufysi8vq1FZ618JK0q0bQdgdlfJD9sMWThMZBQJPq9xq0lALIot xX+xhTLTOjbbAdTlv4THcPCNSk1gBIiRAIW4ubs4= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBH0V5093262 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:00 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:16:59 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:16:59 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGA116630; Thu, 24 Dec 2020 05:16:55 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Date: Thu, 24 Dec 2020 16:46:16 +0530 Message-ID: <20201224111627.32590-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org "serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index a75433b459dd..2a03191eac64 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -787,6 +787,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) u32 reg, num_lanes = 1, phy_type = PHY_NONE; int ret, i; + if (!(of_node_name_eq(subnode, "phy") || + of_node_name_eq(subnode, "link"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { dev_err(dev, From patchwork Thu Dec 24 11:16:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351884 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933135jai; Thu, 24 Dec 2020 03:18:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJywzUW1WIiZ6ts3lX1KdyGF/UcI0aDFohcjAz+SeuaIVZ2YD3z9pL5rxfY4dAz68f/V0x46 X-Received: by 2002:a17:907:204b:: with SMTP id pg11mr28594351ejb.192.1608808737009; Thu, 24 Dec 2020 03:18:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808737; cv=none; d=google.com; s=arc-20160816; b=ZN6gvg7/AioqgLyreE9TyR87I0sgQyodDb/50pOQ82oT2/SBvp9ZvAjnAgdOEIyfWl XUzxgOSDFd5wYDB/lGXEvGeAPNJEqw2gQKZXONIEu7RXgyiQbe0U8Wpi0jF34mgaXaq3 w5FqQ7g24TCjznN5PK6au4tmmpGaVxrFAA14zhkHoLpGrPGQIPyF2dJFNfhdktlVMEyX 67mdSyDXD4eCfeYAYzfpLdOgf9zrKHEQ58ecGlXvCAv7rEo8AWbp4zmZjAyUFUo0pOym bs8Z64vLj0od9RsPaTU9Spg4+S1K6SiSHE671OADlMLOU8pvBfsKRzDlvMAMPGc59q02 EE2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=VxF8kGigCKqkh77tBFluIHDcpsujh9oOUvSPK2P6qiw=; b=0epXCHK17omqdo1YFTwhoMGRGmB4PKokNgsXgqtF1L2HyHxZgSEhZNv3hRt7HMt1n+ 2kHzzy+uPA16GAtVgXKjUwY5XRlmsCPQlNkINMKAq7/Og5JZOQF9McHPbwsyRmXCsL2G m5/9jlE8jILYAe11WhvW+s5MG3sop6U2GuHEdR2p6pFSlMqBmXSPL46M58DsEt1n6Zmx 9XEGjJZ43RKuJkJ1vHDx1PYeeZfl6nc77Mc+E9x1iAC545ZoOnJJPt2AJ6NMKXON2RP3 BHG6I3HH6qjngvhfXln8sVN+Ovgg78Cx7Vhf/mPa5CizNhVmv3VzfNhk8S/9xN3TOWXj 0nBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BS6JwMZO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.18.56; Thu, 24 Dec 2020 03:18:57 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BS6JwMZO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726186AbgLXLRv (ORCPT + 7 others); Thu, 24 Dec 2020 06:17:51 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37748 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726746AbgLXLRv (ORCPT ); Thu, 24 Dec 2020 06:17:51 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBH5Ew041788; Thu, 24 Dec 2020 05:17:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808625; bh=VxF8kGigCKqkh77tBFluIHDcpsujh9oOUvSPK2P6qiw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BS6JwMZO19mJkwysTfsduFTm/cj4ckpewYhxavid51HFwrX/1z1LyIYgH4QvqtwC1 LPduf46Ml1/oBh6OIubYSP/xtwENJ+rsQY/xUXM8t+UHrMPWoPCYVe24hY3eED+u4T gaHyGG8c7BIbr5Kp2F4ybYRlZ/1MOJjjUpZn8DPI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBH5G7060608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:05 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:04 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGB116630; Thu, 24 Dec 2020 05:17:00 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Date: Thu, 24 Dec 2020 16:46:17 +0530 Message-ID: <20201224111627.32590-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 19f32ae877b9..f7ba0ed416bc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -577,6 +577,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dn, child) { struct phy *gphy; + if (!(of_node_name_eq(child, "phy") || + of_node_name_eq(child, "link"))) + continue; + sp->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); From patchwork Thu Dec 24 11:16:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351891 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933202jai; Thu, 24 Dec 2020 03:19:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJwilsl+PXCJlpLw6J9KfyKXZ12bKqfncoVTDyySFdTC9AiGg5ceFq34LGAEWfVsbPHnRFi9 X-Received: by 2002:a17:906:9345:: with SMTP id p5mr27256197ejw.40.1608808743262; Thu, 24 Dec 2020 03:19:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808743; cv=none; d=google.com; s=arc-20160816; b=uK0Zco3jrJCFIoT4VduVPqC6G3F7uKV7HMRMuxv1vJBucfhVKBURxu93LPCOTuc4yU v2juVVRDI79mgrd+fLqrrOMYDeKBca5jrq5fAyliugoSTtwHxRNNtX9Ozfyleb9HuNNX DD7Yw3IvIe0lfyZ90sSPC1oCTFo/yS5jdG0KDkJGma2XZKQn4SiDsbJIR3JpbowwSDV0 7h58Lw1BGGTPWCIE3M7SdkOEhouryXl3V/KyIlGIf/trc9LjQ6IjJf+BLRaCankNCo0v bb5xNKsHJ9q8HHOHPYezd7RG50b/U7pxIhVvi3v1qlFz1RUeeI69cG5mXbjHBTizWrUq 88BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1m1jaw1QKhWt1my5TiZgSyHmcvod41lJIai7xVZR3M8=; b=cvdbuMTUfME9Fw2HOuIZkcBjBM1I6WkTyzyvSPo2Bgxqyuuv0VtGn+tC3PAY1Cm/FN i//Xer+iM7IjLOqD91XWug90P6JEl5dyyA6bN+WT/Lz5XY+TXxUqRyCN6jw7586ltdKG 7jXcd1OEjRqPmMIQgxdyYjK/0pvEAWUGHtNHMp+SweTZieex9F7yOs4qbrBepOM2O+eJ OANYOkdGgwTwpZMXMijZb3K2WN+pIFDiin8s3wkgXtacEP2VtHHdmueeYgxYlKaXy+MR hEC/y0gqLVNGjrIRelQ0PcEfVesAYc/ybNPY4iDtBPtQQ/ZagJcqT2spn3gUux9ZFzbn ouOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cEibqEjQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++--------- 1 file changed, 35 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index f7ba0ed416bc..7bf1b4c7774a 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -477,6 +477,38 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(clk); + } + sp->clk = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk_dig_div = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1_dig_div = clk; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -487,7 +519,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) unsigned int id_value; int i, ret, node = 0; void __iomem *base; - struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -524,11 +555,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get_optional(dev, "phy_clk"); - if (IS_ERR(sp->clk)) { - dev_err(dev, "failed to get clock phy_clk\n"); - return PTR_ERR(sp->clk); - } + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + return ret; sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); if (IS_ERR(sp->phy_rst)) { @@ -542,22 +571,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->apb_rst); } - clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk_dig_div = clk; - - clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk1_dig_div = clk; - ret = clk_prepare_enable(sp->clk); if (ret) return ret; From patchwork Thu Dec 24 11:16:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351885 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933137jai; Thu, 24 Dec 2020 03:18:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5lV5O8R8je3u/9zk66pX4vhiTvFsuTwiflPGZyx/66EgdMcL0Cd1TNsrzn/yhJa/GxSNK X-Received: by 2002:a50:d2d2:: with SMTP id q18mr27910345edg.346.1608808737824; Thu, 24 Dec 2020 03:18:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808737; cv=none; d=google.com; s=arc-20160816; b=cvFMPJ5+hH1A4olt4TddI2kNnCGXSHNKUylTdGD+7Wqmloy+hs7ILgqcfH5JBIncvw JP6VqEAZZpkMq0+2Lxq5AN/yKX/hBdC7rl6bogQYidddQ2nyQKD3XgLZbyCkkLZ1gwYK y+5Rh/4GdT4YpvH9ugY8m/A4DDqGRuin34NLP7pV8vPcYen/x2n39vvgI5proXyf8+30 kygDlmTv7BzqC9JXct6auTlOm1iBXF4I/y7Sf2Wns1HV5xWUH5+K2vStybn9nrQxKlJS MEy05cFxywgbRjtUZXO+Rgj2Y8R1UHP9vBUbboPG6VMicE/8Rox0ugvMHT+5ie+Ad5CN ywTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+nl8LicT//augqm13+dqzPO4Zt/8O9Pq6Zxz1AFAlx0=; b=YOuzuRlW3MCvwJYavHqK+ZoFjZALogZ3Lp8NTXA7nK4AFcy64FozRLbAERF8qcs5sL e439Ur/mkxemJLwzDG1Tlm8eA9daFQ4kWXI7VdY2SeK5BMH9k0tJOQm+7JPuWD8DWnpy c6kANLQv15tcNBY+mf5GI8jG0m0lSb64Kz7vMM/u729vcJ2KPSsMivBAJ0EZl9+0Rmzc yTq/MAElYlkG9JdI8gKOXxgI2aoLVUef6nG0buJuXBqJJiPxIec+R/jdFwKhaaWBXr8y K55S9Y3XwSLZ2I5X+XekjmVGU7boawJoQw1L5wQ3gJtDQm1E7UnkGZiPnylRYRHYtQXn KxtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NXBK9g1t; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.18.57; Thu, 24 Dec 2020 03:18:57 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NXBK9g1t; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgLXLSI (ORCPT + 7 others); Thu, 24 Dec 2020 06:18:08 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37798 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726591AbgLXLSG (ORCPT ); Thu, 24 Dec 2020 06:18:06 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHEiW041847; Thu, 24 Dec 2020 05:17:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808634; bh=+nl8LicT//augqm13+dqzPO4Zt/8O9Pq6Zxz1AFAlx0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NXBK9g1tSf8RnimtCvNmAHb4EhIAjmRwr++iCbThVu3FL1WVqbySNHyVXBGZpU4TM Zyx+8PLHPB5YbH1Rl3frr5gbdlG4y261lOYj75k8DgNeO7L2YF467SgfzYekcZ+juu xPpj2tk6uCXn2CA9DUdmYmUFT5MY0cTwAMRx7/aI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHEZ3058458 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:14 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:14 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:14 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGD116630; Thu, 24 Dec 2020 05:17:09 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function Date: Thu, 24 Dec 2020 16:46:19 +0530 Message-ID: <20201224111627.32590-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 36 ++++++++++++++++-------- 1 file changed, 25 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 7bf1b4c7774a..935f165404e4 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -509,6 +509,28 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct reset_control *rst; + + rst = devm_reset_control_get(dev, "sierra_reset"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(rst); + } + sp->phy_rst = rst; + + rst = devm_reset_control_get_optional(dev, "sierra_apb"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get apb reset\n"); + return PTR_ERR(rst); + } + sp->apb_rst = rst; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -559,17 +581,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); - if (IS_ERR(sp->phy_rst)) { - dev_err(dev, "failed to get reset\n"); - return PTR_ERR(sp->phy_rst); - } - - sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); - if (IS_ERR(sp->apb_rst)) { - dev_err(dev, "failed to get apb reset\n"); - return PTR_ERR(sp->apb_rst); - } + ret = cdns_sierra_phy_get_resets(sp, dev); + if (ret) + return ret; ret = clk_prepare_enable(sp->clk); if (ret) From patchwork Thu Dec 24 11:16:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351892 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933221jai; Thu, 24 Dec 2020 03:19:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJxPhT8YRFFJv6X9KTtCPOjUz89eq1CKPhsSoKvMm92TzRanVN83K2/pDZCJew6LjkS4zpcz X-Received: by 2002:a17:907:20a6:: with SMTP id pw6mr28170241ejb.73.1608808745074; Thu, 24 Dec 2020 03:19:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808745; cv=none; d=google.com; s=arc-20160816; b=W2nPECpUEVdUgUHhU/UQl66r3CUWO4DtqwNBaY0p1A6RyjpnsnMppwpPnTalKBZhs0 Ne/ZZGba12EymmkpXArYRZVMMuIMGSXh3ee+3PRUxGZrgG1ryPLb+SrKmx4k1vDYnNQo ihXQ8OpkOx7kRppS2+e01/JoEOfnpiVFnvPQYdmOMr+6i++gOq/vcKRYipxne6D48ZE5 8QzaN6iDqfZ35KR/NElCrgjpbovjMsx0BI0xsols3hGgFvtT40yIktmDcLGKfXtrqKPy +iAg3doNuRm06RhwZl20yTHfPndodMoljmV8v1+supKzyaYY+uqiqZvuSt9AMPOVzJHg fYeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=X8lkmYvm2LZftzAI7MPmXYXTlNDPCOiWt9wiFwCLMFg=; b=g+cpdAoQtlZycxyEAIkoksnhuWgAw65p0RbaO7WQ76pqbcZnPnYxWMdwC2k+NrfVdA 13tvCKdmNiwDl0SuqVrSj6y6cFJdWwNhQumNxR+CjCQRy+NgScEUYDP3Yc0gGUUOthlh JSA5SJdIqOudosINqOVXVp/D1QNxyr4+ptr7KZePni70vqyfilu2LC37VhEuYfzelkgA shyClVXGp5uWmumt6npYtZac9Exf7MtskVcJbErcDYp+1yGS+3y4A//nDPPyZfyi1rNN HUMhXkS4gaOkABJjNAAub5OhZ4HbRnT93vbJXRgnmZvYEBVygZ3O2s8EBouoyJa8/9Pp nH7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=s3WdSe+g; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.19.04; Thu, 24 Dec 2020 03:19:05 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=s3WdSe+g; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728114AbgLXLTC (ORCPT + 7 others); Thu, 24 Dec 2020 06:19:02 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35668 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727759AbgLXLTC (ORCPT ); Thu, 24 Dec 2020 06:19:02 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHJjJ076204; Thu, 24 Dec 2020 05:17:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808639; bh=X8lkmYvm2LZftzAI7MPmXYXTlNDPCOiWt9wiFwCLMFg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s3WdSe+g8q4e8MUUczFGswhcSW4YYOEuehaKawKzB8TeTEImOzKn1fBn2ioFyItY0 cFgeljLBvVsN2oVXHL+Kw92gAaU97pdJYDtDCjUSr5/Z/bGL01hxzjs60J0UfFBZXG 4r05d+GvWqh3xP/A5tDHQYdZIMEAGWF4K9tXU8JQ= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHJlw058539 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:19 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:19 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:19 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGE116630; Thu, 24 Dec 2020 05:17:15 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Date: Thu, 24 Dec 2020 16:46:20 +0530 Message-ID: <20201224111627.32590-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 935f165404e4..44c52a0842dc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -514,14 +514,14 @@ static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, { struct reset_control *rst; - rst = devm_reset_control_get(dev, "sierra_reset"); + rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); if (IS_ERR(rst)) { dev_err(dev, "failed to get reset\n"); return PTR_ERR(rst); } sp->phy_rst = rst; - rst = devm_reset_control_get_optional(dev, "sierra_apb"); + rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); if (IS_ERR(rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(rst); From patchwork Thu Dec 24 11:16:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351886 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6933149jai; Thu, 24 Dec 2020 03:18:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJxQQOvv+kkv9fBG/8LukkAk5bzKA5fKHHtPB9Bp2m/R6XuWKpRubiy86+iIQUKauo9qAatY X-Received: by 2002:a05:6402:3553:: with SMTP id f19mr14483045edd.129.1608808738768; Thu, 24 Dec 2020 03:18:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808738; cv=none; d=google.com; s=arc-20160816; b=YMIcr0NmTM0LOTiYsjATbBDvOdQWFJWEht2+9Ig73mkLwN+KzbPs58YBRtL0aaLIfF RpIKQ+wxg/XnfBkr1jwMkMBkBKDSL5cqeX/+l2UwYqZ2YWPEM6+7Xslgd0YSPF3XEQKT vszX2V2wKmddp7hCiDc4Z+tuIm/FJSVGduAWp11Y1mhDct0ykiTl9E9ioofKrNuR8ElF TyodsKvM33c5W2srG8RVlnzhb4EZ4+NvKSWw02CJAeEAQ01MQet8O8fa9Ki4E60MjOk6 hZoDBMmtWVU2EpU94iWOM+mH46cQ0wbLSFoIbDl6cw+31y7/ST21UYmRTud4VKe1DSYa 4Urg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=cI1RzCXhjshanMa9/MzV4KMdCSBLf7GenyIxvqdQkrY=; b=dLDNBMyPpov/uY7xcFuXVXGSp/vOTSGSgh92Oh8y+2m/hWweXAD1at1Qk0K8m2gy92 YvPLBtP056ifg4gNISeaSioaKQrrSEM2X8A/m5vgOX2+z8ziCZKo6dd5HEmLyQlp0Iiz H4/s4lOfLr8GcDOfMiFsT5FrMmqGd9Yee+WWSc6Ez/1zuhz6gkyh5YzEcFN6nBKNw2YR /3zfBM1Jr+ilHrMPJlULRkajbfbbSL7Mh6Xfo151Ze/3qLGzjsuSUO8zCoEYdHRotuUv oZeedFbrU8EnJjQqF1u9bcNCrvbjreR4dITnvAtBrNmsS3UcJ58hYuydGKAmL0AVKsG/ oLYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dUR7Y0f6; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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REFRCV is used to drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to be able to seamlessly use any of the external reference clocks. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 209 ++++++++++++++++++++++- 2 files changed, 207 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 432832bdbd16..23d5382c34ed 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -24,6 +24,7 @@ config PHY_CADENCE_DPHY config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER + depends on COMMON_CLK select GENERIC_PHY help Enable this to support the Cadence Sierra PHY driver diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 44c52a0842dc..8b7b2a838f5f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,6 +7,7 @@ * */ #include +#include #include #include #include @@ -31,6 +32,8 @@ #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 +#define SIERRA_CMN_REFRCV_PREG 0x98 +#define SIERRA_CMN_REFRCV1_PREG 0xB8 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -151,6 +154,35 @@ static const struct reg_field phy_pll_cfg_1 = static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); +enum cdns_sierra_cmn_refrcv { + CMN_REFRCV, + CMN_REFRCV1, +}; + +#define SIERRA_NUM_REFRCV 0x2 + +static const struct reg_field cmn_refrcv_refclk_plllc1en_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), +}; + +static const struct reg_field cmn_refrcv_refclk_termen_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), +}; + +static char *refrcv_node_name[] = { "refrcv", "refrcv1" }; + +struct cdns_sierra_refrcv { + struct clk_hw hw; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_refrcv(_hw) \ + container_of(_hw, struct cdns_sierra_refrcv, hw) + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -197,6 +229,8 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; + struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -364,6 +398,146 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static int cdns_sierra_refrcv_enable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 1); + regmap_field_write(termen_field, 1); + + return 0; +} + +static void cdns_sierra_refrcv_disable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 0); + regmap_field_write(termen_field, 0); +} + +static int cdns_sierra_refrcv_is_enabled(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + int val; + + regmap_field_read(plllc1en_field, &val); + + return !!val; +} + +static const struct clk_ops cdns_sierra_refrcv_ops = { + .enable = cdns_sierra_refrcv_enable, + .disable = cdns_sierra_refrcv_disable, + .is_enabled = cdns_sierra_refrcv_is_enabled, +}; + +static int cdns_sierra_refrcv_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *plllc1en_field, + struct regmap_field *termen_field) +{ + struct cdns_sierra_refrcv *refrcv; + struct device *dev = sp->dev; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + char clk_name[100]; + struct clk *clk; + int ret; + + refrcv = devm_kzalloc(dev, sizeof(*refrcv), GFP_KERNEL); + if (!refrcv) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &refrcv->clk_data; + + init->ops = &cdns_sierra_refrcv_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + refrcv->plllc1en_field = plllc1en_field; + refrcv->termen_field = termen_field; + refrcv->hw.init = init; + + clk = devm_clk_register(dev, &refrcv->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add refrcv clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_refrcv_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_refrcv(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *plllc1en_field; + struct device_node *of_node = NULL; + struct regmap_field *termen_field; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return 0; + + plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; + termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; + + ret = cdns_sierra_refrcv_register(sp, of_node, plllc1en_field, + termen_field); + if (ret) { + dev_err(dev, "Fail to register reference receiver %s\n", + refrcv_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_refrcv_unregister(sp, node); + + return ret; +} + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -402,6 +576,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) { struct device *dev = sp->dev; struct regmap_field *field; + struct reg_field reg_field; struct regmap *regmap; int i; @@ -413,6 +588,24 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->macro_id_type = field; + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + reg_field = cmn_refrcv_refclk_plllc1en_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; + + reg_field = cmn_refrcv_refclk_termen_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_termen_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -577,17 +770,21 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - ret = cdns_sierra_phy_get_clocks(sp, dev); + ret = cdns_sierra_phy_register_refrcv(sp, dn); if (ret) return ret; + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + goto unregister_refrcv; + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - return ret; + goto unregister_refrcv; ret = clk_prepare_enable(sp->clk); if (ret) - return ret; + goto unregister_refrcv; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -664,12 +861,17 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) clk_disable: clk_disable_unprepare(sp->clk); reset_control_assert(sp->apb_rst); +unregister_refrcv: + cdns_sierra_refrcv_unregister(sp, dn); + return ret; } static int cdns_sierra_phy_remove(struct platform_device *pdev) { struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct device_node *dn = dev->of_node; int i; reset_control_assert(phy->phy_rst); @@ -684,6 +886,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + cdns_sierra_refrcv_unregister(phy, dn); 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Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 188 ++++++++++++++++++++++- 1 file changed, 185 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 8b7b2a838f5f..2a509be80c80 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -25,6 +25,7 @@ /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A @@ -34,6 +35,7 @@ #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 #define SIERRA_CMN_REFRCV_PREG 0x98 #define SIERRA_CMN_REFRCV1_PREG 0xB8 +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -183,6 +185,36 @@ struct cdns_sierra_refrcv { #define to_cdns_sierra_refrcv(_hw) \ container_of(_hw, struct cdns_sierra_refrcv, hw) +enum cdns_sierra_cmn_plllc { + CMN_PLLLC, + CMN_PLLLC1, +}; + +#define SIERRA_NUM_CMN_PLLC 0x2 + +static const struct reg_field cmn_plllc_pfdclk1_sel_preg[] = { + [CMN_PLLLC] = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), + [CMN_PLLLC1] = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), +}; + +static char *cmn_plllc_node_name[] = { "pll_cmnlc", "pll_cmnlc1" }; + +struct cdns_sierra_pll_mux { + struct clk_hw hw; + struct regmap_field *pfdclk_sel_preg; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_pll_mux(_hw) \ + container_of(_hw, struct cdns_sierra_pll_mux, hw) + +/* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ +static u32 cdns_sierra_pll_mux_table[] = { 0, 1 }; + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -231,6 +263,7 @@ struct cdns_sierra_phy { struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -398,6 +431,138 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops cdns_sierra_pll_mux_ops = { + .set_parent = cdns_sierra_pll_mux_set_parent, + .get_parent = cdns_sierra_pll_mux_get_parent, +}; + +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *field) +{ + struct cdns_sierra_pll_mux *mux; + struct device *dev = sp->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &cdns_sierra_pll_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->pfdclk_sel_preg = field; + mux->table = cdns_sierra_pll_mux_table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Fail to add pll mux clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_pll_mux_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *pfdclk1_sel_field; + struct device_node *of_node = NULL; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return 0; + + pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; + ret = cdns_sierra_pll_mux_register(sp, of_node, + pfdclk1_sel_field); + if (ret) { + dev_err(dev, "Fail to register cmn plllc mux %s\n", + cmn_plllc_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_pll_mux_unregister(sp, node); + + return 0; +} + static int cdns_sierra_refrcv_enable(struct clk_hw *hw) { struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); @@ -606,6 +771,16 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) sp->cmn_refrcv_refclk_termen_preg[i] = field; } + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + reg_field = cmn_plllc_pfdclk1_sel_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); + return PTR_ERR(field); + } + sp->cmn_plllc_pfdclk1_sel_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -774,17 +949,21 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - ret = cdns_sierra_phy_get_clocks(sp, dev); + ret = cdns_sierra_phy_register_pll_mux(sp, dn); if (ret) goto unregister_refrcv; + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + goto unregister_pll_mux; + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - goto unregister_refrcv; + goto unregister_pll_mux; ret = clk_prepare_enable(sp->clk); if (ret) - goto unregister_refrcv; + goto unregister_pll_mux; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -861,6 +1040,8 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) clk_disable: clk_disable_unprepare(sp->clk); reset_control_assert(sp->apb_rst); +unregister_pll_mux: + cdns_sierra_pll_mux_unregister(sp, dn); unregister_refrcv: cdns_sierra_refrcv_unregister(sp, dn); @@ -886,6 +1067,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + cdns_sierra_pll_mux_unregister(phy, dn); cdns_sierra_refrcv_unregister(phy, dn); return 0; } From patchwork Thu Dec 24 11:16:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351893 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6934140jai; Thu, 24 Dec 2020 03:20:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJz4j1H77dOtcURwRz9kr6AajCtjNBjHYJ8W1zlFjVJZ1Henjc4jLrbv7aiw05D2pdoSiQkq X-Received: by 2002:a17:906:af49:: with SMTP id ly9mr26673988ejb.38.1608808822118; Thu, 24 Dec 2020 03:20:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808822; cv=none; d=google.com; s=arc-20160816; b=LfTw/xDHoaiAeRfxo8IJ0auWhlXnpv55wZjzDBGlRvGDs8nZkRyg53cYHbDMoEAKAR O/DJSnLavF+mfPAUYcvGiZrXtSTXPwTzOyznKCMv3/Z7EX//AXYhbomy1vF9v0sNbYX8 1+TvaDAVqae4jRv4G0hM9fTcBCADirhF1m8vLwFNVdE+OBB44AzxhxxJdNZ9+qEGPRQ2 2qQFH85RizBATQhWz3lb6E9fdubAf2PX5T+8MTLoguJ1fkQSPU+w9I7MHrFoxcXEv1w5 lzyW3qsOBzMqrOYbmmCZMbo3oq/A57mw20KYvAWHUSxPPMVB+FmG8OBxx3rgC8Hli58z Rmgw== ARC-Message-Signature: i=1; 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This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 2a509be80c80..ad0ea74515d6 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -267,6 +267,8 @@ struct cdns_sierra_phy { struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; + struct clk *pll_cmnlc; + struct clk *pll_cmnlc1; int nsubnodes; u32 num_lanes; bool autoconf; @@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, } sp->cmn_refclk1_dig_div = clk; + clk = devm_clk_get_optional(dev, "pll_cmnlc"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc = clk; + + clk = devm_clk_get_optional(dev, "pll_cmnlc1"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc1 clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc1 = clk; + return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->pll_cmnlc); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->pll_cmnlc1); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->clk); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->pll_cmnlc); + + return 0; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->pll_cmnlc1); + clk_disable_unprepare(sp->pll_cmnlc); + clk_disable_unprepare(sp->clk); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_pll_mux; - ret = clk_prepare_enable(sp->clk); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_pll_mux; @@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->clk); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_pll_mux: cdns_sierra_pll_mux_unregister(sp, dn); @@ -1059,6 +1111,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. 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[23.128.96.18]) by mx.google.com with ESMTP id c4si11409789ejk.182.2020.12.24.03.19.00; Thu, 24 Dec 2020 03:19:00 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t2PpE3bQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728667AbgLXLS0 (ORCPT + 7 others); Thu, 24 Dec 2020 06:18:26 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35732 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727144AbgLXLSZ (ORCPT ); Thu, 24 Dec 2020 06:18:25 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHbob076276; Thu, 24 Dec 2020 05:17:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808657; bh=TA56idjSLu14l1mLeNOv3BuYpulaKUC46doLv8n2T5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t2PpE3bQhvJn/i8xiij4TYjy8c5u6bPRFje0AmzFHa0mcMAjM0EJ8YKJWHINkzWGq oS6KphtURwQW92h4cbePiat6RmlJjE7+KRp9g5I7ax/Ij/6pPkuijd8NMWTfLfamTw Ts3qQ6z/UOuM/adx9bg0iSipHcn+LtqBiaZy5LLI= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHbDE094263 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:37 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:37 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:37 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGI116630; Thu, 24 Dec 2020 05:17:33 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Date: Thu, 24 Dec 2020 16:46:24 +0530 Message-ID: <20201224111627.32590-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT nodes for clocks within Sierra SERDES. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++-- 1 file changed, 120 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2d526ea44a85..9d1edce31829 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -400,8 +400,36 @@ #size-cells = <0>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes0_refrcv: refrcv { + clocks = <&wiz0_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_refrcv1: refrcv1 { + clocks = <&wiz0_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_pll_cmnlc: pll_cmnlc { + clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&wiz0_pll0_refclk>; + }; + + serdes0_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc1>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + }; }; }; @@ -457,8 +485,36 @@ #size-cells = <0>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes1_refrcv: refrcv { + clocks = <&wiz1_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_refrcv1: refrcv1 { + clocks = <&wiz1_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_pll_cmnlc: pll_cmnlc { + clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&wiz1_pll0_refclk>; + }; + + serdes1_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc1>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + }; }; }; @@ -514,8 +570,36 @@ #size-cells = <0>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes2_refrcv: refrcv { + clocks = <&wiz2_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_refrcv1: refrcv1 { + clocks = <&wiz2_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_pll_cmnlc: pll_cmnlc { + clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&wiz2_pll0_refclk>; + }; + + serdes2_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc1>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + }; }; }; @@ -571,8 +655,36 @@ #size-cells = <0>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes3_refrcv: refrcv { + clocks = <&wiz3_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_refrcv1: refrcv1 { + clocks = <&wiz3_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_pll_cmnlc: pll_cmnlc { + clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc>; + assigned-clock-parents = <&wiz3_pll0_refclk>; + }; + + serdes3_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc1>; + assigned-clock-parents = <&wiz3_pll1_refclk>; + }; }; }; From patchwork Thu Dec 24 11:16:25 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id q11si13009155ejx.0.2020.12.24.03.20.22; Thu, 24 Dec 2020 03:20:22 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vZZhO7bB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728292AbgLXLT1 (ORCPT + 7 others); Thu, 24 Dec 2020 06:19:27 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35746 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728214AbgLXLT0 (ORCPT ); Thu, 24 Dec 2020 06:19:26 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHgOV076292; Thu, 24 Dec 2020 05:17:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808662; bh=ldtRgeUKammL4+qtr5CA5LK2LIOwvnUVwhoio6N+/GE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vZZhO7bBdpFiwtDahIIaOGZoaQBMmu6Q/zurOkhC+p15a7Gn4lV3VeEExvmezcOBI N4mrii7pu2pOzDsZ7IkEC5xOE6qvaKs/2UQLo5Vp1A0uY7esRe0gOqIwcjaAqsAH4/ FC7yG5NRG6uxHoTRsikUO4pXvciW7KG+8QkKgWQw= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHgoN061386 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:42 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:42 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:42 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGJ116630; Thu, 24 Dec 2020 05:17:38 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Date: Thu, 24 Dec 2020 16:46:25 +0530 Message-ID: <20201224111627.32590-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename the external refclk inputs to the SERDES from dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1 respectively. Also move the external refclk DT nodes outside the cbass_main DT node. Since in j721e common processor board, only the cmn_refclk1 is connected to 100MHz clock, fix the clock frequency. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 4 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++++++++++--------- 2 files changed, 34 insertions(+), 28 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22b..86f7ab511ee8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -635,6 +635,10 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 9d1edce31829..20cb390d33b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include #include +/ { + cmn_refclk: cmn-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: cmn-refclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -336,24 +350,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -362,21 +364,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -438,7 +440,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -447,21 +449,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -523,7 +525,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -532,21 +534,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -608,7 +610,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -617,21 +619,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; From patchwork Thu Dec 24 11:16:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351896 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6934185jai; Thu, 24 Dec 2020 03:20:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwPBhyTE7Ewv81GFUksphx26GN8+g3VPBzCZu02nF4l6mRGEP6jEcHXqeWymGDAI0tLmvN4 X-Received: by 2002:a17:906:cec7:: with SMTP id si7mr27173566ejb.123.1608808825179; Thu, 24 Dec 2020 03:20:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808825; 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[23.128.96.18]) by mx.google.com with ESMTP id q11si13009155ejx.0.2020.12.24.03.20.25; Thu, 24 Dec 2020 03:20:25 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dNL8+Iaj; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728214AbgLXLTa (ORCPT + 7 others); Thu, 24 Dec 2020 06:19:30 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35756 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728887AbgLXLT2 (ORCPT ); Thu, 24 Dec 2020 06:19:28 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHlnI076299; Thu, 24 Dec 2020 05:17:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808667; bh=14cbnSxHB44iZkpTWbvcT9c4bCPw1pt8QKkVr6DRwOw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dNL8+IajYYcwHIMcONVNE6wWn9oJbQVX3WN2Bf2JRIPs3yN4OfinRR90yoICgegUp cmqB6pRQI0AvqIrpLL1GjW2g3IPlPXRt0fFPB1bQ2yf6KPBsxbuGyhcmr/Hn0MJbJh z9axrQas3+dyluJ7rrHk9zB3yvN1ZyUj9d/3gIkg= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHlAD094322 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:47 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:46 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:46 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGK116630; Thu, 24 Dec 2020 05:17:43 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Date: Thu, 24 Dec 2020 16:46:26 +0530 Message-ID: <20201224111627.32590-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use external clock for all the SERDES used by PCIe controller. This will make the same clock used by the local SERDES as well as the clock provided to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 86f7ab511ee8..788126daf91c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -639,6 +639,51 @@ clock-frequency = <100000000>; }; +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes0_pll_cmnlc { + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&serdes0_refrcv1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes1_pll_cmnlc { + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&serdes1_refrcv1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes2_pll_cmnlc { + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&serdes2_refrcv1>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; From patchwork Thu Dec 24 11:16:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351895 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6934161jai; Thu, 24 Dec 2020 03:20:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJzSAsyD5GTJuhNuZuPZsTWmMHW605vJSNI3yQaJ+0qS2oQ8t0DP/E/XugQpzpskJbyyVqeG X-Received: by 2002:a17:906:77c5:: with SMTP id m5mr27118840ejn.424.1608808823830; Thu, 24 Dec 2020 03:20:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608808823; cv=none; d=google.com; s=arc-20160816; b=sWLo9RpTpmZhNMOo9FViRhDbs65m7eGN8u5Tx3xQhoGLb5RMKEwhaqC2zhjk5wfLqE 8u6g1nAUIfy1QFXpNuC0AE48QD9sO9rrLqgZYK1Fw6I8kxcXV77Pz9j8pifyNrXDxhXe wRCnX410lJDjXKjZbxO4MH4fOYiqnBFbU1kAhoyaaVBLCxa9ga4OaQ2oDo9BHme4bMa2 icvV2MCxBU3Jx6hga4ZBlfUjm3GraU0rv96DceMJ/85lQtvoTIj02xGNIcjL52JuocI6 FNSlikd1Fzy3ocPskdjGnQBRT3xA9YxCAHW51E6Apd9eUCc1fGzQzCsyirhB7W4DuiD/ q+2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JZPshwWVVHYyyVCfjW7JfaXlQvyXib/1joMtQSq41ig=; b=HpCYJK4SsH9geil5Yx3wnYRORr/rTFm+7m0zlwlIkAl9HopJhTGFzYWYI9t3NZtGD9 Chfajx8lKoNJ/ricliHNOVrfkCfTYuC9LzC/zmt6lwILqRN04X6lITmv0vcA7HKC1OAD 8FEjMBONzdBylsuPxwf5oitFEDgvJqt9xF/LRbZWQ5PeCrqZvafrAKJ83VMui8YAjnXi 1Sz9W4UUsCPSbbtKczlEKQEvrpgG5VZmVmbTRzprh7dfKsVWY0LVg/1BdRkTbjOxTQft ynYkRXmLfQzEK45seauXahHbjStT3iFL0Zh30HqJyMXH3Q5bDX5Pn+cUgeNsXnxdhg5y Vp2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qLFOSEDH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q11si13009155ejx.0.2020.12.24.03.20.23; Thu, 24 Dec 2020 03:20:23 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qLFOSEDH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728923AbgLXLTe (ORCPT + 7 others); Thu, 24 Dec 2020 06:19:34 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37896 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728911AbgLXLTc (ORCPT ); Thu, 24 Dec 2020 06:19:32 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBHpkO042124; Thu, 24 Dec 2020 05:17:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608808671; bh=JZPshwWVVHYyyVCfjW7JfaXlQvyXib/1joMtQSq41ig=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qLFOSEDHajdS5TXt/BraTYPP2iJriIE4jP2suH4Z8Z7YWjAfSBZCyYVMXsrVdu8uE F1lfNg7ttDimhx+BhgOkzs/zkrUPA6BQepDDZYPPWDRaBasjNPVhRgSeGHUacod3H/ WChAxULNPUuSGFen+yyEJGjFQ7mEwNtynsE1nAdg= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBHpdc061452 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:17:51 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:51 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:51 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGL116630; Thu, 24 Dec 2020 05:17:47 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel CC: , , Subject: [PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Date: Thu, 24 Dec 2020 16:46:27 +0530 Message-ID: <20201224111627.32590-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") and commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") added PHY DT nodes with node name as "link" However nodes with #phy-cells should be named 'phy' as discussed in [1]. Re-name subnodes of serdes in J721E to 'phy'. [1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 788126daf91c..13ae0d89caf2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -358,7 +358,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -685,7 +685,7 @@ }; &serdes0 { - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -695,7 +695,7 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -705,7 +705,7 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>;