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[23.128.96.18]) by mx.google.com with ESMTP id p17si19506302ejw.23.2020.12.29.00.37.21; Tue, 29 Dec 2020 00:37:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D6RIykqb; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726138AbgL2IhI (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726388AbgL2IhI (ORCPT ); Tue, 29 Dec 2020 03:37:08 -0500 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5AABC061796 for ; Tue, 29 Dec 2020 00:36:27 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id jx16so17186104ejb.10 for ; Tue, 29 Dec 2020 00:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=geSRvMF6kCfgAVrxKSiIze0q0V64uiyFq2IRTDk+dkk=; b=D6RIykqbbsTWhkZryFVxGocnOeZBVKPudNdGZj2vvHUJUpibdCgqocDJAFSK69Wn+P ymnqXLJWmCoJHZr1s5yODfIsbwEpwTdf35wOlRql8UUQ/EHkfge2GjSLXjgBLI4cAc/z w2w0N5ec5hqW3/YUt/ZIVYrPH+riYh9YtJWeh+f+uFlBG945PBhLiczUnLmEPKlulJJY lwj0R0V2ex90i06Jx7cOt3H3UF7oz5k2Dnxweced4IDyyrk9ebdnJSGyfrNF9UxskCxY NjDScanYjDP6sBg626FxAxriZaOxTqFeayKPdUECGYXEGon7UU4ZUlLe6Lg8sON6zDz1 pI0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=geSRvMF6kCfgAVrxKSiIze0q0V64uiyFq2IRTDk+dkk=; b=noxwhPtwfoPfXL2T/JTzidk1jso4VpqjtpWAlGFKU0sX0LbHO8V8t6ZZ6fPg2ROb3c MYgmrnXI+1+JyaRvcewkLlGmKV2yIP+HAD4Pu8p44Xvs9j2e2C9oCcTgY9ahoDK3UXG7 aXXf4jZf9RcUq/aafLbRbuM3zgr/znEuX3VVysVOtYL+iLjLolzkAU+i7VspwPBB2vMo RDxiAB0mXz522XGL077eWmevqH+KNvf/PVZaZepeavlbUbfF3fkuOGtKn8iuXhWz/zEp g5Hxdp6R5XRwiCQdWOQY39ptloP9suGIN2purHdohOgLZo7qycnXKhY4vBu0LrTC4MmH TmMQ== X-Gm-Message-State: AOAM530Xww7bKXQqTO6pSPvUXccHbXuiSlA//u3RXk1KLKFk1Q1uahwp AKPR9WZj8OjXvRbl7fGN5/41xA== X-Received: by 2002:a17:906:a04e:: with SMTP id bg14mr3255978ejb.149.1609230986639; Tue, 29 Dec 2020 00:36:26 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:26 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 01/10] mhi: Add mhi_controller_initialize helper Date: Tue, 29 Dec 2020 09:43:42 +0100 Message-Id: <1609231431-10048-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This function allows to initialize a mhi_controller structure. Today, it only zeroing the structure. Use this function from mhi_alloc_controller so that any further initialization can be factorized in initalize function. Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/init.c | 6 ++++++ include/linux/mhi.h | 6 ++++++ 2 files changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 96cde9c..a75ab8c 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -1021,6 +1021,12 @@ void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_unregister_controller); +void mhi_initialize_controller(struct mhi_controller *mhi_cntrl) +{ + memset(mhi_cntrl, 0, sizeof(*mhi_cntrl)); +} +EXPORT_SYMBOL_GPL(mhi_initialize_controller); + struct mhi_controller *mhi_alloc_controller(void) { struct mhi_controller *mhi_cntrl; diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 04cf7f3..2754742 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -537,6 +537,12 @@ struct mhi_driver { #define to_mhi_device(dev) container_of(dev, struct mhi_device, dev) /** + * mhi_initialize_controller - Initialize MHI Controller structure + * @mhi_cntrl: MHI controller structure to initialize + */ +void mhi_initialize_controller(struct mhi_controller *mhi_cntrl); + +/** * mhi_alloc_controller - Allocate the MHI Controller structure * Allocate the mhi_controller structure using zero initialized memory */ From patchwork Tue Dec 29 08:43:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353967 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10370918jai; Tue, 29 Dec 2020 00:37:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJxBMj4IZCjHrYd1xiG85k7QL4WgAZMhzoMOd0hxDnWAguppjH3yWqMCKFye5z19JqNFqfW5 X-Received: by 2002:a17:907:2116:: with SMTP id qn22mr44460342ejb.483.1609231041865; Tue, 29 Dec 2020 00:37:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231041; cv=none; d=google.com; s=arc-20160816; b=MDHlKL56lmxWRBIMnRlanvHwCuVAuhT0/kyuqLlGfIeKMfgSAwRmb1Jxbb3Tolc7p6 12s18pBxgR1maWv7gNCR47Y1CyoE+eHmb49F31aADPZcNhqiBEjzjPamWQd3Ejoe2QNQ RL0N0xXK11p1iz/kkGimtZM0STfG6UQ6WQ+SPqHma22U5z0oZbhzCqj6Oh0hawCApvHz WGVo9GF0JGYfiJcDqWKWwK8MEKnJlvWul/B8ZOLM6ybsvqrxrDO1rvdELpn11Hkjq0Mh Hl5QNraJTsnQ32dde1i6jeR6f38v6uamadGk7HfwDbG8NejnuvfMwBUPuqiAvoDqnhOU PmJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=pOEXaNJekDpHw1CP3O0Pj76+vI42wYO3Vt7QFcDTgJc=; b=cJoeUIAzze18yQltuSgqOwtWCTUu64qCj3fJdW3uXrlxZ1/l02c7HGd61dY797od5c hGjGMBB42MFZCZ+Q6UIe0Y35PzSypbIoz82GHyO0+JF82bn4sRb/chnx67ATaP2TlCkg 813/SJjkJuRtKESfobTuNXSffSkh6/1G7fQZn6JzjiE9DBysn9UKqA2k5gDvay85PfpH G9UO8x8YovIAQXQMNu+lD/G++PNeUAwwChrZJRo3kGuwey//8TGH91X7BjCycr3mCXk6 ybrbGVcp0xy3dm6RWXRf+hk6L4hZXvGmqpS7HkkVvow9RkF3s7A/w4sjEWwNx/eX5Uqz 4Smg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=csyhjrc9; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p17si19506302ejw.23.2020.12.29.00.37.21; Tue, 29 Dec 2020 00:37:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=csyhjrc9; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726388AbgL2IhJ (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726144AbgL2IhJ (ORCPT ); Tue, 29 Dec 2020 03:37:09 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A244BC061798 for ; Tue, 29 Dec 2020 00:36:28 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id j22so17175117eja.13 for ; Tue, 29 Dec 2020 00:36:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pOEXaNJekDpHw1CP3O0Pj76+vI42wYO3Vt7QFcDTgJc=; b=csyhjrc9GjSVvQEAW1cEocZMyz2EMGheHNVnnmDv0CF1ePIXFh8mDWmDM3iseoUyI2 1FbMkDvIQUDHGos9ZJpsFT51nrnHNAOa0x76SrekYbiayhWDbqKiZIzoiKum8CRKvauh nShM6D29YuBZv1nCW8O0+iQRDTzP8zw8Jivu0FbuaWWCrIQg3UPW/gZFideULgvKisd5 Jnkpdex9GLvlZv1kbgIxbNANA43zz/ugTmJTXMLprHBV6mTYQqeBJTNPV6JSbkPpXOz+ wst8LvcQSGUXXDBlWgCmYHGGBqNkfcrLk/SgKqI8lCFk6YdXYw/C1rxlRVP1WFcUYuoV 1Ziw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pOEXaNJekDpHw1CP3O0Pj76+vI42wYO3Vt7QFcDTgJc=; b=YacfcoSdwLvWGs4cA2knCIi00p0M6XgyOt7j3GE9triupyBaO9T+5l2Txi6kLDMLLS GDcbkNBGJUU9XMNGP55TOA8E1oMMPgGrUwLrEZSgDEZPZEspz90YTBenWDwAx1LAv6Ti Hx5S79hm+5dCgqo5QKljvqvgl73O4wFmsOF9ReE/zrWx1wKTASu00G/XgBn/l8eLU68Q cRJf8Jr3+S9gPVFRS4NCq9hnAKDexZlsBZfgMTmL9+7uVHUJx44fkJ/gFV+Oc2hcOEU1 tF1ivoE4vRBN7n3rctQH7+6jWarlng1U9OU6BMZb5vgV5BiBZ+d5rZ7im4HcI111b63V BsiQ== X-Gm-Message-State: AOAM533+5pxntAUO6emOdG5536OIRz7EQmrJ4Mkc3admVCJr35HFigKj 46pLtnSXIoLQFyVxX3dmHRQWSQqOiyqasg== X-Received: by 2002:a17:906:d62:: with SMTP id s2mr44721010ejh.61.1609230987411; Tue, 29 Dec 2020 00:36:27 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.26 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:27 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 02/10] bus: mhi: core: Add device hardware reset support Date: Tue, 29 Dec 2020 09:43:43 +0100 Message-Id: <1609231431-10048-3-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MHI specification allows to perform a hard reset of the device when writing to the SOC_RESET register. It can be used to completely restart the device (e.g. in case of unrecoverable MHI error). This is up to the MHI controller driver to determine when this hard reset should be used, and in case of MHI errors, should be used as a reset of last resort (after standard MHI stack reset). This function is prefixed with 'mhi_reg' to highlight that this is a stateless function, the MHI layer do nothing except triggering the reset by writing into the right register, this is up to the caller to ensure right mhi_controller state (e.g. unregister the controller if necessary). Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/main.c | 7 +++++++ include/linux/mhi.h | 7 +++++++ 2 files changed, 14 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index a353d1e..9f8ce15 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -142,6 +142,13 @@ enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_get_mhi_state); +void mhi_reg_soc_reset(struct mhi_controller *mhi_cntrl) +{ + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, + MHI_SOC_RESET_REQ); +} +EXPORT_SYMBOL_GPL(mhi_reg_soc_reset); + int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info) { diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 2754742..8b1bf80 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -687,6 +687,13 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); /** + * mhi_reg_soc_reset - Trigger a device reset. This can be used as a last resort + * to reset and recover a device. + * @mhi_cntrl: MHI controller + */ +void mhi_reg_soc_reset(struct mhi_controller *mhi_cntrl); + +/** * mhi_device_get - Disable device low power mode * @mhi_dev: Device associated with the channel */ From patchwork Tue Dec 29 08:43:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353968 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10370928jai; Tue, 29 Dec 2020 00:37:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5VyI9YN3kZa1O6IJVC4/RX1gJyjszujoVPoFDyrfvom5jdaidZg1UrrLAnXJWnin/l5ZN X-Received: by 2002:a05:6402:2041:: with SMTP id bc1mr45016645edb.369.1609231042705; Tue, 29 Dec 2020 00:37:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231042; cv=none; d=google.com; s=arc-20160816; b=e6wCFyMPvcTXijVLFEk5duP18Ddy9meOFavH5KJ9a7jDnkKK5vFxWn2JNT7z46kdUT sD8Zu9XHBP/691/jhS6MwwOklFLjz9MokTfKGXzRr9YtzU3fMuHnmKEaNi+0AuA3tI5G dOrRRBzLc1bLECQsUt5/UNruzT/hcPmRXSch8F+yJFOJiR2tqjVQ0C1Soq6kH/EMHZUQ xYtp4y9QkTnX95GoCG1Xsyyo9MngpVnDHtqZkVVDiv1geT09yZn5MO4ujNCtaFy1tJ+L kooDpmSUqaIppdChCHHOZbMWYn85vrAN5HJT27OMnR8FuObK9TcOTJzJQ6m5OMllXlK0 wlWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=u23Upri+mVTKw2vMmpl89dQD9K1UaxJ4Tc+YMYk9PIg=; b=IymSOfaY7yaCrP/j+fmQUkK4Gr5Oqn3+EcZBAK7Lnc7BGrHKI/65Z/MbKBumOAQzOO d/wNWjGQRxszDyrNCfMxMg7vCMS21OZiLNbbcMrRfmzPMALJKX2XqHDbdiHy7/k3rF0x fmKcIJfpQCXtGuZ2eCauxygW7ZFOFCefQMZGXpQB7FvLlyfyYev+inRM1bh5fyG8oNT+ VXbpfXWzxJZSRQ3oZ6r/ADSOyxkjGujL459YlqjAiELOCD0sv3h5KI5AiowShoeifl8D tUd9JrQq93rWXp9pXlheNNUEjL7DxuF/kmqxSnwo7F7uBBhiTTzpb+6gP2Hta2oKU2p2 pAMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SErjQYPU; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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That can be prevented by setting a larger number of events (i.e 2 x number of channel ring elements). Tested with FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index e3df838..13a7e4f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -91,7 +91,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ - .num_elements = 128, \ + .num_elements = 256, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ From patchwork Tue Dec 29 08:43:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353969 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371732jai; Tue, 29 Dec 2020 00:39:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5ZRq5LT1pUckSHCISfgEZBLysmeRH7g/J+ObMsjDVAdDi0Rx6FFNMl3Cp81pRmnIPXx75 X-Received: by 2002:a05:6402:845:: with SMTP id b5mr46158069edz.38.1609231144923; Tue, 29 Dec 2020 00:39:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231144; cv=none; d=google.com; s=arc-20160816; b=cpNnKNPpomGE3aRkW0nH3rGYlRpXeK3uyt/vQVqZUEjV7614Y0o05U6nBc5hOqn/kr o8eL8EsupUPBXK9t4w28+ZVo7HSYXGbRWgZw3MJjHWZ5rvCpsQpUONREn9hKrojoOF35 geOga6118zZNt6RPt3x8rme3tljCUhtNQDbMiPcXvTTV6simBzr+Ow+JeTr/Cz7qOk0d zd8Fea3FyTvGI2GRQC5OHKeAquQ8XcCcGDfba329cMLBn6j3slCISQcdWownYsJuH5hY y67TAFSj746ZUBmnWetfIJsIFmdIVPbVHUoFdRYZ/wkV43BKQcCVJhI19RGGeAilibSu tmMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=0XpiShSj7O9MtA/3MXXhrx+6w1NooiPAdfYV2yyoWgr+l54VHCmDKnQ2QO4iRQBKKh emia1yUAXJu2SHpw48PAOoVB7p5ngfR28zf2UsIQ/M8l6VbH6lW+MmTxCPYIb6WOGoIP qIt34GwZzelz8hoLf6MPdQns2581FKNMZgXW8QhsMj1G9qYvRrgeaNJCeepdQjWVRuEd FyT21O/BDnpvNHgzPIXKz4sa4f3Nn8tyC9IMj6B/TysBtJCLHETAxmuSQ0WdgOLlkmQ9 1z3nN5vY2KzDieBt6mjJjomuFz/GAzL7tQl4mjfPECcAMzJGqwMGBjQapTu9tqpjBk5i fZRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=giyY+as4; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si21816192edp.7.2020.12.29.00.39.04; Tue, 29 Dec 2020 00:39:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=giyY+as4; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726178AbgL2Ihs (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725986AbgL2Ihr (ORCPT ); Tue, 29 Dec 2020 03:37:47 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 559A6C06179A for ; Tue, 29 Dec 2020 00:36:30 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id lt17so17232924ejb.3 for ; Tue, 29 Dec 2020 00:36:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=giyY+as4LBRWSxR8Oh2vVriyApOQD59afQIHnBuhU1mQ8+ONsJEvDK7q6/LXElrSJ1 gmtAPUuj3JV4pjDdkJEvUCFTWZyLjWAPIP6ohCs4LNv4RCrtNWRrDSbJAuwI2nb5/XpO 4AyLbAaBNWCuHMExyV0KLkFL4tyvvJfv7M4A51KKTgwD+rUsX5R4AREmhvd1x6/DTGvJ kkT7uDCo3EC2SEDqWgx1CjwCqLTHFhp0d1/zpBmJOplZ5K8c9AssNwWiXqNmios9dZc9 3RfgQXWA6EqUs1tl9hDEaATjDLf5PKWbh4WQkr3sNkM/AImO3zUAGs72duMmkdkpkcYp kS/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=igsPNOIk/HCCUqVHIEXIB7A32UgxngrSm1bisOIh+4CUfJk0pafh8iHQ3pzjIN2awY wBADiT7aA8DbCIxaEFGssqL8R4ctER+2BxhEi7qXWf9+x8rkoV7Zj5adO+1s1uyvWZc5 8pauyWNXF0IvyADBL9tenInEmjwvEmBDIrrirGiU3ddkgRXAnIoX6ye4tvEJf2TcrEHn sa6FHnng9KVkJdJz1PhURBSa14siucXU5yU4AQVLAB6A/CCRFGCAPJ5v8oR0g+6ca+z1 qrBP812fAADhOc6iyZDapZND6+xPQ0y4xr/qU7Ur8/XqvukRgc90vPcFVbXY8/zNhzTh F9+w== X-Gm-Message-State: AOAM5312HJWWVJWa9bm5XgPSCXm5MWhw+xi4S/gC4hTV2fo7CskccsCA lV01QTF1HfV8PzWM45QCd/A2ny5HkFiMcQ== X-Received: by 2002:a17:906:3bcd:: with SMTP id v13mr44714785ejf.181.1609230988978; Tue, 29 Dec 2020 00:36:28 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:28 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 04/10] mhi: pci_generic: Enable burst mode for hardware channels Date: Tue, 29 Dec 2020 09:43:45 +0100 Message-Id: <1609231431-10048-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 13a7e4f..077595c 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -76,6 +76,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -110,8 +140,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { From patchwork Tue Dec 29 08:43:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353970 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371742jai; Tue, 29 Dec 2020 00:39:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1WGMkHySVs2npNWLS7MlPXmRUF22NBbgV+ho5QguUX4S+KqCDM6baYk/irsS853XPF50Y X-Received: by 2002:a17:906:174f:: with SMTP id d15mr38104497eje.52.1609231145369; Tue, 29 Dec 2020 00:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231145; cv=none; d=google.com; s=arc-20160816; b=XvhAfZ0AIVMatEjPC0Qtc7mO5mBHG4Pc8EMqY07rLmnOdN02GIdlvd2J4VJNm2L5oL dZaplY4aC0DQS+tK5l5T/hf7UnbaAQ6S+/GFXO5pqoY9chAbYbR9/0lxoyRwhevkaLM2 5ro4JcwUErNuylXjcbFfPme5vL6OXaKFvtwZCuWQOFMjoVHdynU0aJOgsINZ5gdKIMNy tk93TYiEOVFraDH40tIekeCRPVkjpOcLNCh6Ana8s4A716yZsyJkX6dJCnPZmNTF1N61 PI1lR307IaTJ2SBtYk1EdmaAR+uGAc9KRtKjyrQMc5lLFyKF7RWEBLXD4am0yDEsJQ8s W7qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=A8ghSZC0o/frzSbWNus1KBuo0kNzFEb9nrR9JTZVUY8=; b=eobKS3qWD7comMZ4fOd6copQ/7CBbwQouy+u5fjuudRbksZ6QR85rYNRKbgAb8yYjX FlZjhQjMptnDKAF7OP19rH0/yuxZUNqWAPfvbD2Vq7DfFdaEOd93/ovThQVgOGg2+Igu PyfjWj5mvm/W9ewPv9O9sdEeTONuuG6UsQe2SWHskuBVWEV6WHbXMCcbV+9Vnn+LmcIk Ob3IA2OafS76Op2o5nacDi9pIlV1iPXSy8JjmdkRLIPH5Uxiw1uobxl8FoAHx8HCWYG4 1zOJ0uVQ9PIaAWsx5PG2JVbD6jH3lUaK0zQxFCdyRkXITuBpZnaeJdtDZwkz7qmvUbrh /sNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MDcWJizk; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 121 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 108 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 077595c..2521cd4 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -15,6 +16,7 @@ #define MHI_PCI_DEFAULT_BAR_NUM 0 +#define MHI_POST_RESET_DELAY_MS 500 /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -177,6 +179,16 @@ static const struct pci_device_id mhi_pci_id_table[] = { }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); +enum mhi_pci_device_status { + MHI_PCI_DEV_STARTED, +}; + +struct mhi_pci_device { + struct mhi_controller mhi_cntrl; + struct pci_saved_state *pci_state; + unsigned long status; +}; + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -196,6 +208,20 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, /* Nothing to do for now */ } +static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) +{ + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + u16 vendor = 0; + + if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) + return false; + + if (vendor == (u16) ~0 || vendor == 0) + return false; + + return true; +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -291,16 +317,20 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; const struct mhi_controller_config *mhi_cntrl_config; + struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; int err; dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); - mhi_cntrl = mhi_alloc_controller(); - if (!mhi_cntrl) + mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); + if (!mhi_pdev) return -ENOMEM; mhi_cntrl_config = info->config; + mhi_cntrl = &mhi_pdev->mhi_cntrl; + + mhi_initialize_controller(mhi_cntrl); mhi_cntrl->cntrl_dev = &pdev->dev; mhi_cntrl->iova_start = 0; mhi_cntrl->iova_stop = DMA_BIT_MASK(info->dma_data_width); @@ -315,17 +345,21 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) - goto err_release; + return err; err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; + + pci_set_drvdata(pdev, mhi_pdev); - pci_set_drvdata(pdev, mhi_cntrl); + /* Have stored pci confspace at hand for restore in sudden PCI error */ + pci_save_state(pdev); + mhi_pdev->pci_state = pci_store_saved_state(pdev); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -340,33 +374,94 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unprepare; } + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return 0; err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); -err_release: - mhi_free_controller(mhi_cntrl); return err; } static void mhi_pci_remove(struct pci_dev *pdev) { - struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev); + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, true); + mhi_unprepare_after_power_down(mhi_cntrl); + } - mhi_power_down(mhi_cntrl, true); - mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); - mhi_free_controller(mhi_cntrl); } +static void mhi_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_info(&pdev->dev, "reset\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* cause internal device reset */ + mhi_reg_soc_reset(mhi_cntrl); + + /* Be sure device reset has been executed */ + msleep(MHI_POST_RESET_DELAY_MS); +} + +static void mhi_pci_reset_done(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + /* Restore initial known working PCI state */ + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + /* Is device status available ? */ + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(&pdev->dev, "reset failed\n"); + return; + } + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to prepare MHI controller\n"); + return; + } + + err = mhi_sync_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to power up MHI controller\n"); + mhi_unprepare_after_power_down(mhi_cntrl); + return; + } + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); +} + +static const struct pci_error_handlers mhi_pci_err_handler = { + .reset_prepare = mhi_pci_reset_prepare, + .reset_done = mhi_pci_reset_done, +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, - .remove = mhi_pci_remove + .remove = mhi_pci_remove, + .err_handler = &mhi_pci_err_handler, }; module_pci_driver(mhi_pci_driver); From patchwork Tue Dec 29 08:43:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353972 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371750jai; Tue, 29 Dec 2020 00:39:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJy/J6d8LLr7O789Lf1HCIr2yS3LICZZmH78sCBavMpq+SY8ihy2OhjVOWVt2M/lrgi+DZFo X-Received: by 2002:a17:906:d152:: with SMTP id br18mr41210661ejb.297.1609231146253; Tue, 29 Dec 2020 00:39:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231146; cv=none; d=google.com; s=arc-20160816; b=fRjbJABbbfiJSr91+Oiu/6jZf919NezP5/ARpEbgLh9FDwmokO6/uy4P8vVnOhoTAH iT02aE6x7wvgaK7QBZKVVCjcr4L9wzEfPZmOT4RFLIv+62ZROHDSShLPXUVzvySi6mZs YM+Ktpta9XyBBqFAyNCI5Q/wGa0i3lR1kMVuxTylCMLnKZCpvJF+6jYYd/QbkFFUqQa0 Jtu0pc5Nm3gJ+Bnj+ng5PZNAr46vWi5lWo6nCAQEmYAr5hKLq5T90kkkTsdsgTABDhw8 pqeL3ei+gRs9GJ2LRlybW/PjuFh3f220aYoP+x75ue7OPMuROydtva6mMfKqxFQ+9wCI Whbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=LFcOLpi81oSUdisHEF+x7OxdMm5UlH9qgt1oY8gs1Nc=; b=b54kU8EcCf0AOuxFkvgxANX5+E/tNVn/vTF7aC7SSpmduY47prfplzXln51dOMG6CJ PkZ2b+uGq0rSk3Bc6xLqwgnQ4jxPyK1ZHyv4HmQOAwaVovmnb5vsk7SMIlyuvRux38Kh 7eosD1vrof9NmFhM9oKPUV/IiXGkIQTReOrpj6fMWqJz2/Qs5MhzG0bwZVTmGGeEUME0 jVyVvz/f93PXkoonLEHcSvgfFusTN+Kk69StO3MFUF1c/LWCNW0SLKhR3BTf4yLpVhzU XS0QZjKPwMP/lqNNRZmsp3yJ1QzQo8EYm64SeJmrB0H3igFDD5ILTWNHZ4xJOLDPbKRZ T+Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nag8Wqhp; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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During suspend, MHI device controller must be put in M3 state and PCI bus in D3 state. Add a recovery procedure allowing to reinitialize the device in case of error during resume steps, which can happen if device loses power (and so its context) while system suspend. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 105 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 2521cd4..3297d95 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MHI_PCI_DEFAULT_BAR_NUM 0 @@ -186,6 +187,7 @@ enum mhi_pci_device_status { struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; + struct work_struct recovery_work; unsigned long status; }; @@ -313,6 +315,50 @@ static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) /* no PM for now */ } +static void mhi_pci_recovery_work(struct work_struct *work) +{ + struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, + recovery_work); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + int err; + + dev_warn(&pdev->dev, "device recovery started\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* Check if we can recover without full reset */ + pci_set_power_state(pdev, PCI_D0); + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + if (!mhi_pci_is_alive(mhi_cntrl)) + goto err_try_reset; + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) + goto err_try_reset; + + err = mhi_sync_power_up(mhi_cntrl); + if (err) + goto err_unprepare; + + dev_dbg(&pdev->dev, "Recovery completed\n"); + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return; + +err_unprepare: + mhi_unprepare_after_power_down(mhi_cntrl); +err_try_reset: + if (pci_reset_function(pdev)) + dev_err(&pdev->dev, "Recovery failed\n"); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -327,6 +373,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!mhi_pdev) return -ENOMEM; + INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -391,6 +439,8 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + cancel_work_sync(&mhi_pdev->recovery_work); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); @@ -456,12 +506,67 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; +static int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + cancel_work_sync(&mhi_pdev->recovery_work); + + /* Transition to M3 state */ + mhi_pm_suspend(mhi_cntrl); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + pci_set_master(pdev); + + err = pci_enable_device(pdev); + if (err) + goto err_recovery; + + /* Exit M3, transition to M0 state */ + err = mhi_pm_resume(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to resume device: %d\n", err); + goto err_recovery; + } + + return 0; + +err_recovery: + /* The device may have loose power or crashed, try recovering it */ + queue_work(system_long_wq, &mhi_pdev->recovery_work); + + return err; +} + +static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, .remove = mhi_pci_remove, .err_handler = &mhi_pci_err_handler, + .driver.pm = &mhi_pci_pm_ops }; module_pci_driver(mhi_pci_driver); From patchwork Tue Dec 29 08:43:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353971 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371748jai; Tue, 29 Dec 2020 00:39:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyeIkLpwuTVUScPtdnAdew0/nqDnSujeu16fdmQAAFIpV7muvl2KxOZ3xQ5ZHVjoYdppj4u X-Received: by 2002:a17:906:b793:: with SMTP id dt19mr44545651ejb.120.1609231145827; Tue, 29 Dec 2020 00:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231145; cv=none; d=google.com; s=arc-20160816; b=MGTj9r9usAwb83+P2y/OxpOIwmzOZ+WvyOO7mG0UJbz0841bI/DQ57+2jiOh4y8Ahk ekdOYXL5yeJr+w1+Ql02aVbZ4XUtMbHIk0wFkxvz5oQANy+Mv8xBL8IT9oTTnAFSj/vo LBgNIVQdzKFbjSnNaFFNFcYELBlSDwzZRyK/iv1swMjX6i0GgUxNjw3c9uqKEYT6yf7z WCFBjxIvkdypGOn3ClpYw2HaqQ1VviJfdfmz+xIfn3z1cE7ZgOY7EFvBfm4ytkEFx5de eW3fHiz7bvaKeMxPPj6dangDhFKzVtYmwzZuFZkYGQ9X+ThFtTBBIROYuSkz9RIULMcO gDtw== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id y7si21816192edp.7.2020.12.29.00.39.05; Tue, 29 Dec 2020 00:39:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kIjp+hni; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726129AbgL2Ihs (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726148AbgL2Ihr (ORCPT ); Tue, 29 Dec 2020 03:37:47 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD450C06179E for ; Tue, 29 Dec 2020 00:36:32 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id 6so17221974ejz.5 for ; Tue, 29 Dec 2020 00:36:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HRI/zQl0AztAy0cvfEZ3YruuvCxYV1sLSbd5prZLqRg=; b=kIjp+hniPCKZ44zRL0Vx18QRUVIzMaVsZA57pEfDai8h15VI4yo0X6CFHvY+si8l2I gSwqr1UV3QD0l+MRrReqScthidY58WrYvttMtrw2Xjygr/DgLe3WQeHbKMHdyGO89Sbx MWpYYfNtk9yepxleziZGE892T4xps+lIxqaxiUtWSXgcXNjmulAQcJ/swJ4ZQBzSmQSf ka7R9b80qg0QzuPida/d/LbiZ0+a04pk8rU5Hq3tZNZolsWW2/b46O0aUhYExZfuqrGX M+H6RIDFckZU8UycrY3+O63ni/6acoOOT1qELuZxgqiFQR91yQGqEhddk9xvlTNmxg8v TyIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HRI/zQl0AztAy0cvfEZ3YruuvCxYV1sLSbd5prZLqRg=; b=msXJ7Kryd7W533AasSPH7UIg5UdE8M19nMdYBWLw5MOYu67+kWc5lEi68cFZXz/rNp Z5Z1svOV5hLHE/T5kUuXo9lAWwRorI8uzemHTv627UylH3onAWpIcsFrhy+d33NuVyE4 N628wfq0wxHFhBP1NjGn+zJXsLKK1IvDNPZk6mD34ydQHLVHD3Ehs5G0JUB1e0eW2Gfk DxZcszc4Knv8pUEH0Y82bEgG9VOD855Zrg7uXLI5eM5MVSe48Izp2ynT1ZH84YyMmpd2 Z0tWbnpBUqb4xdcUaYMrc8L3Co7HzkGgXg1YfXc6fkCy1LnnpDFdVHVJQNnXG8+UXfaL HYiw== X-Gm-Message-State: AOAM530kKZl0xZNTGu1qykc3sbbTrG+rQ3MkHYNUQM5jqSg/bRGu2+Yo aurN7YOeAcO9FQnUkjonAf784A== X-Received: by 2002:a17:907:da7:: with SMTP id go39mr46177746ejc.58.1609230991596; Tue, 29 Dec 2020 00:36:31 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.30 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:31 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 07/10] mhi: pci_generic: Add PCI error handlers Date: Tue, 29 Dec 2020 09:43:48 +0100 Message-Id: <1609231431-10048-8-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In AER capable root complex, errors are reported to the host which can then act accordingly and perform PCI recovering procedure. This patch enables error reporting and implements error_detected, slot_reset and resume callbacks. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3297d95..9fe1e30 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -405,6 +406,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_enable_pcie_error_reporting(pdev); + err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) return err; @@ -501,7 +504,54 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); + + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } else { + /* Nothing to do */ + return PCI_ERS_RESULT_RECOVERED; + } + + pci_disable_device(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) +{ + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_RECOVERED; +} + +static void mhi_pci_io_resume(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "PCI slot reset done\n"); + + queue_work(system_long_wq, &mhi_pdev->recovery_work); +} + static const struct pci_error_handlers mhi_pci_err_handler = { + .error_detected = mhi_pci_error_detected, + .slot_reset = mhi_pci_slot_reset, + .resume = mhi_pci_io_resume, .reset_prepare = mhi_pci_reset_prepare, .reset_done = mhi_pci_reset_done, }; From patchwork Tue Dec 29 08:43:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353973 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371755jai; Tue, 29 Dec 2020 00:39:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJweDKt04vlzfMpIPHHkA0Jp5LHcgOaVCLJ3cQf7vOSs3MNrv0QwT9/LX5RSXmiCVyIBLIpN X-Received: by 2002:a05:6402:129a:: with SMTP id w26mr46306827edv.355.1609231146648; Tue, 29 Dec 2020 00:39:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231146; cv=none; d=google.com; s=arc-20160816; b=TGJA64dQCjNTs/Wt4aQ95yg0cUIjmH1UPF52WxSA6B58tfj9Ow0GFtnoHOngE9RHYy o/egVjxearWgOuUY5TgcLHunEB6P4mdufvIu4RtZJnMnVhD8GzMFwA4GWdNDlf8qkPeG 6sLZg5GS1qBh/YhCVSUYOFpEz9ukT2cXz12JoY24UXSF90HtPDxokHJW8eNcFZPojQ06 A8WH9lJiVB7IwiWc68WfuK+cNjpaM41iWXxtfMKDsvzzt6fGoMgrFwTXbNRUey/9QXQb b3Fhli1M+8e51miBL468DIQdqmwOLco384b+YQ5jo1brLcrE9nTcRDXSAF7DS/Td+zBD e//Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=nEn/OUbK+5BNC0SGN0UoGUUqsvJDQ/HeZj3c89NIANo=; b=SwqmOBd/f4nDmycGzQx+EPAeh00C88V63ztzPLNmJ8qWQbIE9jZyRyLsM1at6RZVeL ZgYOGuEzk3dTKkyNltTVURwspau3A8BzczXoK/tqZDBX+Z1n1pEkEg6ZnRujz01k0evr QdtjdVLxK2y25DP0/CJaMbXLHegHufio4Uit6cvSCqC6H0mZCRb6kvfys4Gsd/b28eHO ruD+C/fj5QKqWp9DWU9N98qQLwy7Dsrw0Q+tP7+lNkMS4cUdO5XgjTLu3o/R/ZdHjDR1 mQS/dYf0hjAJbH/o1XTXTPeeSdW51QPWIEpMYp6PzdPLIscdX1GuspkOMUShJRwq/RAR Apcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fcZmAhjj; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si21816192edp.7.2020.12.29.00.39.06; Tue, 29 Dec 2020 00:39:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fcZmAhjj; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726144AbgL2Iht (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725986AbgL2Ihs (ORCPT ); Tue, 29 Dec 2020 03:37:48 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0896C06179F for ; Tue, 29 Dec 2020 00:36:33 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id cw27so11929977edb.5 for ; Tue, 29 Dec 2020 00:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nEn/OUbK+5BNC0SGN0UoGUUqsvJDQ/HeZj3c89NIANo=; b=fcZmAhjjN9QIRsJR0/Qu3yoCpFrMb6Q/D4THDmAVq7oG2/tbNO7EAHf/z6m6ykLbzV WURTVzuQqOpfXEMTKou0FM7q6lQu3cv/dA6+VApIR1mnBhaq79qzF+CySJusMlxcGMA0 yu8MVeU9FF3wFia6F8S7piYpUrYnIYdj+W91dC2JgcJrkgGO3s0En5edNiOVLzwS5/8q EMN82+xbKp84YtZMGAvi/BIn4c/MXEyykU67GdjtenqE3xRzYnxxzN8ds6FgXSW41DmJ rUC742/h7jeIdmU+yUw4ar0GJZ7b4vUrAYOpaGLREG/X+DHK32IK10JUaSr3h+VcmRcv wDeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nEn/OUbK+5BNC0SGN0UoGUUqsvJDQ/HeZj3c89NIANo=; b=kcbuPeCK7EB8pSYCWW+MrceFbmvg5JeVzIJ60hCw4/5smT/I+F6A/TFRNstYuhFDQl BZ4EUEQmCnoWfVDrV3YMccxRvmp97FSHrmzBRRoBKf1xftHoiho0p2MQYVpaoiQ7FLSC wsZaR5nwgUNEV/yLf4EgciEHtRYjNWzfo6P9dwXgFXONbtrtVzml27F+0/d5Qk5I8L77 EtviecieIan9mnP7vi3r7Vb6lSjSw2QWvE+2PdcbsafV06vQ9rLY1Pxjb/NBVB/BBFio dPz66qecNyTXsk4Px0//tuJDpNJumgmrR5ur11m4QpIcN3dpLGamBzIU/8C+xv8xUKyL 8F6g== X-Gm-Message-State: AOAM532L3StNhXY6cUYCSS175+8d8Lez1gUClNy9bgfU35WRQrtQAs4y ivZ9WgRHx7AQuEH9XoOXG/pcTQ== X-Received: by 2002:a50:d888:: with SMTP id p8mr45538202edj.147.1609230992532; Tue, 29 Dec 2020 00:36:32 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:32 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 08/10] mhi: pci_generic: Add health-check Date: Tue, 29 Dec 2020 09:43:49 +0100 Message-Id: <1609231431-10048-9-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the modem crashes for any reason, we may not be able to detect it at MHI level (MHI registers not reachable anymore). This patch implements a health-check mechanism to check regularly that device is alive (MHI layer can communicate with). If device is not alive (because a crash or unexpected reset), the recovery procedure is triggered. Tested successfully with Telit FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam Reviewed-by: Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 9fe1e30..812d54f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,11 +14,15 @@ #include #include #include +#include #include #define MHI_PCI_DEFAULT_BAR_NUM 0 #define MHI_POST_RESET_DELAY_MS 500 + +#define HEALTH_CHECK_PERIOD (HZ * 2) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -189,6 +193,7 @@ struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; struct work_struct recovery_work; + struct timer_list health_check_timer; unsigned long status; }; @@ -326,6 +331,8 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -351,6 +358,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_dbg(&pdev->dev, "Recovery completed\n"); set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); return; err_unprepare: @@ -360,6 +368,21 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_err(&pdev->dev, "Recovery failed\n"); } +static void health_check(struct timer_list *t) +{ + struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return; + } + + /* reschedule in two seconds */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -375,6 +398,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENOMEM; INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + timer_setup(&mhi_pdev->health_check_timer, health_check, 0); mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -427,6 +451,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + /* start health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_unprepare: @@ -442,6 +469,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -459,6 +487,8 @@ static void mhi_pci_reset_prepare(struct pci_dev *pdev) dev_info(&pdev->dev, "reset\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -502,6 +532,7 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) } set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, @@ -562,6 +593,7 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); /* Transition to M3 state */ @@ -597,6 +629,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) goto err_recovery; } + /* Resume health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_recovery: From patchwork Tue Dec 29 08:43:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353974 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371758jai; Tue, 29 Dec 2020 00:39:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJyc1tQqbgLL258Cdmmoo6Xlsg6OeerOWSh4w0akN5NsT6HJ5Yb1cdTmwHOZ1rX3wAkDeEEB X-Received: by 2002:a05:6402:1714:: with SMTP id y20mr44428191edu.360.1609231147031; Tue, 29 Dec 2020 00:39:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231147; cv=none; d=google.com; s=arc-20160816; b=YHii5SEVKBPPWB/N60ksjEvyS9HS4Iv6zCizSomopzzNrHTWZ6NGjJFoH/SUd28A4P R4A2xLrTT0pzcz+cQn4mcu/tL+k0KTRWKOMrCwxWKdRPTrS/bZd1Q2vb6OcMGx09ZFlg 7C6SQ7Z9sFa5JOFp3fdje8xdzvNL2EuG/caTb2rI3BGIgtWt/mG5wNE4rEPip6CQC7Hb mjVCkbOdeCsC8+nk1dYRkN/lqP8E1Z9yJ+xi/izr6HmzHMiz6xojukXUHRh85V5EnPIU Sqji4qqJZKrksNGp54m7PlejFQ4LReqNurmXU8rNbf/fJHQnUyR9sJD/8vNQkc+faUfK 7Puw== ARC-Message-Signature: i=1; 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Increase the timeout to prevent MHI power-up issues. Signed-off-by: Loic Poulain Reviewed-by: Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 812d54f..d4ad9c5 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -162,7 +162,7 @@ static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .max_channels = 128, - .timeout_ms = 5000, + .timeout_ms = 8000, .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), .ch_cfg = modem_qcom_v1_mhi_channels, .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), From patchwork Tue Dec 29 08:43:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 353975 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp10371764jai; Tue, 29 Dec 2020 00:39:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJzY3bsO6Y2/Oz3XwCfVhZiMw9s+2YN060MDKAi7uTOOGlYLk6fBzUzgYpExn1yzpzRpIEW9 X-Received: by 2002:a17:906:f85:: with SMTP id q5mr45374443ejj.105.1609231147476; Tue, 29 Dec 2020 00:39:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609231147; cv=none; d=google.com; s=arc-20160816; b=GRQBG+jXZthnzNlobDEvxflmqgxRj58mF3dhImkWPYY70AqL7cJMwUFbeKFvN6jVFd Dn1Q1PYB+msbgA6e5c1g0ij9+3Hw3QDy0SRsknI7bbOZs+jxiaKKD1Ckr/W3d+AUMAi7 ib+xxHoYeFO2Rpw7++iFjCf9ogcG8GajuZnxux3pNanJbj1+pEY4rbc2jWdYLK1oXh89 lVfS6C8mlq5uGl5t2lKe2aFNJYepHMXz9EFyMe1GcU0RxkWosubew3k/plFCUSTONLoc 0k8yhnNLXUpWMTA8jGfarH5vUSMoPz8CPNGDEOf6Y8TV3q6AleU4aNqknaRQBi/aJvWW qA3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=+H0dqYG1zJyMCHg6k54AsatNRlQKpuVWQQhBEPb2DEA=; b=GzrlKcqrBaWijFaTu0B1o+5Q5hEI8xprIaJMRwSYx/1kS7j+IxtiP1duOLnGBo/UOh 9q5o4uWeMTu7b/5N3FpnmPwHLA8LoMia3hMkMIsWBGCzPixqyt7PNjTov6rsWWfXKR8x YR8G/j++0LIWmpJSlqAHKQ0fp8POSXRzf/uvw6jYPeaGA7CvZ22/jZMPvBrkIaM/5oVQ 3UwT4qKoRGfcNqAFLBVkF5tdPmg07slJz2tA436BVr+kxcsHhgBg41oW1Evro1H7mvbH pGs25GgegiSiC/ILWWtF7nGahN8FNAdrKRFJxE2qte6HGqTItLy9PMs3YMeyhvQZ8u6t UCUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ciIi0yjK; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si21816192edp.7.2020.12.29.00.39.07; Tue, 29 Dec 2020 00:39:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ciIi0yjK; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726240AbgL2Ihu (ORCPT + 15 others); Tue, 29 Dec 2020 03:37:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726264AbgL2Iht (ORCPT ); Tue, 29 Dec 2020 03:37:49 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88946C0617A1 for ; Tue, 29 Dec 2020 00:36:35 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id d17so17192360ejy.9 for ; Tue, 29 Dec 2020 00:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+H0dqYG1zJyMCHg6k54AsatNRlQKpuVWQQhBEPb2DEA=; b=ciIi0yjKN2k6PdIwtTm0CtmzO2GKzKG7E0PRkecbE1FS3cUQVCiX4BFwohRAsDYTcf e953sx74/jx1AtMQ22bh4WcXXn734hOh8RMKPGPqY4am5udPZsRb0jUA9Sm44QPTbk05 SR+KOsGOv6F80e58htmaJFBtwmMYsO158VNAcJtIy3LMVmgG/dFIma08PbdO6vwcVq6J TVJSAsEvYvh64ink5wjh6oHFp5xXKOOcikC8nzuQNvfYi4JCn9CfBHoh4X82sIkg+9m4 m4M+IJ2ehNOFPVeanhSxlAHJAm5shmahrWWbQVYMXe/hJ3CegQ1/fgdOOMcMY4Nlek0O XclQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+H0dqYG1zJyMCHg6k54AsatNRlQKpuVWQQhBEPb2DEA=; b=ukGJ1/IZsVKQ2N4bn/WcXvzAJOi3rBYS1eK8QBtEmZYcT8ed4pEOmf2KOigKct5VoO oBLixE3W7utEDc2U83ckV1AKGyD1CHQIB2YuC/98fJPa1LtNYCCxyVnHMVBHniv4B0is tkQp2+nd6HGpI8dAR/n9mCUFpijDehhZDaWaoUmJNDPjn4pnZAQciVq0hd0ilNJY+W5s jjWTAn2t1UccoT9t/VsUpEOvO6lg2EkZ9n0UBBd3tP7qcrmgVTyIgHqY3dhq2SZBSmVB Lt1p3sMamq37TO1JbgCqcdxD83jj0f17tLihZ282Mlg20CSiXcJ6xbs2LeC8vWFd5cIB GsUw== X-Gm-Message-State: AOAM532x/onk59xgNz+K4tYFsc5uHVFtJba7vqNNvbrEHTUEx9nREYcU Cbfyn31KW9flmJpTYpypa/Bhw/40RmGQVA== X-Received: by 2002:a17:906:d101:: with SMTP id b1mr25883339ejz.80.1609230994259; Tue, 29 Dec 2020 00:36:34 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:6f69:290a:2b46:b9]) by smtp.gmail.com with ESMTPSA id c23sm37265143eds.88.2020.12.29.00.36.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Dec 2020 00:36:33 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v6 10/10] mhi: pci_generic: Add diag channels Date: Tue, 29 Dec 2020 09:43:51 +0100 Message-Id: <1609231431-10048-11-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> References: <1609231431-10048-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Diag over MHI. Qualcomm Diag is the qualcomm diagnostics interface that can be used to collect modem logs, events, traces, etc. It can be used by tools such QPST or QXDM. This patch adds the DIAG channels and a dedicated event ring. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d4ad9c5..0947596 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -142,22 +142,26 @@ struct mhi_pci_dev_info { } static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ MHI_EVENT_CONFIG_CTRL(0), + /* DIAG dedicated event ring */ + MHI_EVENT_CONFIG_DATA(1), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(1, 100), - MHI_EVENT_CONFIG_HW_DATA(2, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 101) }; static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {