From patchwork Thu Feb 15 12:49:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 128418 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1711500ljc; Thu, 15 Feb 2018 04:50:50 -0800 (PST) X-Google-Smtp-Source: AH8x226WR0K02aXX3l0H021cooLKg9QqZHIimH5R+TrCVAN4JAEYlpu0l1KazK8Cx/OvabOKKWRG X-Received: by 2002:a17:902:208:: with SMTP id 8-v6mr2462437plc.359.1518699050720; Thu, 15 Feb 2018 04:50:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518699050; cv=none; d=google.com; s=arc-20160816; b=TZnthGSg3HlRQFwZINAUHm6EfNavQ2w7xSyqRH7rEUK5OLsrxLt4cGPabIg8SgT0vK II++ugOTmjNWAeMDBLTqDVy8H5MDztHPWbkUsXmDIpH2ZXgLCkG2fcX88kKzvkP7QyNT ARY4ALheHI2jLgHhODbfHdxIRvF9y4Hck1rYWNmxbfkoUVnWyDB6ZM6jm1E1ixiDSWLS iEAszjOlhJ8cnYs2b8miwWaK18YaK5cV0SLkZv3frIzXMW2Vgkwy5FSViPBZDppnbn0C WXe/webtWvGrEB0D7noGgRMa32IKbHKLHS0R82C/PSKT2O5DO/Z8jupQWQWuXdAcJWqy 2tqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=ZxMsSkqScbYFsDrnJfoup1Xntb6MFJDF/f3JU+5GPMo=; b=o7bK8Tl9OzulodqSlci5MR+2lwc/CA2HCHCqzzI3xF10/Dgc6j/+pEHEzk1P4u1xJW U/t4rSANn4UK3RsawUHAIwe6hOqnnzdcfJ0v3V9vxSOfbaKFHhIYn+WsTpiUmIUd58Lg jfnd0rxnuRRdxJ+w7H0PXzGMO5oocZJbtielDO0qlJYXIjy2x39M1zVlCx13kt0AeNkF syts2gyP+SVsXW5gSCjFWK+vBxlmqb3F++lGOT2j4k5wsDFY2v/RYcXLkS15EaZ3Uaet DXlpEXUMybtjjH62QuixGU1G/L454FW7Rk67Bi7TRfcyoxybdlC0GC/vRaJ197ifvcTx V61g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Nu7+1lbP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z8si2502582pgs.605.2018.02.15.04.50.50; Thu, 15 Feb 2018 04:50:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Nu7+1lbP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030852AbeBOMus (ORCPT + 6 others); Thu, 15 Feb 2018 07:50:48 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:19497 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031323AbeBOMuq (ORCPT ); Thu, 15 Feb 2018 07:50:46 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1FCoQgv011073; Thu, 15 Feb 2018 06:50:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518699027; bh=AQUwByd32+h+qmRivffAHa5wE9h0APX85xne+oDniqE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Nu7+1lbPTwlcexll1RRG/kk2LkzW75nRT0Ke26k+zVtLGTIm5tXE1zjRsoJaGwbza 3J7D43T4bN6JE+orvRwqpInYxzwk/6emO7GDnYZkG5yoDCFf68QW9oihmWPet9I+Gx z+iaYu47Aetlu4+YyIiNtBj00U3Q3hFWYgiAHDug= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoQTN012242; Thu, 15 Feb 2018 06:50:26 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 15 Feb 2018 06:50:26 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 15 Feb 2018 06:50:26 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoKZD020487; Thu, 15 Feb 2018 06:50:24 -0600 From: Tero Kristo To: , , , , , CC: , , Subject: [PATCH 1/5] dt-bindings: clock: ti: add latching support to mux and divider clocks Date: Thu, 15 Feb 2018 14:49:47 +0200 Message-ID: <1518698991-10099-2-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518698991-10099-1-git-send-email-t-kristo@ti.com> References: <1518698991-10099-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain hardware configurations, like dra76x, have some of the clock registers partitioned in a funky manner that requires the clock control setup to be latched for PRCM to be notified of the change. This is accomplished with a separate control bit under the register. Add support for this clock latching support to divider and mux clocks. Signed-off-by: Tero Kristo --- Documentation/devicetree/bindings/clock/ti/divider.txt | 3 +++ Documentation/devicetree/bindings/clock/ti/mux.txt | 3 +++ 2 files changed, 6 insertions(+) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt index 35a6f5c..9b13b32 100644 --- a/Documentation/devicetree/bindings/clock/ti/divider.txt +++ b/Documentation/devicetree/bindings/clock/ti/divider.txt @@ -75,6 +75,9 @@ Optional properties: - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, see [2] - ti,set-rate-parent : clk_set_rate is propagated to parent +- ti,latch-bit : latch the divider value to HW, only needed if the register + access requires this. As an example dra76x DPLL_GMAC H14 divider implements + such behavior. Examples: dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index 2d0d170..eec8994 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -48,6 +48,9 @@ Optional properties: zero - ti,set-rate-parent : clk_set_rate is propagated to parent clock, not supported by the composite-mux-clock subtype +- ti,latch-bit : latch the mux value to HW, only needed if the register + access requires this. As an example, dra7x DPLL_GMAC H14 muxing + implements such behavior. Examples: From patchwork Thu Feb 15 12:49:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 128419 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1711642ljc; Thu, 15 Feb 2018 04:51:02 -0800 (PST) X-Google-Smtp-Source: AH8x225jEsLJgArwMb5ywIAY7UY4jFHwLauxmejNgQ8Tmo+kSFCs3f1iyT1PqfmQDLL79d1IrZWV X-Received: by 10.98.131.139 with SMTP id h133mr2543430pfe.155.1518699062235; Thu, 15 Feb 2018 04:51:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518699062; cv=none; d=google.com; s=arc-20160816; b=PhlCk/OSholdpJQTX5Ce7DtN+WQG+fQBzJ24Bzddmcu+wkCVskxcaDPZExEoORR8lL MBWKd9tKw0ksaftKnNYdhaLoy2HyZtxPPD9+QBFDrMg9WSwlCA8VliYGV4U+j5qKw5w+ MG0I81hsGqEGmgR94oZ65hrYLRFgq7GH1vleKcdYBr3XaVk7cbvPW5kehY5YbZ7/+bUk IyZrMxWRYRTNskGSGz1zZIN5Tjqqx+6OfiZM4T4zicM92brHqI7i1J0J8Ko2N6d5bPpy 7hd11Bz8mrAfE71fsp6y1fIg+3D90uzB6uXDTvqiQnfcbEQ8DpRZfr6EuHU1+3xRO4GY C9Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=bvWsoVxg0dEQ1jkqrIg/SDLP1yxyy8G507LtM9fvtp8=; b=AHPRxuLQPQppEGbpmT3+c3lwKGHiFoJ4C+3VplhqaTT0LCZFlhQLjH+UyVqAFEEnTR /b2+t4VCqUmN3KQrIgtgprh2Oey4/SJDCXSbFDUVKwkkhb5wp8jiSujTCdYNWkmUDJD0 xT4GejXbADYPirT4xEOpGRoDHQ1nXxg5irzVHHh6Rurmk1fowShEFp+6q+rOIUSEBbV9 n15uI6fllglGRRfjWZz0fXmWH+N4bTkESyuxpzWSe1Y+oFuCoNMIuzQY4Q8Xh3QEk1i6 +SipPMKy0JEBWoXsNiHFhjx2L+Fmx81RLRzLk3A21yw7mUzoF2sHV0PAapEQ+8K5co+g HAmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=xJ5h1NM9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m8si2411357pgu.551.2018.02.15.04.51.02; Thu, 15 Feb 2018 04:51:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=xJ5h1NM9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031392AbeBOMvA (ORCPT + 6 others); Thu, 15 Feb 2018 07:51:00 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:50156 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030843AbeBOMu6 (ORCPT ); Thu, 15 Feb 2018 07:50:58 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1FCoXjF016586; Thu, 15 Feb 2018 06:50:33 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518699033; bh=nO9o+CTZYPN96Bjucl1B4bwNvPkrNh6Y8Rz51aGsZWE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xJ5h1NM94P7mz4LvEYRwauufu0wmnl0kHYXrIeOrBv6h/x8XiVZXMFPxnbgtoB6BY oms6D9j6oJqQ/1eKn/ZpjBBmCte6+ifhaeQFThMQ4ZtUY7VCNEhHr2OwAhZfpdBZZ5 Jzxaj0W8bJA2mCPL4tNDbanqZMd/Cam49CaC7XQs= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoWnk012400; Thu, 15 Feb 2018 06:50:33 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 15 Feb 2018 06:50:32 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 15 Feb 2018 06:50:32 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoKZF020487; Thu, 15 Feb 2018 06:50:30 -0600 From: Tero Kristo To: , , , , , CC: , , Subject: [PATCH 3/5] clk: ti: add generic support for clock latching Date: Thu, 15 Feb 2018 14:49:49 +0200 Message-ID: <1518698991-10099-4-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518698991-10099-1-git-send-email-t-kristo@ti.com> References: <1518698991-10099-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain clocks require latching to be done, so that the actual settings get updated on the HW that generates the clock signal. One example of such a clock is the dra76x GMAC DPLL H14 output, which requires its divider settings to be latched when updated. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk.c | 14 ++++++++++++++ drivers/clk/ti/clock.h | 2 ++ 2 files changed, 16 insertions(+) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 4efa2c9..7d22e1a 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -275,6 +275,20 @@ int ti_clk_get_reg_addr(struct device_node *node, int index, return 0; } +void ti_clk_latch(struct clk_omap_reg *reg, s8 shift) +{ + u32 latch; + + if (shift < 0) + return; + + latch = 1 << shift; + + ti_clk_ll_ops->clk_rmw(latch, latch, reg); + ti_clk_ll_ops->clk_rmw(0, latch, reg); + ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ +} + /** * omap2_clk_provider_init - init master clock provider * @parent: master node diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index d9b43bf..2f8af8f 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -194,6 +194,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); void ti_clk_add_aliases(void); +void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); + struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, From patchwork Thu Feb 15 12:49:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 128421 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1711861ljc; Thu, 15 Feb 2018 04:51:19 -0800 (PST) X-Google-Smtp-Source: AH8x2250DjduQu7qQUCKNhHil8VTq/F5sjoo6wx6JWEGEBx5AggW+z8Q+XYB6oBhxW5F8qrX2CJA X-Received: by 2002:a17:902:2845:: with SMTP id e63-v6mr2437668plb.438.1518699079212; Thu, 15 Feb 2018 04:51:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518699079; cv=none; d=google.com; s=arc-20160816; b=kiY6kR+6QLBjOAm8dDivmcoHhq5TLneMV436ldEXZtZmqeDUpMehBMJhlbPCMpHUUO qUb6GsNX9PbxpJBL1UBvWl0M3jVigL+pk9lA+EVS+bJ2uK9qZ2C6IuipjBDKCXI6utiv ZEY9jirZwNDEEhW9GFwiPOuFmdmFWPn4KLsY6l8p5FoW8cx1zbTqNKtGFKSERX+DjdrM 8pbaYlmAg6GR8UUSQHUPosvnccV6GCuEwlscukbomrWBF/zqqvN4m48ByJrG78B6bSuy 4Mxr7YlQv2z64scYCH9MkMCqsFIBydJAT3kWXoP61d7GPW5OohWlbd1P5yKX2+08FE12 YUsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=r6UvAf4fdj4luo6Ywokd8xH/2I4rDmDXk1BRsx6d2Jo=; b=e74lC6F0+m2V0eLAH88c5EXj/L4VY3k03/kYlj9ZJsStFe6H8gtlCrWzn7O4X7d3rE Bxo1FpwFAVlvngVlWp1b1D+mjRuLhCnQiwuev2RgM4U5KI9/lsOOiHDovAt9vSImI+T6 gp/5+fN8ftjzGQq+R5G8sLv7bZzkrgLk0PoK1AEQGD3Wi+berF3UpK1HONa/snVb1lqz RwirSDHOSsi7v36+yzVuSCuJOSXTpPFYzNUcpb27aIoS0yG7hU5EIjBpzpvfNtwr9AHV iIPHc8ANKzD4ozPAGs4KG3Qi+07/RCugidMJzxzVGMiM/R3HAdbd767KXT2j1iiO7Tbg 5jhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=bvZrINaO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m8si2411357pgu.551.2018.02.15.04.51.19; Thu, 15 Feb 2018 04:51:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=bvZrINaO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031323AbeBOMvS (ORCPT + 6 others); Thu, 15 Feb 2018 07:51:18 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:50169 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031225AbeBOMvR (ORCPT ); Thu, 15 Feb 2018 07:51:17 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1FCocPn016594; Thu, 15 Feb 2018 06:50:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518699038; bh=tEu7BHXSW4cmgfIMHpz9RVQFm2pP9qctLaYqgL5BdHM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bvZrINaOwI8JvOR/wO+UtTWzS5Ry9+6TqQGGkFD2jeGu2GrzKmAF713Y4VKRVIfs8 NqIeP7DKIUFD8LpTi8ChPf8iZFZjTe77pQMIK8YzUGGY4b7HitO4HdfvPxpP+sr/Pw e22M14Ve5QQyervY/Zv7RmNQCB8hWc82B+SIlTrE= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoc4V019141; Thu, 15 Feb 2018 06:50:38 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 15 Feb 2018 06:50:37 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 15 Feb 2018 06:50:38 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoKZG020487; Thu, 15 Feb 2018 06:50:32 -0600 From: Tero Kristo To: , , , , , CC: , , Subject: [PATCH 4/5] clk: ti: add support for clock latching to divider clocks Date: Thu, 15 Feb 2018 14:49:50 +0200 Message-ID: <1518698991-10099-5-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518698991-10099-1-git-send-email-t-kristo@ti.com> References: <1518698991-10099-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Latching the clock settings is needed with certain clocks, where the setting is "cached" in HW before doing the actual re-programming of the clock source. This patch adds support for clock latching to the divider clock. Signed-off-by: Tero Kristo --- drivers/clk/ti/clock.h | 1 + drivers/clk/ti/divider.c | 26 ++++++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 2f8af8f..62b108c 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -22,6 +22,7 @@ struct clk_omap_divider { u8 shift; u8 width; u8 flags; + s8 latch; const struct clk_div_table *table; }; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 77f93f6..aaa277d 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -263,6 +263,8 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val |= value << divider->shift; ti_clk_ll_ops->clk_writel(val, ÷r->reg); + ti_clk_latch(÷r->reg, divider->latch); + return 0; } @@ -276,7 +278,8 @@ static struct clk *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct clk_omap_reg *reg, - u8 shift, u8 width, u8 clk_divider_flags, + u8 shift, u8 width, s8 latch, + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk_omap_divider *div; @@ -305,6 +308,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, memcpy(&div->reg, reg, sizeof(*reg)); div->shift = shift; div->width = width; + div->latch = latch; div->flags = clk_divider_flags; div->hw.init = &init; div->table = table; @@ -420,6 +424,7 @@ struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup) div->table = _get_div_table_from_setup(setup, &div->width); div->shift = setup->bit_shift; + div->latch = -EINVAL; return &div->hw; } @@ -452,7 +457,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) clk = _register_divider(NULL, setup->name, div->parent, flags, ®, div->bit_shift, - width, div_flags, table); + width, -EINVAL, div_flags, table); if (IS_ERR(clk)) kfree(table); @@ -556,7 +561,7 @@ static int _get_divider_width(struct device_node *node, static int __init ti_clk_divider_populate(struct device_node *node, struct clk_omap_reg *reg, const struct clk_div_table **table, - u32 *flags, u8 *div_flags, u8 *width, u8 *shift) + u32 *flags, u8 *div_flags, u8 *width, u8 *shift, s8 *latch) { u32 val; int ret; @@ -570,6 +575,13 @@ static int __init ti_clk_divider_populate(struct device_node *node, else *shift = 0; + if (latch) { + if (!of_property_read_u32(node, "ti,latch-bit", &val)) + *latch = val; + else + *latch = -EINVAL; + } + *flags = 0; *div_flags = 0; @@ -606,17 +618,18 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) u8 clk_divider_flags = 0; u8 width = 0; u8 shift = 0; + s8 latch = -EINVAL; const struct clk_div_table *table = NULL; u32 flags = 0; parent_name = of_clk_get_parent_name(node, 0); if (ti_clk_divider_populate(node, ®, &table, &flags, - &clk_divider_flags, &width, &shift)) + &clk_divider_flags, &width, &shift, &latch)) goto cleanup; clk = _register_divider(NULL, node->name, parent_name, flags, ®, - shift, width, clk_divider_flags, table); + shift, width, latch, clk_divider_flags, table); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -639,7 +652,8 @@ static void __init of_ti_composite_divider_clk_setup(struct device_node *node) return; if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, - &div->flags, &div->width, &div->shift) < 0) + &div->flags, &div->width, &div->shift, + NULL) < 0) goto cleanup; if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) From patchwork Thu Feb 15 12:49:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 128422 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1711966ljc; Thu, 15 Feb 2018 04:51:26 -0800 (PST) X-Google-Smtp-Source: AH8x226Ng88/RcE28PfzhZnAaPLsmVSY1h0g7LtPl/EJdGVz5+YFcVVv0CmtZZCIUmpSszsq+8Qp X-Received: by 10.99.171.70 with SMTP id k6mr2189349pgp.355.1518699086209; Thu, 15 Feb 2018 04:51:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518699086; cv=none; d=google.com; s=arc-20160816; b=JVWc1AJnxjnBdE0+u993mqgZ2YXZDgYy0zU8b4DyAMoMtPJbTupABtOP+O+eUlFQHR BoBJ2O2LYJv4o3JOkEpRMVRTY35PCyDzCNyLRI5Tq2DfAHBSvV34u7LAIIxNXW1+yUmL TZDgxFCdZy1fMtoqeh5yb5tIMwJVyHQ3xbxWGZUTMW8RRn+tPyB2SAH4tGN+XxEdfyEG DMd0V/OCCNl/Jfohwegdp2FGt7bbWP3TBm/qPa5i5wu/nyIgcNbx8VEcliQ3xRTXHtSJ 2tpeNkJDknjJTekFoeY/dWT1RCDXvVfEf225aGEsdh4r2SiOo1RqLBK7cmBmvZbhWGvy +8xw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id m8si2411357pgu.551.2018.02.15.04.51.25; Thu, 15 Feb 2018 04:51:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=mawsbFWk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031479AbeBOMvY (ORCPT + 6 others); Thu, 15 Feb 2018 07:51:24 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:50171 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031225AbeBOMvX (ORCPT ); Thu, 15 Feb 2018 07:51:23 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1FCohRV016602; Thu, 15 Feb 2018 06:50:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518699043; bh=yiNuqhsw8qa81EkXTtFU7T0Uo9mwtXZXA6mMz8UldUM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mawsbFWkU8fgNGgR+X+GY9DebisakyuayXnaZvfnrjqz2eRRm1/ex6a8vWh3EeaRL cNWsWsi3ss5g5xkkLHwS+kHfDJ+ssAPZI2rT7k7WAZfvcJfgCCIlUwWCMY00P98Z9D 4UglVhCI5QIwxzk/axw0cc/r5ywkL4iB+giTX7b0= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoh44012538; Thu, 15 Feb 2018 06:50:43 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 15 Feb 2018 06:50:43 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 15 Feb 2018 06:50:43 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1FCoKZH020487; Thu, 15 Feb 2018 06:50:38 -0600 From: Tero Kristo To: , , , , , CC: , , Subject: [PATCH 5/5] clk: ti: add support for clock latching to mux clocks Date: Thu, 15 Feb 2018 14:49:51 +0200 Message-ID: <1518698991-10099-6-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518698991-10099-1-git-send-email-t-kristo@ti.com> References: <1518698991-10099-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Latching the clock settings is needed with certain clocks, where the setting is "cached" in HW before doing the actual re-programming of the clock source. This patch adds support for clock latching to the mux clock. Signed-off-by: Tero Kristo --- drivers/clk/ti/clock.h | 1 + drivers/clk/ti/mux.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 62b108c..90b86aa 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -34,6 +34,7 @@ struct clk_omap_mux { u32 *table; u32 mask; u8 shift; + s8 latch; u8 flags; }; diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index d470580..69a4308 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -86,6 +86,7 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) } val |= index << mux->shift; ti_clk_ll_ops->clk_writel(val, &mux->reg); + ti_clk_latch(&mux->reg, mux->latch); return 0; } @@ -100,7 +101,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, struct clk_omap_reg *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) + s8 latch, u8 clk_mux_flags, u32 *table) { struct clk_omap_mux *mux; struct clk *clk; @@ -121,6 +122,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, memcpy(&mux->reg, reg, sizeof(*reg)); mux->shift = shift; mux->mask = mask; + mux->latch = latch; mux->flags = clk_mux_flags; mux->table = table; mux->hw.init = &init; @@ -160,7 +162,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) flags |= CLK_SET_RATE_PARENT; return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, - flags, ®, mux->bit_shift, mask, + flags, ®, mux->bit_shift, mask, -EINVAL, mux_flags, NULL); } @@ -179,6 +181,7 @@ static void of_mux_clk_setup(struct device_node *node) u8 clk_mux_flags = 0; u32 mask = 0; u32 shift = 0; + s32 latch = -EINVAL; u32 flags = CLK_SET_RATE_NO_REPARENT; num_parents = of_clk_get_parent_count(node); @@ -197,6 +200,8 @@ static void of_mux_clk_setup(struct device_node *node) of_property_read_u32(node, "ti,bit-shift", &shift); + of_property_read_u32(node, "ti,latch-bit", &latch); + if (of_property_read_bool(node, "ti,index-starts-at-one")) clk_mux_flags |= CLK_MUX_INDEX_ONE; @@ -211,7 +216,8 @@ static void of_mux_clk_setup(struct device_node *node) mask = (1 << fls(mask)) - 1; clk = _register_mux(NULL, node->name, parent_names, num_parents, - flags, ®, shift, mask, clk_mux_flags, NULL); + flags, ®, shift, mask, latch, clk_mux_flags, + NULL); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -234,6 +240,7 @@ struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup) return ERR_PTR(-ENOMEM); mux->shift = setup->bit_shift; + mux->latch = -EINVAL; mux->reg.index = setup->module; mux->reg.offset = setup->reg;