From patchwork Mon Jan 4 08:11:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 356447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BA4AC4332B for ; Mon, 4 Jan 2021 08:13:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 004CE22286 for ; Mon, 4 Jan 2021 08:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726236AbhADINA (ORCPT ); Mon, 4 Jan 2021 03:13:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726026AbhADINA (ORCPT ); Mon, 4 Jan 2021 03:13:00 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A338BC06179E for ; Mon, 4 Jan 2021 00:11:42 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id w6so16043077pfu.1 for ; Mon, 04 Jan 2021 00:11:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CxihuApHeST5FtR1ic0MIOxlrYHGlIn3irwCDLvd5sM=; b=BpAHH4z7dBz+9MtlkHURf9h9Jom69vFHB+b4oROjoPES4tpnQZcIHzUGTYA6HA4we2 NvQH40Hhy/8qTIFq89IboeKBQoo3kWTl4AZUy9cvRjjYzoTeCwqKGc+PTZELhs9DkJv4 wSy6pyD6zbAg7cY5t/xJ769muFVFQUzII4m+WmHUdeGllqDotmtOr9Z3n7KrNC45FfPg tCLg8zSz56Pqqohri8sSaSxwdmTpb41Z8HozHaDHKwZ+pDfMv6GjBOLl+DvDWXmqdzk0 PT4EEXLVxdhzMpeffC66L4pOMl/dbaMlcJbxT2UmoO+TEoR5og1/zpw8xVNpjJGwOMvR vGlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CxihuApHeST5FtR1ic0MIOxlrYHGlIn3irwCDLvd5sM=; b=thySmGn65bvlaq4ytJ5EG1O2Rb5Hb4HsvjuvSQ2n7s9zYn5HjcDiJXZeFSr1V0oLWa feitOvSuTQdzBE/vLAMIl69PFlCxHO8L0lRSLlqMecKVFaguL0sd9uIUkaJzuD6HVf+D ICuuDkjVmm5RDqQN6kEMm9zxlPAjfD9Sv/2J9R8LngPQkXl97YJt27IfQfRCVgvksxBS CNKdODDW1sf2aGpaDdbRGjzeNHQ6LG7nPTqp9+Oc3/iRw3dtZyK8SMxUSjrFBUiUL0L0 DEmxxVg7qFtSqQ3yWyMnJ2VQwA9rPirWngi/gUiuhspeygxUs2IxuunMi62EmZma7d8B 64hg== X-Gm-Message-State: AOAM5303+UASPDQRBirj7LOljeRXde8CWDlRxSwOLpryGsKHA1gvD4uz oLefhBdgG1aMt6FDU3xwtK0+EyhpVtfG X-Google-Smtp-Source: ABdhPJzsUzP25IuIbNHbmlezqcHXoggp/NpOFZ6YItSIZh0LEJkTFEBCupvJVazPbqroM29RL8ffzg== X-Received: by 2002:a65:458e:: with SMTP id o14mr64244220pgq.444.1609747902114; Mon, 04 Jan 2021 00:11:42 -0800 (PST) Received: from localhost.localdomain ([103.77.37.160]) by smtp.gmail.com with ESMTPSA id n7sm55051339pfn.141.2021.01.04.00.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 00:11:41 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: mailbox: Add binding for SDX55 APCS Date: Mon, 4 Jan 2021 13:41:21 +0530 Message-Id: <20210104081125.147300-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> References: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree YAML binding for SDX55 APCS GCC block. The APCS block acts as the mailbox controller and also provides a clock output and takes 3 clock sources (pll, aux, ref) as input. Signed-off-by: Manivannan Sadhasivam --- .../mailbox/qcom,apcs-kpss-global.yaml | 59 ++++++++++++++++--- 1 file changed, 50 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index ffd09b664ff5..3c75ea0b6040 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -27,26 +27,24 @@ properties: - qcom,sdm660-apcs-hmss-global - qcom,sdm845-apss-shared - qcom,sm8150-apss-shared + - qcom,sdx55-apcs-gcc reg: maxItems: 1 - clocks: - description: phandles to the parent clocks of the clock driver - items: - - description: primary pll parent of the clock driver - - description: auxiliary parent - '#mbox-cells': const: 1 '#clock-cells': const: 0 + clocks: + minItems: 2 + maxItems: 3 + clock-names: - items: - - const: pll - - const: aux + minItems: 2 + maxItems: 3 required: - compatible @@ -55,6 +53,49 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + - qcom,msm8916-apcs-kpss-global + - qcom,msm8994-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcs404-apcs-apps-global + - qcom,sc7180-apss-shared + - qcom,sdm660-apcs-hmss-global + - qcom,sdm845-apss-shared + - qcom,sm8150-apss-shared + then: + properties: + clocks: + items: + - description: Primary PLL parent of the clock driver + - description: Auxiliary parent + clock-names: + items: + - const: pll + - const: aux + - if: + properties: + compatible: + enum: + - qcom,sdx55-apcs-gcc + then: + properties: + clocks: + items: + - description: Primary PLL parent of the clock driver + - description: Auxiliary parent + - description: Reference clock + clock-names: + items: + - const: pll + - const: aux + - const: ref examples: # Example apcs with msm8996 From patchwork Mon Jan 4 08:11:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 356341 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14781700jai; Mon, 4 Jan 2021 00:13:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJyA0OonM+mSdFMPxOTY0Bimf9nlBjYGmFfJWDLBcSoFxyMeYM/g6YPxizS1+CwK7aslNTiz X-Received: by 2002:aa7:c358:: with SMTP id j24mr70330629edr.265.1609748024033; Mon, 04 Jan 2021 00:13:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609748024; cv=none; d=google.com; s=arc-20160816; b=i9NTZQb7irqxZkc0yZR7KMRVkPq3DcXL6SLKVYwoiI3ZjBnoH6AyZE3MVVNm5psDvc fP7nmpEy2juFbC7YSIxc53Hi84Lhdo8JaFpBs1pOQDVFoShhSDeuBxy54fRODl7fINaD MVrAebsFq5Sf38LRwMG7K0XNu9UE/WZM31rPE08fLfLmVTyXse38YSZ4u444kG66I/9g XpXOkX5aP9S/1icwnm5ibvdtqzetQ5DglE1aIxiCRXnwxSD/YZVsLQq4C2XB1fV0wqIm T+Q+XRjgFGgwEsX9j+mx8wMfueJuCNjLNPtf77oB5yP7GU2iLgBjuJa60zGjakjJFqaH pLKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6K/LbU0XVZ+HxnpwCy+UchOVctXMQ6ehwHVLCHIYOAk=; b=USkivrCIvpzMFlZ8tPZag4umCDeqszo4hBEkEh+g+DY0+Js6qA57gWcfBVjlcIq1Gc xqWtcQkTEZYtp+J3AR9hA8wtfnZx5dHXsagpAqbVCNDERD8oq5taSesS97wXEsRVsJqb kBCRuwmVe4cNEo9kEbuwiX35q1dsSy4xhGsSIahd52HlbEzgQowAF72h2VgnsZOYk/ci Fb2iCCWCEXxWSnpyD2AiWmfZO1wIiWI8k2jdrY8HLji/zBX/LJzge4RBa+WR/O+nFnhP rTjuppZuy079dJ7LYEoE9YbcJbwz2keUCl1g02+w7dWyXsM5U4EidVO7bAkDKfbAZsDY dEIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AJVyxZqP; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g10si29383294edt.499.2021.01.04.00.13.43; Mon, 04 Jan 2021 00:13:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AJVyxZqP; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726176AbhADINB (ORCPT + 15 others); Mon, 4 Jan 2021 03:13:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726178AbhADINA (ORCPT ); Mon, 4 Jan 2021 03:13:00 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 300B0C0617A2 for ; Mon, 4 Jan 2021 00:11:48 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id t6so14155705plq.1 for ; Mon, 04 Jan 2021 00:11:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6K/LbU0XVZ+HxnpwCy+UchOVctXMQ6ehwHVLCHIYOAk=; b=AJVyxZqPY8oCUIhavLRxLVaeY/nKST4WwvW9m0zupZ8MN/jpsbqN7h9xR3nLQPzpgQ 0LqiqdHsG4QGyDgoSlR9UDHybEgUSqAHSiLDCDamcg9m9ftmt0JacydO3qoF9fqZSgCv +S9yXQIJO+I37jM3O8f9dBWxMcNKhT7UR4u7nNRkbqqP9JgSbgt+MQyohLGBzXgGqJv9 wexF8LPSezG975+OhcEB2t/rNAuNv1HFJp5uYI7tMCAyG891Rn3RzZXuiROrzI1pRd2j vciTnTYcm9phQVnQekJn+Ub0YZv3cJ1ldD2i7d2x7rQ65JaKjMzYOC+Sf/6FKHIPXnzT CDKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6K/LbU0XVZ+HxnpwCy+UchOVctXMQ6ehwHVLCHIYOAk=; b=IUugKrQ0rnQEnSyQTCIC1j1kUqENXHubYz5lx/9w1LIjbCAETIilwOk7jhEifGcfTg CdXbAfP2e8yTzbFn9V6PRbWWhy/sqeeVfXQrKTEUg0DJ38Zq89DRxobvFg/kLURuOCas GJyRUnkdoQ5zGLKeU5hH4bkICcKLLB20eUAE/vtMdOvlSzPFbtti6qxxvtzm4W2Ms9zA ccuq/VFhbeD/A8SKxehIMf4BOZGD6H+KFJVkKs+jUIgthnwbraGgHxFwmPfGQGLyBWsV ASaUSVySqG4ziarKOXp/EC1zl2YVCJkU5x7/0vL7BXTtHHenCeLACwYeA8PipI+hkDxt LZMA== X-Gm-Message-State: AOAM5310f1rIvMfH38ovzo43AtKr+br6XmUg1UxMDL3LLIRZ+6Bnm0UM OQO/tDVLBnjbSJya2YqlG9h4 X-Received: by 2002:a17:90b:1218:: with SMTP id gl24mr27686229pjb.130.1609747907702; Mon, 04 Jan 2021 00:11:47 -0800 (PST) Received: from localhost.localdomain ([103.77.37.160]) by smtp.gmail.com with ESMTPSA id n7sm55051339pfn.141.2021.01.04.00.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 00:11:47 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/5] mailbox: qcom: Add support for SDX55 APCS IPC Date: Mon, 4 Jan 2021 13:41:22 +0530 Message-Id: <20210104081125.147300-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> References: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.25.1 diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 077e5c6a9ef7..b00556450335 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -61,6 +61,10 @@ static const struct qcom_apcs_ipc_data apps_shared_apcs_data = { .offset = 12, .clk_name = NULL }; +static const struct qcom_apcs_ipc_data sdx55_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -162,6 +166,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data }, { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, + { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); From patchwork Mon Jan 4 08:11:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 356342 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14781728jai; Mon, 4 Jan 2021 00:13:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJy9tT7N7lq8wmUXvYOmnLeiG1Ic54bQQfAtGPZ4BhNapsygnFsUBYKhRQmWaE6ZnJj5vEUg X-Received: by 2002:aa7:d511:: with SMTP id y17mr69967019edq.249.1609748027024; Mon, 04 Jan 2021 00:13:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609748027; cv=none; d=google.com; s=arc-20160816; b=vKlNv0aqSvSoNX7cpxyI79+iwtqhwkAUCBJiQ5VMgZ6Rpxro6D7Dp479g3DJppIm1v mH9nOU4KFBq9heLTYzv676n9MzfkTKl4fV62oE4z3HXOU/YkRhe/xIgRFx8g4dALKX6O AeKHQtpwnVpXXHj98IfusVeMMLtBpgiKpcHejUadTQ9KIWT3nQbx7cdhaLCynlCFYVqN x6codCphmxW0grhML4FzDsi/A9GtxjNCfY+jDqqjRDDVltd5WgUZs+mQSrWRCWSn/bEn cktusg4CHZyXitNhu35BpGCUaQqXKHt/g8jhkyfKfhkUlK0BMy6yb5E2fxv10KEZo7xK z8cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9oCBXEeItNyLdmXrVsfC7b3QROxgUzyHxaMFoVN3rtU=; b=VArnddRZY+6EzFnjndJnxgCUgIlixuR0bzCjzE/t1U4Lz6U7+jNTAE5JUz3EiAg3j6 6ogMn3xAz9CDxsL7hA5huXNjtn9zrNDeULzvSpAjlNcXkC3xaAfQTD0hJZ590GKT4r7V qpWCiZa4sUMF9/hBomnEKPKEx40/ZiwJuqbZTP/0ufknbZ0gFKQdoYe23keAzLdI+uBu fQwY88/JsSr/Y3iOTp4tOA0SIeTjGsyQ3kjZU5BlVOf3D8A99VWkowvwP5rzefGa36// qvrx1mpoL0CHx3okswSPhQIA7w40pcPGJkZ/PJkU1k46VUBaqvpXwbgqEVotkht4IbD7 ZM4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hDEUNdAP; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a7-pll.c | 100 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 drivers/clk/qcom/a7-pll.c -- 2.25.1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d32bb12cd8d0..d6f4aee4427a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -28,6 +28,14 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_A7PLL + tristate "SDX55 A7 PLL" + help + Support for the A7 PLL on SDX55 devices. It provides the CPU with + frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on SDX55 + devices. + config QCOM_CLK_APCS_MSM8916 tristate "MSM8916 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9e5e0e3cb7b4..e7e0ac382176 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c new file mode 100644 index 000000000000..e171d3caf2cf --- /dev/null +++ b/drivers/clk/qcom/a7-pll.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm A7 PLL driver + * + * Copyright (c) 2020, Linaro Limited + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include + +#include "clk-alpha-pll.h" + +#define LUCID_PLL_OFF_L_VAL 0x04 + +static const struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll a7pll = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "a7pll", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct alpha_pll_config a7pll_config = { + .l = 0x39, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x2261, + .config_ctl_hi1_val = 0x029A699C, + .user_ctl_val = 0x1, + .user_ctl_hi_val = 0x805, +}; + +static const struct regmap_config a7pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + +static int qcom_a7pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + void __iomem *base; + u32 l_val; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Configure PLL only if the l_val is zero */ + regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val); + if (!l_val) + clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config); + + ret = devm_clk_register_regmap(dev, &a7pll.clkr); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &a7pll.clkr.hw); +} + +static const struct of_device_id qcom_a7pll_match_table[] = { + { .compatible = "qcom,sdx55-a7pll" }, + { } +}; + +static struct platform_driver qcom_a7pll_driver = { + .probe = qcom_a7pll_probe, + .driver = { + .name = "qcom-a7pll", + .of_match_table = qcom_a7pll_match_table, + }, +}; +module_platform_driver(qcom_a7pll_driver); + +MODULE_DESCRIPTION("Qualcomm A7 PLL Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Jan 4 08:11:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 356343 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14781731jai; 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[23.128.96.18]) by mx.google.com with ESMTP id g10si29383294edt.499.2021.01.04.00.13.47; Mon, 04 Jan 2021 00:13:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FivOHfrb; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726289AbhADINQ (ORCPT + 15 others); Mon, 4 Jan 2021 03:13:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726303AbhADINP (ORCPT ); Mon, 4 Jan 2021 03:13:15 -0500 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6222C0617BA for ; Mon, 4 Jan 2021 00:12:04 -0800 (PST) Received: by mail-pg1-x52a.google.com with SMTP id n25so18623802pgb.0 for ; Mon, 04 Jan 2021 00:12:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uOArHEk74zxp/6R3wPGuqn1ZRRiW7s9F52OXIpe5TrE=; b=FivOHfrboOpdeFtFAuYKXJVPL2wZyskFjtEDu8GWnsIjVE6dSwfH03r+nk+7Xtoa6F 6ZwclVjWES1UGDfajr7p08X6qcizFw+Ib0P8DHA3Taou3RMa58vj3+UPBpusFZJ+Lw5n 7zINpXJR/eyDjNjt9lC59pndDtNM5eAXNbmwh9qsGV/80jgmFH83kYY8QW4LSUstrLuR nadTGVt2/D/pT0lrkGrAOGLWBSWCQ1kjAseIGkZhLpFudivTwyyFNgTXXa6fmHQDtUSa JdRNnUTkCwe97d07XW/NvJZzo97/F5YKnAJuwpfpUyrRIpS9ExiMRldfwIyTRrpuZSqw CsxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOArHEk74zxp/6R3wPGuqn1ZRRiW7s9F52OXIpe5TrE=; b=kC3mFjzhKBB51zyLn8OoOB4AI4IdQKHjpIgC+CsdTG58ywtcL+wQVjU+l9jGlKnCHE RSPPlnXFoJZJac817dvq6I6iEEicqIzAqb1lS59RQYC3iHIXFg9Xs4UvSfXxlY/N1vGo DywFHs46hbzsf63oeOJNXWy1ralaMwA91/IatJsefu4vTV4LDtyB1woAgz4Rx+TN9T/R G1LYnVxvikqOJ4ElHA2CmFI0gJiU+mkbl+7daqPAE5DRU3ORbStzAE7i2P9b3BfbE7yk C58YkoUxQ7PF+F5P2w0SJbttf34rushbHojYtZopUEqxlBFWKG18xQ9wmwnndA7Mi0hY qdCQ== X-Gm-Message-State: AOAM530xwaXlj79PSpEUfQgA/2cSc5zQuyaSpwDKtia5575BEEto4AeN oj7Ls0zyquEXgbzYEEvZdifF X-Received: by 2002:a63:5924:: with SMTP id n36mr58899261pgb.9.1609747924240; Mon, 04 Jan 2021 00:12:04 -0800 (PST) Received: from localhost.localdomain ([103.77.37.160]) by smtp.gmail.com with ESMTPSA id n7sm55051339pfn.141.2021.01.04.00.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 00:12:03 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/5] clk: qcom: Add SDX55 APCS clock controller support Date: Mon, 4 Jan 2021 13:41:25 +0530 Message-Id: <20210104081125.147300-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> References: <20210104081125.147300-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver for the SDX55 APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-sdx55.c | 149 ++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clk/qcom/apcs-sdx55.c -- 2.25.1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d6f4aee4427a..2c67fdfae913 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -45,6 +45,15 @@ config QCOM_CLK_APCS_MSM8916 Say Y if you want to support CPU frequency scaling on devices such as msm8916. +config QCOM_CLK_APCS_SDX55 + tristate "SDX55 APCS Clock Controller" + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for the APCS Clock Controller on SDX55 platform. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as SDX55. + config QCOM_CLK_APCC_MSM8996 tristate "MSM8996 CPU Clock Controller" select QCOM_KRYO_L2_ACCESSORS diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e7e0ac382176..a9271f40916c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o +obj-$(CONFIG_QCOM_CLK_APCS_SDX55) += apcs-sdx55.o obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o diff --git a/drivers/clk/qcom/apcs-sdx55.c b/drivers/clk/qcom/apcs-sdx55.c new file mode 100644 index 000000000000..14413c957d83 --- /dev/null +++ b/drivers/clk/qcom/apcs-sdx55.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm SDX55 APCS clock controller driver + * + * Copyright (c) 2020, Linaro Limited + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" +#include "common.h" + +static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 }; + +static const struct clk_parent_data pdata[] = { + { .fw_name = "ref", .name = "bi_tcxo", }, + { .fw_name = "aux", .name = "gpll0", }, + { .fw_name = "pll", .name = "a7pll", }, +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A7 PLL is reconfigured. + */ +static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = mux_div_set_src_div(md, 1, 2); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + struct device *cpu_dev; + struct clk_regmap_mux_div *a7cc; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret = -ENODEV; + + regmap = dev_get_regmap(parent, NULL); + if (!regmap) { + dev_err(dev, "Failed to get parent regmap: %d\n", ret); + return ret; + } + + a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL); + if (!a7cc) + return -ENOMEM; + + init.name = "a7mux"; + init.parent_data = pdata; + init.num_parents = ARRAY_SIZE(pdata); + init.ops = &clk_regmap_mux_div_ops; + + a7cc->clkr.hw.init = &init; + a7cc->clkr.regmap = regmap; + a7cc->reg_offset = 0x8; + a7cc->hid_width = 5; + a7cc->hid_shift = 0; + a7cc->src_width = 3; + a7cc->src_shift = 8; + a7cc->parent_map = apcs_mux_clk_parent_map; + + a7cc->pclk = devm_clk_get(parent, "pll"); + if (IS_ERR(a7cc->pclk)) { + ret = PTR_ERR(a7cc->pclk); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get PLL clk: %d\n", ret); + return ret; + } + + a7cc->clk_nb.notifier_call = a7cc_notifier_cb; + ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb); + if (ret) { + dev_err(dev, "Failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a7cc->clkr); + if (ret) { + dev_err(dev, "Failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &a7cc->clkr.hw); + if (ret) { + dev_err(dev, "Failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a7cc); + + /* + * Attach the power domain to cpudev. There seems to be no better place + * to do this, so do it here. + */ + cpu_dev = get_cpu_device(0); + dev_pm_domain_attach(cpu_dev, true); + + return 0; + +err: + clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb); + return ret; +} + +static int qcom_apcs_sdx55_clk_remove(struct platform_device *pdev) +{ + struct device *cpu_dev = get_cpu_device(0); + struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev); + + clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb); + dev_pm_domain_detach(cpu_dev, true); + + return 0; +} + +static struct platform_driver qcom_apcs_sdx55_clk_driver = { + .probe = qcom_apcs_sdx55_clk_probe, + .remove = qcom_apcs_sdx55_clk_remove, + .driver = { + .name = "qcom-sdx55-acps-clk", + }, +}; +module_platform_driver(qcom_apcs_sdx55_clk_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm SDX55 APCS clock driver");