From patchwork Mon Jan 4 13:49:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356381 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978547jai; Mon, 4 Jan 2021 05:42:52 -0800 (PST) X-Google-Smtp-Source: ABdhPJxX+rI/oKJJtqr64lGvOEZRebfpxP7VyuikZqVQQBkSjIpjYwndgknQLDetZAVAtk0UVZl5 X-Received: by 2002:a17:906:f153:: with SMTP id gw19mr68157090ejb.272.1609767772129; Mon, 04 Jan 2021 05:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767772; cv=none; d=google.com; s=arc-20160816; b=ijeT3a3SobX+oSSv1dxaC2dXw79/A8ofU+X5E68X56k6bwrCvqKHwllz/Hd4yLhJzT JHj6ZoeQsCwCIaKZXe2u+H/Il8gyiOeS8q8Q8qI0Cql8YnfmKvUeyDUVY9ijGmIMkt5s lbxHfzrd5O2nPYJ5x515HvwUhCd5Szml2KV5xvkBAzGgX9hf0eWhrSa5hvkG3lD4VxcF cr9rW3Mnfmm36go4U4hew8gAYMKU/sZhD2c5idSIiJjNV9vQV40ZL1hrDsynHB3bHYDu RerdColBHBCTX2yJ+IPda2XazhYb3O9m0QiL+Q3jYNopYc2Fw5Zlnw639lQE0QJK3zy1 8f3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=PwDxa1yR487r7EqfSYHvHT2UzfEdaV/GhFU5BAFnhMcUS0iy7EaYwSGbwjmn4GTRoV q5QX8JRMxRQt+wEBwcdtgigIcp2QkeOyJRSsP0hTWMkyambimn5zayL4pEqhpss3Dgue 6sf4vgH8k3rDZUNxpsQeRNU4qHmjyGnBks4OP/2/aQQd3mtF9NmkVrgiZPHo8Me5e8+V VWtiUtne+CKF4/uqFQsQgWrEF2eRO5lEXohzWYW7h+KizBy1zvx78S6TTsg+A+CGQr+5 D3iCY2MLM2P4jA0u0quDKCUZinQDudDzxdO1r52mJJQKM8d2IkFziaZ6Ihqm9P9afKlz 2E8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/0aQMuT"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.42.51; Mon, 04 Jan 2021 05:42:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/0aQMuT"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726640AbhADNmv (ORCPT + 15 others); Mon, 4 Jan 2021 08:42:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbhADNmv (ORCPT ); Mon, 4 Jan 2021 08:42:51 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6A85C061794 for ; Mon, 4 Jan 2021 05:42:10 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id k10so18503705wmi.3 for ; Mon, 04 Jan 2021 05:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=l/0aQMuTQBAkPOZSm08RmdSm1kqoPxvPBl8+byeCXJuumKsmV7g/OKSTYLCtnQUxDO 17JxJiiI8zweDO/K+6s9g83X/5T3A/CaoqIjmFJd/AY3eerFXN2aHu60wcKMHgFxwRIu zHouXN+yMPWIHfWMELCP/J8Ec4OL8QowQMY/mCBGWOJXZNecyJLWMZa2/BPCXAs4Mpud qPYphRh/LEBs+PIEn0OV6Uis7aIVMRE/Y8swRHVYKi/2Tw6aBIEH3Uzi4Glz1F6D3V0G O6Opz+5jDwpWbZbPqYcUZFHOeynzYJGLSQydnl4YMsQVk8N737R72TFy4q55BHMlBDPk d/eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=07rDU/OuVJvk6JF93jkdN2tmY83mHUDzBU2a1fn2P0w=; b=awWkFCPSQtTyIFZaEwo2+hFsh4TWaLb3ibZUaQrT2XcMiq7BPnMH0ELzoll5Osehaa dqs7nMaCEyNaZsOud9FrBKey1rLAuZZZ7HJlZ6Dy10+qGWdEnmltnThqojUKauB4uVAx sbQCgO82TibqHkvzCoDMFb7zcuOlRNL18U5sYkfy5p74Ogb/BmJtEuij/GZCEUe7Hg4e HVicjHdvPIbgXolAyAm2ndpNNVSgXCTLgIZrjk8zv/tYEQEVV5+C2xnRj3AuSb5tdKpd Os2eMjti8/A2wSor4zwNpUAygWMWOWm/+73oBYpBqNDTt3O8sURVzBpdBNcsn11uWilq a84w== X-Gm-Message-State: AOAM531+MTSoWR61XBq6LFecHa4d5CsSzIQ73AyZqnUiA713VCiomo36 eNx0GwOhKTwFa8QNkHPW8sRjGQ== X-Received: by 2002:a1c:9ac6:: with SMTP id c189mr27075961wme.137.1609767729368; Mon, 04 Jan 2021 05:42:09 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:08 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 01/10] bus: mhi: core: Add device hardware reset support Date: Mon, 4 Jan 2021 14:49:30 +0100 Message-Id: <1609768179-10132-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MHI specification allows to perform a hard reset of the device when writing to the SOC_RESET register. It can be used to completely restart the device (e.g. in case of unrecoverable MHI error). This is up to the MHI controller driver to determine when this hard reset should be used, and in case of MHI errors, should be used as a reset of last resort (after standard MHI stack reset). This function is a stateless function, the MHI layer do nothing except triggering the reset by writing into the right register(s), this is up to the caller to ensure right mhi_controller state (e.g. unregister the controller if necessary). Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/main.c | 13 +++++++++++++ include/linux/mhi.h | 9 +++++++++ 2 files changed, 22 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index a353d1e..c181a85 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -142,6 +142,19 @@ enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_get_mhi_state); +void mhi_soc_reset(struct mhi_controller *mhi_cntrl) +{ + if (mhi_cntrl->reset) { + mhi_cntrl->reset(mhi_cntrl); + return; + } + + /* Generic MHI SoC reset */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, + MHI_SOC_RESET_REQ); +} +EXPORT_SYMBOL_GPL(mhi_soc_reset); + int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info) { diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 04cf7f3..7ddbcd7 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -355,6 +355,7 @@ struct mhi_controller_config { * @unmap_single: CB function to destroy TRE buffer * @read_reg: Read a MHI register via the physical link (required) * @write_reg: Write a MHI register via the physical link (required) + * @reset: Controller specific reset function (optional) * @buffer_len: Bounce buffer length * @index: Index of the MHI controller instance * @bounce_buf: Use of bounce buffer @@ -445,6 +446,7 @@ struct mhi_controller { u32 *out); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val); + void (*reset)(struct mhi_controller *mhi_cntrl); size_t buffer_len; int index; @@ -681,6 +683,13 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); /** + * mhi_soc_reset - Trigger a device reset. This can be used as a last resort + * to reset and recover a device. + * @mhi_cntrl: MHI controller + */ +void mhi_soc_reset(struct mhi_controller *mhi_cntrl); + +/** * mhi_device_get - Disable device low power mode * @mhi_dev: Device associated with the channel */ From patchwork Mon Jan 4 13:49:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356382 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978559jai; Mon, 4 Jan 2021 05:42:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJxrOBaN6rnU1RZ6RrA2SjmgV1cm6mtCHgLVDbG/23UkF8GMhedefJg68Xi3dFJmUeagPHsP X-Received: by 2002:a05:6402:8d9:: with SMTP id d25mr18978569edz.278.1609767773445; Mon, 04 Jan 2021 05:42:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767773; cv=none; d=google.com; s=arc-20160816; b=dTdPRMHIpYQ8uyeoU9Hb4pX8JHD0OEVL0Pf8eNqdT+ZODCZhcClvSOfUx2oHkdrqkR AV7XHa1v60mjC8x1xIlThrCEwF0pHl+/RNRYZPGd38vKKDdM9bxdAop882P30s5lF1Jl cJPlnQcH0n4SgH2Khxc61UpporyIjls8Odfu1NZYV5YeVjQcDEqzcMnXnQXRBZLnpJji U9KPAeHd9vCXdmenmvQati1Y3OV5w2fc4wpscr4meFed0Yr5hkOwLGM7nzfpMUZEEMeI +NSwE36iCoIpq+UTrfeEp+CeO862O/7dQGMjjgeMDi5ZkpH0aJDVBpl6Nhc3xyb8vye8 1CYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=u23Upri+mVTKw2vMmpl89dQD9K1UaxJ4Tc+YMYk9PIg=; b=gXEzakvbC7xnr/EOO7FixbOIQUYVSDzArChWCauOlfV8HyLi91oYcRf5D3oBgwhHSB nmQtSSv9HSvssyet+TDmN1Cwc//9p+09TQu3//AP8w5uzw+CQh36uI2qR6sez8b0Y6Od Dp3+qCKB8apwfjqG3CTO6xMNaWNuPL12TJWzP+IG1xX2/r1iY9JQ53ryKdUY+aM8gtBX q/B5gfO4sDCAOeqDFRvNTDsP08Isr4MZnwLBwuU6nlmndGR6tnT3TYikC9K1ML0mf4Mf 0BbrBMToP51sv9GyGRcpJGdmMNWzP93AAkrzP5PhjBFEdaJ2Wd/Nqhwab1qSvFK8tyZb 7gCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="KdU/z2W/"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.42.52; Mon, 04 Jan 2021 05:42:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="KdU/z2W/"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726662AbhADNmw (ORCPT + 15 others); Mon, 4 Jan 2021 08:42:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbhADNmw (ORCPT ); Mon, 4 Jan 2021 08:42:52 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84992C061795 for ; Mon, 4 Jan 2021 05:42:11 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id i9so32215684wrc.4 for ; Mon, 04 Jan 2021 05:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u23Upri+mVTKw2vMmpl89dQD9K1UaxJ4Tc+YMYk9PIg=; b=KdU/z2W/BC4a5O6/Op7jOih0OZdWuuJUciuhR0WccvXslPnct5zHgkojzX+DB/08+9 8OF5Bn4TAma4uAjk6ljvi6OSnlsV8xayQ+fT0SHYjamZWnIUWVVm6nsPKEZRYZ3b9O1l 8JANatH70Zw18LikmuH9GPIX2cuPELzzQ/DrM7eLm/4bZt0nildSQdRZdRuPUYoA/8UC 6Fa9HcE9aCsQM2BkRUjXXD45VVtDQ0f555MT+5eTdd1aITZO3xzBrjmT39u5MZs98UI+ BZF7oEfuvd028wahT6J/aOD2/HfxUFUmE+jfijYbmWe7g7lL7VFuwata/0+dhCkwj74L twwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u23Upri+mVTKw2vMmpl89dQD9K1UaxJ4Tc+YMYk9PIg=; b=IFMjdqYdJp9lHnGE3ngf7gJ6g8XxK9W3YGvzwPMdgCN5VSOCK8qk+E6SAgzonlR+sz 5TTPSYd9epslfYT6gkKtyihBC/vI9UsIcOaXULZW5Q/Dx9n8b3W59ltzkN5q0LwCueuk FQX2tKBr2C9iCZY+Z0pn5mAUcmuIkc0Js4XSQ08LwYHXBrcUUZrb7EYoUf59ubCXPd3q XbPIoH3GkTyW0a71WaToryidRAxzkZQXmIOM3NePy0v+uTh5o8oJVRhfnCdqYAwrqKMT Ek7gDSt6KC+QiIFSrwvt+JP174SOoqic2EjMt3m28PKI2YvJjeIZ9+kdlngJqfclfUFQ gb7w== X-Gm-Message-State: AOAM53180qGjKBLGXZBiWRWuYArt9ArPqpV1ezh+i3UPamQChWVtktiI mEDsT/sjwKgjnqA5W8cDwxEuOQ== X-Received: by 2002:a5d:4b4c:: with SMTP id w12mr79135226wrs.402.1609767730299; Mon, 04 Jan 2021 05:42:10 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:09 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 02/10] mhi: pci-generic: Increase number of hardware events Date: Mon, 4 Jan 2021 14:49:31 +0100 Message-Id: <1609768179-10132-3-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the IPA (IP hardware accelerator) is starved of event ring elements, the modem is crashing (SDX55). That can be prevented by setting a larger number of events (i.e 2 x number of channel ring elements). Tested with FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index e3df838..13a7e4f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -91,7 +91,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ - .num_elements = 128, \ + .num_elements = 256, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ From patchwork Mon Jan 4 13:49:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356383 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978568jai; Mon, 4 Jan 2021 05:42:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJzXFDwoxs9P1cZAxD1TKBE6x7fOqkQdiXZHaGZjaKEzOw6QKCBTG+wnvjuaS63GunJz02ek X-Received: by 2002:a17:906:ae14:: with SMTP id le20mr68523528ejb.451.1609767773880; Mon, 04 Jan 2021 05:42:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767773; cv=none; d=google.com; s=arc-20160816; b=zRwEqoYJFHNm3Y4sQBYeN/rvnAU8CihBhYhDCtqifsZDQmZqfmlII1VLFXUimmLRUa 2GQxZj3brU3sCVaUJ6SFi826RIDrJJ0K3Nt1LMGDfjeJL/WmBP9ZB7WNyi6TV5QD3Q5M LZkEvf0YonmG5JWOsEoiLgMN44sOYlwy7mm2EE2xjOyf8XfZ5Y4S0WP7cwvqtZ8MzRKr z7b6Burvb/9yR5C/GVuBlSYFWTVzKVT4rWHplE6VYgQD4N7kjwpakyAlzNfQVWUPaV/V l13bDGi48PdQm03m+5x2W/Sq7UOkpse6RkDo64+KW26PuPUn6fS/XMRGokZzOCjFX/vA bP5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=MkeCdMAJPZmLxc6YEqvhWKBD6uPygtoaXQQ7bd/Z3b9d72x4R/oeJQjyP1I4LaReFN DbyfZFPLuLLS0JJ/BfYFOuzzzRS3mwMSq5j4Bvl0LC9r6/72e9LDbXxZvUA8NBuIWPUz K/ZCWvPUU8jlrhn7sOA2+rLxTPKErQxssrG1Fi+CCvH8iry2POwrLxRsportbnMc5g7J yy4P+e6paNsG6h1Tl7xlXQFsSaC/MqNHVTW3rz3yQxQ237u0juCy3g4Mplbdsc4vWjre KYVIFhgTS0519xs0+UHtzq7YrS1ByWIFI3pQ2rCILzFKWczShUksp4qZGPu1Gz7JSp7R MUCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ij9S+uxC; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.42.53; Mon, 04 Jan 2021 05:42:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ij9S+uxC; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbhADNmx (ORCPT + 15 others); Mon, 4 Jan 2021 08:42:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbhADNmw (ORCPT ); Mon, 4 Jan 2021 08:42:52 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65DEFC061796 for ; Mon, 4 Jan 2021 05:42:12 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id q75so19358200wme.2 for ; Mon, 04 Jan 2021 05:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=Ij9S+uxCQOB8AB3yESR3oc43wm/FoqRTkJXriq4dF1yk/BLFqfvlm1jHCaQnNyz1Aj od5JJMa9vFwX0+ZpgDDv/f0iJN20OjYMo3GmdsVdJJEPHiTYzOQeasUmvfxNZ+rVnbG/ TZ/e/X9/7qh6Up6nBWfKRR1lT3pv/v5Z/8PMNSrvdLEC8ZSTlzBDgaAoHy1t2MX+k92T 1jj0EXvagGel6P/PMAkLnH78nVq8HGYxFrF7DsVFqNEb/4NfCB9IsQ+6fgTSJkHF8pe5 h7TYRu69Ko0Nrw+QXoGysqnF3zJHFISAgEuqxKhCwTFAHvr7jYfyfUOZJifIWKAf9Q3Q oeTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b6KTirZejd3sDDi2THGHxOo7aZHrY3+M9Y8zIKfmv2E=; b=AStMVZVNL8ZO1uK8CcQwuC0ll9akSvE9k5V8JF5rWZdPHO2kwrZb/ODrqnA40wMG8z YyCql9kgiWSVvC687yx2rY7dGRhTeIPRTdR0ZyGEKnuSCQNDxFRlOmFC8myzy/BRQJPf lekoxSgRfvMrxYVily2NCGqsU/nU9uoDqlj9nyBz55+lNy09UmExYlfUTEapNrDcH9oH q9WZYkeAFiM6fGbVYP1qZsbdKHNQRFGy9K6u+8iWJq119jJlwbbyi2Mrj4WSn4+sxDhu DQvDMeFaGTFcUSegIdIbENdjSgTz9Jt3PMex6UlcZJwxTk1bTguR3Z0LsIBLqNJOWfll Qpxw== X-Gm-Message-State: AOAM531/4H7cxFGfPK8cZAtl/4u0laAKTvbs7fIX9Iw+TflK+qPBc17d GQcHCUztMoYaIFB5hNesSWL+wIFNyNTYQy/Q X-Received: by 2002:a1c:1dd4:: with SMTP id d203mr27331101wmd.118.1609767731127; Mon, 04 Jan 2021 05:42:11 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:10 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 03/10] mhi: pci_generic: Enable burst mode for hardware channels Date: Mon, 4 Jan 2021 14:49:32 +0100 Message-Id: <1609768179-10132-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 13a7e4f..077595c 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -76,6 +76,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -110,8 +140,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { From patchwork Mon Jan 4 13:49:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356384 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978977jai; Mon, 4 Jan 2021 05:43:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJxBEwfkTukXU79Y2smQp95rsdYP3Q7BkQy06e7WTYxdUCoQ+9/LeQUk8snDRu302eMsWgUw X-Received: by 2002:a05:6402:307c:: with SMTP id bs28mr71586452edb.186.1609767810676; Mon, 04 Jan 2021 05:43:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767810; cv=none; d=google.com; s=arc-20160816; b=qsvOXf7KEx0ilC1zUr6OBzz7f4tPLXQx9B74fTyjcQ7JSw1C/M7R7QTuWczpiRs97/ thYmAAn4h22MT2Dj4DuijR8tzpZa2HAvwsB7S+y7r4VVgps54rus26tkQMzKGmQ+TUdc 906j59j9QahEkQwhrunUA/UqodoR/t2CGoWy8KL1LhKVaTkQ72ORApej2b+NCEREt+bz R5moAasONpmssUEyts7y5jbZhzfW4WJalHPdpJm0M1rOZLe7/y6ut7mctjdREebbFHLH HYJUINNqQfHE7Mg5JPqS1lcQ02xw0nDiaXjjC/msg512BwNvIsu9sFp2B2pHjA9j+shj yFXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Y1bhk4d70RfYK4KKcQ1GGp2yJkWrRsB8ydpZfDNXHKI=; b=OAQPXpRuWWU6dPCKSpTPhHyptojHNUNCN9fBIKUvVb1jVbDugNBx5taKYnAy+FsDrJ sI+fHvCiftD+Zs7hAaFe7hDYiO6yjP2biL/5x8kSL1eP/sRpfuGNagnms9wYz0vEiZgY wEGvUBSX69sPvYmcaxONy8WqKp4Tcom7hm7ALHXQkOY3aVZd2MGHUUm6dTbJix0sQI/M 0FfbgdAGKpk4iuXpyks/aG8TjdrhFtuaWjhkaq2ZVjQNMoMCV6PInx2z5MDGwnYx0R13 2wdp0vKQeMC0HTvFKW9jeM8Erzv6OakuWpRhKnX47HpYsQ//3u1edvcf7WXsQ6byjBym RrEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ucu6PEIe; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.43.30; Mon, 04 Jan 2021 05:43:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ucu6PEIe; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726612AbhADNn3 (ORCPT + 15 others); Mon, 4 Jan 2021 08:43:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726579AbhADNn3 (ORCPT ); Mon, 4 Jan 2021 08:43:29 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5665CC061798 for ; Mon, 4 Jan 2021 05:42:13 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id c5so32197182wrp.6 for ; Mon, 04 Jan 2021 05:42:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y1bhk4d70RfYK4KKcQ1GGp2yJkWrRsB8ydpZfDNXHKI=; b=ucu6PEIe7FFcdMoabuH/mrCv1QWDVy8L7bfkCC36VbWO6wI+/S8UZQc/4xBm9diXfc h7SPqPl9Np5xjMxnqvlDnUHjrauuSnPdnL5/8rzCrwnAo5eSHmb6x8wkcBKlx7gUfd6X dCm7scWP/CFnRy0C5C9kHqVaPAvaMXAfr++yjYEzXNV+9ziJIHFC8rE8ZkwurPztadt5 vIA7nJ211ayEGfn4oyqRa5umsgNhWntby2sfr349ho9Y4eg2Uw3mHHwWxVw5ds0msCC/ xfi8RE18+HtdtfLuvE3X5xJ24//oesIF9z6vtUgTdvCovJlIXBik7m2w+ld+QZ2RKaEp 2R7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y1bhk4d70RfYK4KKcQ1GGp2yJkWrRsB8ydpZfDNXHKI=; b=ApnxwYbj05lCSOMEdyTLxdEPzNGP5rBXnK/52Y70hWLTZN3VCv28xlSP37t/DyHqAs 0VeS90ljZDUKP0PbtjGs1WLH50Z6UxoMHciX6RWaPbePaslrijtw8ttuYFnakiv7JAfd FvMecdk5fS7qXyGf1fKDfGvxFNCIlhGYHbWWz9KKSz0fcTAU5f64h989MlgQ+lrBiwiI Gv9SfXocRqALvY7g18lbvcSpunA9Svp/Br1BTYBBaLUidBPpP7q4NeOsXnK4vhovpg0e /7mnw+2GIFE4pa9IFGssdPnieecAfzUh6j3eFMJiMzdiMHcAB0LAyxudb2Ek9/X2s7KC dVog== X-Gm-Message-State: AOAM531N3s1HskQ6CS+G9oVKTzRaHso02sHJUTOsHVJd2pttSUK+wlrd xZIvyEdR880IF96ih3AOFQEttw== X-Received: by 2002:adf:d082:: with SMTP id y2mr81328295wrh.301.1609767732085; Mon, 04 Jan 2021 05:42:12 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.11 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:11 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 04/10] mhi: pci_generic: Add support for reset Date: Mon, 4 Jan 2021 14:49:33 +0100 Message-Id: <1609768179-10132-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for resetting the device, reset can be triggered in case of error or manually via sysfs (/sys/bus/pci/devices/*/reset). Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 121 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 108 insertions(+), 13 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 077595c..b2307e7 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -15,6 +16,7 @@ #define MHI_PCI_DEFAULT_BAR_NUM 0 +#define MHI_POST_RESET_DELAY_MS 500 /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -177,6 +179,16 @@ static const struct pci_device_id mhi_pci_id_table[] = { }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); +enum mhi_pci_device_status { + MHI_PCI_DEV_STARTED, +}; + +struct mhi_pci_device { + struct mhi_controller mhi_cntrl; + struct pci_saved_state *pci_state; + unsigned long status; +}; + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -196,6 +208,20 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, /* Nothing to do for now */ } +static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) +{ + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + u16 vendor = 0; + + if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) + return false; + + if (vendor == (u16) ~0 || vendor == 0) + return false; + + return true; +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -291,16 +317,20 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; const struct mhi_controller_config *mhi_cntrl_config; + struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; int err; dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); - mhi_cntrl = mhi_alloc_controller(); - if (!mhi_cntrl) + /* mhi_pdev.mhi_cntrl must be zero-initialized */ + mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); + if (!mhi_pdev) return -ENOMEM; mhi_cntrl_config = info->config; + mhi_cntrl = &mhi_pdev->mhi_cntrl; + mhi_cntrl->cntrl_dev = &pdev->dev; mhi_cntrl->iova_start = 0; mhi_cntrl->iova_stop = DMA_BIT_MASK(info->dma_data_width); @@ -315,17 +345,21 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) - goto err_release; + return err; err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; + + pci_set_drvdata(pdev, mhi_pdev); - pci_set_drvdata(pdev, mhi_cntrl); + /* Have stored pci confspace at hand for restore in sudden PCI error */ + pci_save_state(pdev); + mhi_pdev->pci_state = pci_store_saved_state(pdev); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -340,33 +374,94 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unprepare; } + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return 0; err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); -err_release: - mhi_free_controller(mhi_cntrl); return err; } static void mhi_pci_remove(struct pci_dev *pdev) { - struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev); + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, true); + mhi_unprepare_after_power_down(mhi_cntrl); + } - mhi_power_down(mhi_cntrl, true); - mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); - mhi_free_controller(mhi_cntrl); } +static void mhi_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_info(&pdev->dev, "reset\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* cause internal device reset */ + mhi_soc_reset(mhi_cntrl); + + /* Be sure device reset has been executed */ + msleep(MHI_POST_RESET_DELAY_MS); +} + +static void mhi_pci_reset_done(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + /* Restore initial known working PCI state */ + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + /* Is device status available ? */ + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(&pdev->dev, "reset failed\n"); + return; + } + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to prepare MHI controller\n"); + return; + } + + err = mhi_sync_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to power up MHI controller\n"); + mhi_unprepare_after_power_down(mhi_cntrl); + return; + } + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); +} + +static const struct pci_error_handlers mhi_pci_err_handler = { + .reset_prepare = mhi_pci_reset_prepare, + .reset_done = mhi_pci_reset_done, +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, - .remove = mhi_pci_remove + .remove = mhi_pci_remove, + .err_handler = &mhi_pci_err_handler, }; module_pci_driver(mhi_pci_driver); From patchwork Mon Jan 4 13:49:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356385 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14978991jai; Mon, 4 Jan 2021 05:43:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJyl2nR7/4ZRW5fmfhdastpHMSnJ58EiyiX27Cw98plPK3uQkTK2n1yRloDZg1ypX9Mca7fD X-Received: by 2002:a17:906:ae14:: with SMTP id le20mr68525209ejb.451.1609767811359; Mon, 04 Jan 2021 05:43:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767811; cv=none; d=google.com; s=arc-20160816; b=Q/BI0W0sm93RnpYjtWGe9prdz9dt/Pp+T6iHv/qMayi9He6S8DO0PztMGJgQ0addt/ nBDZ0NjtNG4Yl7jFd+4mPzKF3HUY1Vz5T2/u8h6Ir5Ya3bhYVzU/0+y9udZ3mvgfZJvH PdZ0beNQyWbqM8O+XrKpSC+NSHGGQ4W8kxOCQQqnjdBEibQQaTxHKIOw6GnmsNigueJa itia4i1c3yZ3hN80MnK471D8V+IZXDHwIqDX7LhHcyEw4wv4twGIbmtFX7XPV2zMR53+ qsKtjYIhjrKd5EbRQPP/aJqBcn0WMqUKQvS9R66W5zMqEvw000G1Hz9Ns3v/hrMiGrb5 c11Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=2kCHLSwMyeWN7et3oMjoEv/8izgQd9h8l2LVl20Grzk=; b=v8tI6fbS6O5UnA/BqGaaVHKiL2NEEAdy2RJYjjfryIMwFynBHYwW/CflCA1XZn38SB s4aKWgWkno9uE8zaaOepi6hOC0N5N4adnsRIjWapDDO9EXUZ9RAWijGhM9nDcw2omPAN GuFjmMiHdImlS8dIdovQ4S8s12SYKKwt/QIHC2v1eHuqm4GMp7VPE/oxqP3VmAs0mPa0 tclcXG53aPDgzyJbkGG7YViWxbuPrfJxrTIBRjTr9er9R/Rfr4KSJio5KK0CF9aZpFxQ jHLFnbtVxyGvEAY973NCLUVUFF8WdmAg2h22AVFpmsX7cIBsK7pTX7MaXrDvnEbqTiub SRXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hSZS6gaE; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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During suspend, MHI device controller must be put in M3 state and PCI bus in D3 state. Add a recovery procedure allowing to reinitialize the device in case of error during resume steps, which can happen if device loses power (and so its context) while system suspend. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 105 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index b2307e7..3d459f3 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MHI_PCI_DEFAULT_BAR_NUM 0 @@ -186,6 +187,7 @@ enum mhi_pci_device_status { struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; + struct work_struct recovery_work; unsigned long status; }; @@ -313,6 +315,50 @@ static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) /* no PM for now */ } +static void mhi_pci_recovery_work(struct work_struct *work) +{ + struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, + recovery_work); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + int err; + + dev_warn(&pdev->dev, "device recovery started\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* Check if we can recover without full reset */ + pci_set_power_state(pdev, PCI_D0); + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + if (!mhi_pci_is_alive(mhi_cntrl)) + goto err_try_reset; + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) + goto err_try_reset; + + err = mhi_sync_power_up(mhi_cntrl); + if (err) + goto err_unprepare; + + dev_dbg(&pdev->dev, "Recovery completed\n"); + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return; + +err_unprepare: + mhi_unprepare_after_power_down(mhi_cntrl); +err_try_reset: + if (pci_reset_function(pdev)) + dev_err(&pdev->dev, "Recovery failed\n"); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -328,6 +374,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!mhi_pdev) return -ENOMEM; + INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -391,6 +439,8 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + cancel_work_sync(&mhi_pdev->recovery_work); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); @@ -456,12 +506,67 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; +static int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + cancel_work_sync(&mhi_pdev->recovery_work); + + /* Transition to M3 state */ + mhi_pm_suspend(mhi_cntrl); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + pci_set_master(pdev); + + err = pci_enable_device(pdev); + if (err) + goto err_recovery; + + /* Exit M3, transition to M0 state */ + err = mhi_pm_resume(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to resume device: %d\n", err); + goto err_recovery; + } + + return 0; + +err_recovery: + /* The device may have loose power or crashed, try recovering it */ + queue_work(system_long_wq, &mhi_pdev->recovery_work); + + return err; +} + +static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, .remove = mhi_pci_remove, .err_handler = &mhi_pci_err_handler, + .driver.pm = &mhi_pci_pm_ops }; module_pci_driver(mhi_pci_driver); From patchwork Mon Jan 4 13:49:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356390 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14980265jai; Mon, 4 Jan 2021 05:45:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJxIj8HKwbj9rRYXBwnsEZ18oYEzXPY93EOUx5XC9pcda5RfxNfTUAtT+51J61gYL0acPgM3 X-Received: by 2002:a17:906:3953:: with SMTP id g19mr65848182eje.429.1609767909619; Mon, 04 Jan 2021 05:45:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767909; cv=none; d=google.com; s=arc-20160816; b=EDqvrUgt+9A414A3FZ/QtMXuQHtfoO8Lq6yi+ZwFtUdsnqiwMT1oePsZ9otAbcJg5H zfNOZg7EqtVrIadKbR1xIair9ASoM+rNmVHQ+3/ShNy+nphiItjwnhrKJV05Z5hepZzK lUj2kMyZZRhFV/UbNqPJkih5FtWYUtSNNAArUzBolHMcwBsSTxQ/u3ViJiuthEuw9Y7P bN70EC1z0tFfPrKT+a42Fvnzn8epJIiuIVg8/KQtt2QR8Sg9/k45CXkTzf7FmGyMgFLY K8ZyuP6PQAqiqBanDZ+noJ0a3OOvNo1YxXVK4Wc+Jjqsk1ai7AmRf7MGCkcYKi3kaWJD zBKQ== ARC-Message-Signature: i=1; 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This patch enables error reporting and implements error_detected, slot_reset and resume callbacks. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3d459f3..0c12027 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -405,6 +406,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_enable_pcie_error_reporting(pdev); + err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) return err; @@ -501,7 +504,54 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); + + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } else { + /* Nothing to do */ + return PCI_ERS_RESULT_RECOVERED; + } + + pci_disable_device(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) +{ + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_RECOVERED; +} + +static void mhi_pci_io_resume(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "PCI slot reset done\n"); + + queue_work(system_long_wq, &mhi_pdev->recovery_work); +} + static const struct pci_error_handlers mhi_pci_err_handler = { + .error_detected = mhi_pci_error_detected, + .slot_reset = mhi_pci_slot_reset, + .resume = mhi_pci_io_resume, .reset_prepare = mhi_pci_reset_prepare, .reset_done = mhi_pci_reset_done, }; From patchwork Mon Jan 4 13:49:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356389 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14980260jai; Mon, 4 Jan 2021 05:45:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5QBnxsvMUoCFSXWEIajnvCMhqHDDWUhjJTZtAAilLCqDHM4TNnVDEWODhOemq9EZEVLCg X-Received: by 2002:a50:d553:: with SMTP id f19mr69581090edj.323.1609767909149; Mon, 04 Jan 2021 05:45:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767909; cv=none; d=google.com; s=arc-20160816; b=Hm23xdRD8eG99/ieHhhPw/g/TrNZ24Wr2FOUPLP3AjdKBVH00psQjSY6FNz0Xs4eUc mAbvbi7zRCzJONQVYKDYzEbdBZoAKi+/QWxnh9IWbibNX0Gr960bEhSs08iF55+yQpDx lU8HqX+7Yby/LqSjft1fynW6YDjsY7CqICKQTEhXJJWV0ttLSsKt1f1/CbeTo3mcrnBM yd3vxOm9zqmbvvp8kniK5XpuEcqxI6ZYBixGlH8jvZekNfsfkLwoaj5VRjI96YzU4KI0 jHw0XIQ04+UPKNJlN3hVCg3P7WqzhFgst7H6YLMksCKpb9ahAEwfLeRPy9NDPLEHv5Ax ohHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=EOo3BNm4x4mG1DWr8qM1BD2pKXPDPKK8io/piH3q8xM=; b=ZkAuuF2hEinmtmyTl9t/Ya2F89V9izjKMxdGLIFyWixkM0YYcF/re5ADQiGxvzJZwm kk0Jh+XceIS8h/gM80p2gpGZC3qsHaDXNUcsWQUuqtI++7dngf4edqRnhftYUHStZHul y7+zU8BiSe4+mVejc7dLH2dwjb8/C78p4UHHTnwmQqMuPS1zfDDKsrK2yOHxDjGYWXtt Spys8EJfqjmM9GRfeO4MnTYJyW4yIiDrrc81t4+3FbrUkV2dAbnUgpuwLU7+XfrKLvs+ Dtu1P5FguRI54bKkeJWGlfnbeaTH/HxUp0EAv/2GVwkg6FWWq7Zscj473ZLMYNy8Ojoz +NjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L6wvuTc+; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This patch implements a health-check mechanism to check regularly that device is alive (MHI layer can communicate with). If device is not alive (because a crash or unexpected reset), the recovery procedure is triggered. Tested successfully with Telit FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam Reviewed-by: Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 0c12027..7e54d88 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,11 +14,15 @@ #include #include #include +#include #include #define MHI_PCI_DEFAULT_BAR_NUM 0 #define MHI_POST_RESET_DELAY_MS 500 + +#define HEALTH_CHECK_PERIOD (HZ * 2) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -189,6 +193,7 @@ struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; struct work_struct recovery_work; + struct timer_list health_check_timer; unsigned long status; }; @@ -326,6 +331,8 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -351,6 +358,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_dbg(&pdev->dev, "Recovery completed\n"); set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); return; err_unprepare: @@ -360,6 +368,21 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_err(&pdev->dev, "Recovery failed\n"); } +static void health_check(struct timer_list *t) +{ + struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return; + } + + /* reschedule in two seconds */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -376,6 +399,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENOMEM; INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + timer_setup(&mhi_pdev->health_check_timer, health_check, 0); mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -427,6 +451,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + /* start health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_unprepare: @@ -442,6 +469,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -459,6 +487,8 @@ static void mhi_pci_reset_prepare(struct pci_dev *pdev) dev_info(&pdev->dev, "reset\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -502,6 +532,7 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) } set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, @@ -562,6 +593,7 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); /* Transition to M3 state */ @@ -597,6 +629,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) goto err_recovery; } + /* Resume health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_recovery: From patchwork Mon Jan 4 13:49:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356386 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14979027jai; Mon, 4 Jan 2021 05:43:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJxN7zE6h+qC84hPyLRWx79vHK6IrcH/MPbaj9Kd7ueZub4NWL3CHYMQu3UexLKR4+bawsLK X-Received: by 2002:a17:906:3593:: with SMTP id o19mr65780568ejb.377.1609767813568; Mon, 04 Jan 2021 05:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767813; cv=none; d=google.com; s=arc-20160816; b=wdu1SmIfMPNYjcVRnYYcd8pODyBdu2Jk9INpNdjAaU0PxU7n+6bbY586Fsak4y5dj4 g/On1mYgRRL1ziLNInEVgsItALyC346td8yn6nBhd72ZH7b+aCyUICSxjOJmnj/VhIVy r9vvtCrodkXufkEE4oUY9CsOdwUdcodVi5k1cSX085/Fe+t2whgUgeNNIRkvS8urXk7a P7byMTnXBbstLQeGaznOibFOk9gazPUAnWrttfup5jelglsKlah4JQkPgecfvjIdb1IQ Vk92TGqXn4QSrxIrhhd6mC80shPJqCQMBy+wiWtWGe+dZ5XGI0nE1+M3fztXnP+yElQL mwlA== ARC-Message-Signature: i=1; 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Increase the timeout to prevent MHI power-up issues. Signed-off-by: Loic Poulain Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 7e54d88..5188ca2 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -162,7 +162,7 @@ static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .max_channels = 128, - .timeout_ms = 5000, + .timeout_ms = 8000, .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), .ch_cfg = modem_qcom_v1_mhi_channels, .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), From patchwork Mon Jan 4 13:49:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356388 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14979065jai; Mon, 4 Jan 2021 05:43:36 -0800 (PST) X-Google-Smtp-Source: ABdhPJxNwSItptiLbPx9T315FCxoJSYd/Yj7cdIyMsEeefmfCaMpIh9Rt7GFkHvzAoZHW7+on0x0 X-Received: by 2002:a17:906:8058:: with SMTP id x24mr63951910ejw.262.1609767815955; Mon, 04 Jan 2021 05:43:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767815; cv=none; d=google.com; s=arc-20160816; b=KGSLch9uWSrx+TqygfgKaxYjVJYfz518WlnA+ahK48xWGMDjZqmKJK07cLW+MMJKZ5 CGs253DjOkiv3ADw4p08mc93JS7XWuuHJHnYpl0cHY8sC9IsJE2TPD6dWATMk7ntRRN5 pWRAG4Dyx1RZF6Rf6/AWJ7aSP6Y6SMm1PHVlJIXiPkJDvH4NWpRj9BX5un9DH1dTkW2p j91OBSa2ETcfI/PYcb3ymFOLafvW8poDkmU1zk7z8pk5oZgQwciOAYbvyEpsMaZ8IPLQ zujTIOCK1/sx3cb7l/O20Qw+Ok1EbmhLxEOCml4dHQ5seniUYRgnkIVHLfXpwF+UrSHo ju5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=54UD8sDmkp2YqxTR752q2R24vr5pZoViVyeG5l4/Dx8=; b=To4ri7jQMUKcUE8vwPT8iA/EGeRQTnYnhuXTIMSDJi8z1RbL5ax8fxI9EKQhb3rjyn E1X8MhMtI/WuHESWQmP8P0dEcwqSHzu/e5AvSePBcd4NLmRJEJCveFgPS/FG1e8ncrJ7 Yws8oeYwtgqr4s2l/ZfTgChOTpIOgnKCHvyAkYyWg+HQgrcVkUPIKSIMhfbujnhmlSeQ 24lAn197h0z5HyDy8iQfQco/VwBQdRM3Sj+dIfUFqKueASCjx45zqGxnuEi5pmzadtxo WsESY283I/dLjaIpzwzRUUmpIw2TCM5aMolpQPKeF16skiItHS+2Szg/wK9hd3KF2GLM +oUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kv2TLMJU; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Qualcomm Diag is the qualcomm diagnostics interface that can be used to collect modem logs, events, traces, etc. It can be used by tools such QPST or QXDM. This patch adds the DIAG channels and a dedicated event ring. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 5188ca2..a4b6221 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -142,22 +142,26 @@ struct mhi_pci_dev_info { } static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ MHI_EVENT_CONFIG_CTRL(0), + /* DIAG dedicated event ring */ + MHI_EVENT_CONFIG_DATA(1), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(1, 100), - MHI_EVENT_CONFIG_HW_DATA(2, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 101) }; static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Mon Jan 4 13:49:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356387 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14979056jai; Mon, 4 Jan 2021 05:43:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJyncfNTLOdbHgZeu8dzPGTl1/yqIpAcxehA3fwMAOD979Aha+6Uym/FjWlV5ikXy90/1TGL X-Received: by 2002:a17:906:ae14:: with SMTP id le20mr68525373ejb.451.1609767815544; Mon, 04 Jan 2021 05:43:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609767815; cv=none; d=google.com; s=arc-20160816; b=Fv0UGekbfOgYFMbf/kJ8XvF1gc/X/71kfVJqH95De9lMRg26tU6TGDnJZnD08h/RgB lG8F93pl8GyWVn2SxdNwTXhrJXcUqeW6k0Mg+oM3PezroDKK7A4PX/KhuKS9Q684N1bg aUGclEJNY5O+7srbIGW90/YYjSC3jYLUiAk53+SVlQetJ+avgTaSBuoHdUcg0mQVAwPP My4J1JReq6tUWt0FhF4LY5CbNCkz2Z0EjCQhkN7p8RFZMbPzSqzW1IB6ohsX5fPpha4j N47zuN4YUze/J3tQHFuAQ8hxymy+9yWlba5ikfQRZ4e7D9uzhyZxFa6RN8tkdrVdy5dT BjXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=9tlpLam/mx4YYUtrncjvdnpIoZDvtEDwVLBS4GoWT3k=; b=0YOjZWeUviy19AoGLLd6HVBxHQfiRVf9tK0rwBN527ARyc5ZPn4ybrSPdgbjtngEWb xsI/b5mynT2ANK/3Id0yWZro+L7phsQlquqF7PRCzEDvyh/4T+hhYgyPmHVXEaN3I06u rNpT2587ZI6b5LY14GrJ/S6ecoDnklwf1pigdKtQG3MXxa2+TtFO8F48TFon2UwsOEP9 1DOcPN0eLXRvgxeEO6aZlI2x1BF+NtOhFUA0SBGM4YraSd7jXoKZRjwPS7uJVJmzqmGW 0B6hO8l0mPNapuhb8Kbsc1RG7S2ZQs+TqmNNvUeyD/ukG+jOykaeLX7FW9IXcigAfQ/s S0sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AXwp40Bn; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t1si26607096ejc.524.2021.01.04.05.43.35; Mon, 04 Jan 2021 05:43:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AXwp40Bn; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbhADNnc (ORCPT + 15 others); Mon, 4 Jan 2021 08:43:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbhADNnc (ORCPT ); Mon, 4 Jan 2021 08:43:32 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B534C0617A3 for ; Mon, 4 Jan 2021 05:42:19 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id i9so32216002wrc.4 for ; Mon, 04 Jan 2021 05:42:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9tlpLam/mx4YYUtrncjvdnpIoZDvtEDwVLBS4GoWT3k=; b=AXwp40BnBQH4Q5DqRaRwfoWGI4DCTmVT/p0zNuEIXLg3C7uEDVk6B3NzGFmuZzgheZ IgnLoDm7PO4gqsqP4g59S0WM58AraDhFRia1RIXsGcRE5Nzq1fC9hBvycLRYabIhg4cw pVK6x9vIjd8myoq/gInNghuoFDj5NoVRdbBH5uLRzTM6gj1kP/sXStNvu0VSpi7cLfs1 j7o0bweKr/TC3VTWgwAbHTthi4WAw4mHXuo6dUG7Lneqf+NbTO63qRRN/XAdm8ybWW1n h0JbNO7FJWJN4pcjFacjpJ8y9fwOTDWsPLAdjbxb7HKdZNyiacP2u9UIZEv2XuDT6C0o 2Zwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9tlpLam/mx4YYUtrncjvdnpIoZDvtEDwVLBS4GoWT3k=; b=o83HKkZSNg2ykflv25mIM3lYv/yhTX267Fp17VHuO3J0untW3yzJClxuutRx0X8r9i 51FeHK765HlVLvS9Y5VBzy/Fpj0QH5KXyMeVYDz9xwYrIS7xGlY+hJCe7a9shdckO3Ta WFYHI4MsrB/0InNovzBKFhmQKps/TJuJDnbMrbZ8waqRXLsOYc2ww4/Oot8NsAaOwIbO vF2x1+QbOm7BCUbNSxyFT+I4IIVViPxnoc5ADqekJfiz/J2/j7DVoPm7psHlJvUYgK70 eB0NWbOpd1Tcp1O+iS5lTNRLHYsYKZpz1yzhXWFmNtYZ0Ls/IbQe+ABmZuSoyIgUYEhD I4OQ== X-Gm-Message-State: AOAM530XLHEjNL63c7AfHlAd+ATfNx8ncBF3Y7/w26ymo4xEdCtVo3L2 9VYIdYKvFUplH8OztXn0X2IWw1gOMaG3mBwJ X-Received: by 2002:adf:ee4d:: with SMTP id w13mr80080322wro.216.1609767737803; Mon, 04 Jan 2021 05:42:17 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id w4sm34042968wmc.13.2021.01.04.05.42.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 05:42:17 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v7 10/10] mhi: pci_generic: Set irq moderation value to 1ms for hw channels Date: Mon, 4 Jan 2021 14:49:39 +0100 Message-Id: <1609768179-10132-11-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> References: <1609768179-10132-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MHI hardware channels are usually the hardware accelerated data path e.g. IP packets path for modems. This path needs to be optimized for low latency and high throughput. After several tests on FN980m SDX55 based modem, it seems 1ms is a good default irq_moderation value: - It allows to reach the maximum download throughput - It introduces limited latency (5ms is too high) - It prevents interrupt flooding Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index a4b6221..1603c83 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -130,7 +130,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ .num_elements = 256, \ - .irq_moderation_ms = 5, \ + .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ .mode = MHI_DB_BRST_DISABLE, \