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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e10si1262001ywh.130.2018.02.16.13.56.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 16 Feb 2018 13:56:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gozcc76Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emnzm-0006lg-Mk for patch@linaro.org; Fri, 16 Feb 2018 16:56:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emnzN-0006k9-90 for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emnzL-0007OV-Fy for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:17 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:44816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1emnzL-0007OI-73 for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:15 -0500 Received: by mail-pl0-x241.google.com with SMTP id w21so2372380plp.11 for ; Fri, 16 Feb 2018 13:56:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nr9Iyx5NP+Nh6KPd1lKtecWd674sH0+DBAayKxV8yEY=; b=gozcc76ZqeGHc6TTs4YjOEdnipzOs2AIW7ru4yGNmNX2UY11nlGsRgL6M2SU21e6SS qnRnxBsXmou8faiTfVU4aOjZeipSZDUPXJGpZ8FqJ2xngS4QB0GyO03a5kVEHJ4d0A9A Y0gYXLNyJgE+KvvZbHpucAqHUMvzsYWqqijw4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nr9Iyx5NP+Nh6KPd1lKtecWd674sH0+DBAayKxV8yEY=; b=IzB40beXZy1lxKc9RJpEYtmhYFLQe1Wf+RKIQgj8AhWug6p9XD1jpQHz9P95viUnFt pvg6+aOY8woJ8aBJeq/h9qF+FXMDZRKH2sMi6SMlS4ICwlG4HNw6R3B+OtlB2oBYd8yt Cfwouis3OkrJb5j92PU3q4MbHIBrR34lj8QDijFlKcVlgY6tXCia70Xehv4c7ZjjAQx6 YgvLQvnFiqTgt0TD8S7PSGszZxODLJ7wazqFcPBAa9B6i/upV6sb5Yz3CxxCKu9ZaDqT L8WzcTsvY3CYKM2RhvJiIpjWQT+aB+eiMQMeskCVRoTn9GQVSp7v5A8QPMQuXUXWKQf/ VoNA== X-Gm-Message-State: APf1xPAcmTAuiVx7aA7KvfBYvx7kqTxBIAl888A7q2N4nCf2jAwej6s5 MJFk+2yEAIqNAFqKB8bpd4Vhl+laAI0= X-Received: by 2002:a17:902:f:: with SMTP id 15-v6mr6929574pla.419.1518818173758; Fri, 16 Feb 2018 13:56:13 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id b88sm39230538pfd.108.2018.02.16.13.56.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Feb 2018 13:56:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 16 Feb 2018 13:56:04 -0800 Message-Id: <20180216215608.13227-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180216215608.13227-1-richard.henderson@linaro.org> References: <20180216215608.13227-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 1/5] linux-user: Implement aarch64 PR_SVE_SET/GET_VL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 3 +++ target/arm/cpu.h | 1 + linux-user/syscall.c | 27 ++++++++++++++++++++++++ target/arm/cpu64.c | 41 +++++++++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 604ab99b14..205265e619 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -19,4 +19,7 @@ struct target_pt_regs { #define TARGET_MLOCKALL_MCL_CURRENT 1 #define TARGET_MLOCKALL_MCL_FUTURE 2 +#define TARGET_PR_SVE_SET_VL 50 +#define TARGET_PR_SVE_GET_VL 51 + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index de62df091c..f5fbb9b450 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -846,6 +846,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); #endif target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 82b35a6bdf..cf00ce10f1 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10659,6 +10659,33 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; } #endif +#ifdef TARGET_AARCH64 + case TARGET_PR_SVE_SET_VL: + /* We cannot support either PR_SVE_SET_VL_ONEXEC + or PR_SVE_VL_INHERIT. Therefore, anything above + ARM_MAX_VQ results in EINVAL. */ + ret = -TARGET_EINVAL; + if (arm_feature(cpu_env, ARM_FEATURE_SVE) + && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { + CPUARMState *env = cpu_env; + int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + int vq = MAX(arg2 / 16, 1); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] = vq - 1; + ret = vq * 16; + } + break; + case TARGET_PR_SVE_GET_VL: + ret = -TARGET_EINVAL; + if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { + CPUARMState *env = cpu_env; + ret = ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; + } + break; +#endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: /* Disable seccomp to prevent the target disabling syscalls we diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..a0a81014b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,3 +363,44 @@ static void aarch64_cpu_register_types(void) } type_init(aarch64_cpu_register_types) + +/* The manual says that when SVE is enabled and VQ is widened the + * implementation is allowed to zero the previously inaccessible + * portion of the registers. The corollary to that is that when + * SVE is enabled and VQ is narrowed we are also allowed to zero + * the now inaccessible portion of the registers. + * + * The intent of this is that no predicate bit beyond VQ is ever set. + * Which means that some operations on predicate registers themselves + * may operate on full uint64_t or even unrolled across the maximum + * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally + * may well be cheaper than conditionals to restrict the operation + * to the relevant portion of a uint16_t[16]. + * + * TODO: Need to call this for changes to the real system registers + * and EL state changes. + */ +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) +{ + int i, j; + uint64_t pmask; + + assert(vq >= 1 && vq <= ARM_MAX_VQ); + + /* Zap the high bits of the zregs. */ + for (i = 0; i < 32; i++) { + memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); + } + + /* Zap the high bits of the pregs and ffr. */ + pmask = 0; + if (vq & 3) { + pmask = ~(-1ULL << (16 * (vq & 3))); + } + for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { + for (i = 0; i < 17; ++i) { + env->vfp.pregs[i].p[j] &= pmask; + } + pmask = 0; + } +} From patchwork Fri Feb 16 21:56:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128652 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1019777ljc; Fri, 16 Feb 2018 14:01:43 -0800 (PST) X-Google-Smtp-Source: AH8x225/GxqJ+G+CdNGEKO0yC1kZ+cXbVEhTk2/aGQ3XP+MqTqpmFp9gHOWOKG3MhvIrBe6ry75+ X-Received: by 10.37.81.3 with SMTP id f3mr5490019ybb.99.1518818503688; Fri, 16 Feb 2018 14:01:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518818503; cv=none; d=google.com; s=arc-20160816; b=KtI18mUYrp3hg39ppg2KCkMbNDlDYfxxsRzjHyMRQjEdbFZWnLJ49zYsREPaKn+CMk 15GuxBCdaQ5QMwlqUW7MwotlTj/DIlVR0dX7LYpcvK2bieNyr/Sje1RS0PtS5eIu40Mt vKmVGsEqKZZOl18hNwX0MINA2S/QBqicUwCsmAmm9wMieo6qwoxYmYC7d+f9OZphEGI2 79D7Nr1r18uRP7C2r31nEe39qItpivEyqHucrSopIywuU+FF660BT6lekNTNQOIJJZZ2 J8OArkxVRYczQV+PooX7ONgmzcTbSCapWPzKWRnFR8mKCq/CcQwpMAMnlsf4TUnjCoRN 7XJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uQrg57S+1ciiLZZckCpcfg+FQGP817cnRwWY4yG6r2w=; b=SHYLTJqvY/ReQg7OCqUEUl2aHf1/Gm1TY+g2rf/9HFyIhyQ721im2wzH7bYLOxcGu0 j+/PMWW9yjW5a/tDSr+oT+ydsXD6QtBXXLw5EZhvW+RHyQ0XmDR0XPEOd9wQARItYVyO y+z35NBhhZcKfcO29iqglSXe8qaJo477WSgLZw1n/dSjvWJ4kIMeTFrdVi9GLevCw+vM Bro7Xv+AFheO6QLz+WDLMaqtqci4vGGfaZZiOPWpSKi3Rlu6zmnOr6m7UVe+nVtDi6Qk 4B4sagm5N/80gJOp+7VOD8yh6jfJ/RXRDF0nYu6yCW3fJuwl0+2LUd4w8KnaSfW4Gz7Y sYmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IUsjKqvG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 2/5] aarch64-linux-user: Split out helpers for guest signal handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out helpers from target_setup_frame and target_restore_sigframe for dealing with general registers, fpsimd registers, and the end record. When we add support for sve registers, the relative positions of these will change. Signed-off-by: Richard Henderson --- linux-user/signal.c | 120 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 69 insertions(+), 51 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/linux-user/signal.c b/linux-user/signal.c index 9a380b9e31..25c9743aed 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1462,16 +1462,17 @@ struct target_rt_sigframe { uint32_t tramp[2]; }; -static int target_setup_sigframe(struct target_rt_sigframe *sf, - CPUARMState *env, target_sigset_t *set) +static void target_setup_general_frame(struct target_rt_sigframe *sf, + CPUARMState *env, target_sigset_t *set) { int i; - struct target_aux_context *aux = - (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; - /* set up the stack frame for unwinding */ - __put_user(env->xregs[29], &sf->fp); - __put_user(env->xregs[30], &sf->lr); + __put_user(0, &sf->uc.tuc_flags); + __put_user(0, &sf->uc.tuc_link); + + __put_user(target_sigaltstack_used.ss_sp, &sf->uc.tuc_stack.ss_sp); + __put_user(sas_ss_flags(env->xregs[31]), &sf->uc.tuc_stack.ss_flags); + __put_user(target_sigaltstack_used.ss_size, &sf->uc.tuc_stack.ss_size); for (i = 0; i < 31; i++) { __put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]); @@ -1485,39 +1486,42 @@ static int target_setup_sigframe(struct target_rt_sigframe *sf, for (i = 0; i < TARGET_NSIG_WORDS; i++) { __put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]); } +} + +static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd, + CPUARMState *env) +{ + int i; + + __put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic); + __put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size); + __put_user(vfp_get_fpsr(env), &fpsimd->fpsr); + __put_user(vfp_get_fpcr(env), &fpsimd->fpcr); for (i = 0; i < 32; i++) { uint64_t *q = aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); - __put_user(q[1], &aux->fpsimd.vregs[i * 2]); + __put_user(q[0], &fpsimd->vregs[i * 2 + 1]); + __put_user(q[1], &fpsimd->vregs[i * 2]); #else - __put_user(q[0], &aux->fpsimd.vregs[i * 2]); - __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[0], &fpsimd->vregs[i * 2]); + __put_user(q[1], &fpsimd->vregs[i * 2 + 1]); #endif } - __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr); - __put_user(vfp_get_fpcr(env), &aux->fpsimd.fpcr); - __put_user(TARGET_FPSIMD_MAGIC, &aux->fpsimd.head.magic); - __put_user(sizeof(struct target_fpsimd_context), - &aux->fpsimd.head.size); - - /* set the "end" magic */ - __put_user(0, &aux->end.magic); - __put_user(0, &aux->end.size); - - return 0; } -static int target_restore_sigframe(CPUARMState *env, - struct target_rt_sigframe *sf) +static void target_setup_end_record(struct target_aarch64_ctx *end) +{ + __put_user(0, &end->magic); + __put_user(0, &end->size); +} + +static void target_restore_general_frame(CPUARMState *env, + struct target_rt_sigframe *sf) { sigset_t set; - int i; - struct target_aux_context *aux = - (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; - uint32_t magic, size, fpsr, fpcr; uint64_t pstate; + int i; target_to_host_sigset(&set, &sf->uc.tuc_sigmask); set_sigmask(&set); @@ -1530,30 +1534,48 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(env->pc, &sf->uc.tuc_mcontext.pc); __get_user(pstate, &sf->uc.tuc_mcontext.pstate); pstate_write(env, pstate); +} - __get_user(magic, &aux->fpsimd.head.magic); - __get_user(size, &aux->fpsimd.head.size); +static void target_restore_fpsimd_record(CPUARMState *env, + struct target_fpsimd_context *fpsimd) +{ + uint32_t fpsr, fpcr; + int i; - if (magic != TARGET_FPSIMD_MAGIC - || size != sizeof(struct target_fpsimd_context)) { - return 1; - } + __get_user(fpsr, &fpsimd->fpsr); + vfp_set_fpsr(env, fpsr); + __get_user(fpcr, &fpsimd->fpcr); + vfp_set_fpcr(env, fpcr); for (i = 0; i < 32; i++) { uint64_t *q = aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __get_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); - __get_user(q[1], &aux->fpsimd.vregs[i * 2]); + __get_user(q[0], &fpsimd->vregs[i * 2 + 1]); + __get_user(q[1], &fpsimd->vregs[i * 2]); #else - __get_user(q[0], &aux->fpsimd.vregs[i * 2]); - __get_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[0], &fpsimd->vregs[i * 2]); + __get_user(q[1], &fpsimd->vregs[i * 2 + 1]); #endif } - __get_user(fpsr, &aux->fpsimd.fpsr); - vfp_set_fpsr(env, fpsr); - __get_user(fpcr, &aux->fpsimd.fpcr); - vfp_set_fpcr(env, fpcr); +} +static int target_restore_sigframe(CPUARMState *env, + struct target_rt_sigframe *sf) +{ + struct target_aux_context *aux + = (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; + uint32_t magic, size; + + target_restore_general_frame(env, sf); + + __get_user(magic, &aux->fpsimd.head.magic); + __get_user(size, &aux->fpsimd.head.size); + if (magic == TARGET_FPSIMD_MAGIC + && size == sizeof(struct target_fpsimd_context)) { + target_restore_fpsimd_record(env, &aux->fpsimd); + } else { + return 1; + } return 0; } @@ -1580,6 +1602,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, CPUARMState *env) { struct target_rt_sigframe *frame; + struct target_aux_context *aux; abi_ulong frame_addr, return_addr; frame_addr = get_sigframe(ka, env); @@ -1587,17 +1610,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv; } + aux = (struct target_aux_context *)frame->uc.tuc_mcontext.__reserved; - __put_user(0, &frame->uc.tuc_flags); - __put_user(0, &frame->uc.tuc_link); + target_setup_general_frame(frame, env, set); + target_setup_fpsimd_record(&aux->fpsimd, env); + target_setup_end_record(&aux->end); - __put_user(target_sigaltstack_used.ss_sp, - &frame->uc.tuc_stack.ss_sp); - __put_user(sas_ss_flags(env->xregs[31]), - &frame->uc.tuc_stack.ss_flags); - __put_user(target_sigaltstack_used.ss_size, - &frame->uc.tuc_stack.ss_size); - target_setup_sigframe(frame, env, set); if (ka->sa_flags & TARGET_SA_RESTORER) { return_addr = ka->sa_restorer; } else { From patchwork Fri Feb 16 21:56:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128649 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1015893ljc; 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 3/5] aarch64-linux-user: Remove struct target_aux_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This changes the qemu signal frame layout to be more like the kernel's, in that the various records are dynamically allocated rather than fixed in place by a structure. For now, all of the allocation is out of uc.tuc_mcontext.__reserved, so the allocation is actually trivial. That will change with SVE support. Signed-off-by: Richard Henderson --- linux-user/signal.c | 89 ++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 61 insertions(+), 28 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/linux-user/signal.c b/linux-user/signal.c index 25c9743aed..f9eef3d753 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1443,20 +1443,12 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; -/* - * Auxiliary context saved in the sigcontext.__reserved array. Not exported to - * user space as it will change with the addition of new context. User space - * should check the magic/size information. - */ -struct target_aux_context { - struct target_fpsimd_context fpsimd; - /* additional context to be added before "end" */ - struct target_aarch64_ctx end; -}; - struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; +}; + +struct target_rt_frame_record { uint64_t fp; uint64_t lr; uint32_t tramp[2]; @@ -1562,20 +1554,47 @@ static void target_restore_fpsimd_record(CPUARMState *env, static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { - struct target_aux_context *aux - = (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved; - uint32_t magic, size; + struct target_aarch64_ctx *ctx; + struct target_fpsimd_context *fpsimd = NULL; target_restore_general_frame(env, sf); - __get_user(magic, &aux->fpsimd.head.magic); - __get_user(size, &aux->fpsimd.head.size); - if (magic == TARGET_FPSIMD_MAGIC - && size == sizeof(struct target_fpsimd_context)) { - target_restore_fpsimd_record(env, &aux->fpsimd); - } else { + ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved; + while (ctx) { + uint32_t magic, size; + + __get_user(magic, &ctx->magic); + __get_user(size, &ctx->size); + switch (magic) { + case 0: + if (size != 0) { + return 1; + } + ctx = NULL; + continue; + + case TARGET_FPSIMD_MAGIC: + if (fpsimd || size != sizeof(struct target_fpsimd_context)) { + return 1; + } + fpsimd = (struct target_fpsimd_context *)ctx; + break; + + default: + /* Unknown record -- we certainly didn't generate it. + * Did we in fact get out of sync? + */ + return 1; + } + ctx = (void *)ctx + size; + } + + /* Require FPSIMD always. */ + if (!fpsimd) { return 1; } + target_restore_fpsimd_record(env, fpsimd); + return 0; } @@ -1601,20 +1620,33 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUARMState *env) { + int size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved); + int fpsimd_ofs, end1_ofs, fr_ofs; struct target_rt_sigframe *frame; - struct target_aux_context *aux; + struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; + fpsimd_ofs = size; + size += sizeof(struct target_fpsimd_context); + end1_ofs = size; + size += sizeof(struct target_aarch64_ctx); + fr_ofs = size; + size += sizeof(struct target_rt_frame_record); + frame_addr = get_sigframe(ka, env); trace_user_setup_frame(env, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv; } - aux = (struct target_aux_context *)frame->uc.tuc_mcontext.__reserved; target_setup_general_frame(frame, env, set); - target_setup_fpsimd_record(&aux->fpsimd, env); - target_setup_end_record(&aux->end); + target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); + target_setup_end_record((void *)frame + end1_ofs); + + /* Set up the stack frame for unwinding. */ + fr = (void *)frame + fr_ofs; + __put_user(env->xregs[29], &fr->fp); + __put_user(env->xregs[30], &fr->lr); if (ka->sa_flags & TARGET_SA_RESTORER) { return_addr = ka->sa_restorer; @@ -1624,13 +1656,14 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, * Since these are instructions they need to be put as little-endian * regardless of target default or current CPU endianness. */ - __put_user_e(0xd2801168, &frame->tramp[0], le); - __put_user_e(0xd4000001, &frame->tramp[1], le); - return_addr = frame_addr + offsetof(struct target_rt_sigframe, tramp); + __put_user_e(0xd2801168, &fr->tramp[0], le); + __put_user_e(0xd4000001, &fr->tramp[1], le); + return_addr = frame_addr + fr_ofs + + offsetof(struct target_rt_frame_record, tramp); } env->xregs[0] = usig; env->xregs[31] = frame_addr; - env->xregs[29] = env->xregs[31] + offsetof(struct target_rt_sigframe, fp); + env->xregs[29] = frame_addr + fr_ofs; env->pc = ka->_sa_handler; env->xregs[30] = return_addr; if (info) { From patchwork Fri Feb 16 21:56:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128651 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1017546ljc; Fri, 16 Feb 2018 13:59:44 -0800 (PST) X-Google-Smtp-Source: AH8x224lLAOmS6sQi+SVIupE4eAy9fDtrUUWxdWc2kdBDPxt3/Q8iI79p17vVGHujre9H+7HbA96 X-Received: by 10.129.37.14 with SMTP id l14mr5933360ywl.412.1518818383933; Fri, 16 Feb 2018 13:59:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518818383; cv=none; d=google.com; s=arc-20160816; b=Lj6Hiq8K8lvHoonYHEsYRNMsiFMvJQFTaqOJtij7bSgqpAfwaEMwZtfVuxeZR+I2bl UjHPbIvouNrWi2byG9UwJAHwkO1od4xNUrkg2zq0zhrjcHSy7c3nLNpusI7RiCoeHqwi NRyqnQ2TlprQYM0DLiuTDsnxPSvpm0czFxROMtZXmyQqSbLGDX+02naNm62g5cgvjzGC 6bUDBbwqky4Aw1N+/fkP2TeyXq53cG7rkswVqLKvIxGCzpTsSPCPjVwp6dShbxwyTGwX dak0oVtII+FADce/roBbFdS9l7gqjCVziwLAkNN1HfeKS9/GdseUzRccrk96ysGW07bG pGCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=pnJnOBb4bnqWYBFZVnu+EyVcw82Gc2SEw4s7fOWRy0A=; b=MrSeGeZIx4b1GdJkR2q6Bbh+8ozVQcRrxKDk9JKkBPuBwh7icsDqgBe/WMaL+py/Iz uskfdVdI3M1/cZ9jQcZkcwM8pBrUHRrCpgBXSRNdGdPHlPby3XiBCn8mVTxicNSBtAHF 4maO92/iw+F3s3OLEUeu2etwp0o0V4FrsquEFNYKJ9Ntcd9Yo2/Ef4IsMvpLgk7tkl3G VYR5MCIgdHRT/K3lUxQ7UlNDilygvar1z2juDbsiKtJunrF7PSG59snOKl9c5JleR4q7 1SAFjpc3yrzV8ep5sipNA9//rx/Tmo3/52x2MmT1EuOvsYN6i8C3wg9SaES8h1fkFPFz WARQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hEcP2Z0O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n142si1554700yba.153.2018.02.16.13.59.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 16 Feb 2018 13:59:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hEcP2Z0O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36908 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emo2h-0000vM-AY for patch@linaro.org; Fri, 16 Feb 2018 16:59:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emnzQ-0006ln-RC for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emnzP-0007QA-SJ for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:20 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:34081) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1emnzP-0007Pv-Jv for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:19 -0500 Received: by mail-pl0-x242.google.com with SMTP id bd10so2396504plb.1 for ; Fri, 16 Feb 2018 13:56:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pnJnOBb4bnqWYBFZVnu+EyVcw82Gc2SEw4s7fOWRy0A=; b=hEcP2Z0OmTnPITCTHhOrG4qZNMX2ku5vHoqTN+NJN5rDhfhv7UJA4m6JAVC8G53ocY QVomMhn0vqkK2EjkZYWhUzgOsE+M8AlI1yMmRu9OoV7OhbIzST8eKfs3vKjKzO7dvjH0 MxJb/EdC/dlD/WrUDIKhxGav6BwCdJMHF4rzg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pnJnOBb4bnqWYBFZVnu+EyVcw82Gc2SEw4s7fOWRy0A=; b=loTILtl0CX5wwt2t49vghUp0QlueGPfI7VJH+QfzTMz0wFj5BujfoYOaB/sGsxQ51E OcxLgkLi9hi5bAJJaW2WKJIL1gBojknJpaN9AenzZNCq49AJtLOt508tl0qqK4sYnBKR XYY0wQ884EEvB3xSn8gbIRJ8NSQonyMEj//4eW/V1qbTopBNp8H2cujlzgkF23zTlNCT RGnH+SFl6DxqBngPskPoWlY1ydfwzurW2j5Cr5t17jndZN1nKPVqItpmhS4eaKcgon7b bOGLJycvckvobsoah8sX8jwp25XY3LK4tXMfS5UdHGapA8thZ3rcQ0S2G/noY9FhAA5E t3OQ== X-Gm-Message-State: APf1xPCYTX77AZSXi2zsw7bQcjSYMuGz7xo2IV9wGisU4pT0f3W7CTxi OD18qt0Du2ulaoU2i5Pkjmjuobx5WWQ= X-Received: by 2002:a17:902:7841:: with SMTP id e1-v6mr7017559pln.130.1518818178260; Fri, 16 Feb 2018 13:56:18 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id b88sm39230538pfd.108.2018.02.16.13.56.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Feb 2018 13:56:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 16 Feb 2018 13:56:07 -0800 Message-Id: <20180216215608.13227-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180216215608.13227-1-richard.henderson@linaro.org> References: <20180216215608.13227-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 4/5] aarch64-linux-user: Add support for EXTRA signal frame records X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The EXTRA record allows for additional space to be allocated beyon what is currently reserved. Add code to emit and read this record type. Nothing uses extra space yet. Signed-off-by: Richard Henderson --- linux-user/signal.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/linux-user/signal.c b/linux-user/signal.c index f9eef3d753..ca0ba28c98 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1443,6 +1443,15 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; +#define TARGET_EXTRA_MAGIC 0x45585401 + +struct target_extra_context { + struct target_aarch64_ctx head; + uint64_t datap; /* 16-byte aligned pointer to extra space cast to __u64 */ + uint32_t size; /* size in bytes of the extra space */ + uint32_t reserved[3]; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -1502,6 +1511,15 @@ static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd, } } +static void target_setup_extra_record(struct target_extra_context *extra, + uint64_t datap, uint32_t extra_size) +{ + __put_user(TARGET_EXTRA_MAGIC, &extra->head.magic); + __put_user(sizeof(struct target_extra_context), &extra->head.size); + __put_user(datap, &extra->datap); + __put_user(extra_size, &extra->size); +} + static void target_setup_end_record(struct target_aarch64_ctx *end) { __put_user(0, &end->magic); @@ -1554,14 +1572,16 @@ static void target_restore_fpsimd_record(CPUARMState *env, static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { - struct target_aarch64_ctx *ctx; + struct target_aarch64_ctx *ctx, *extra = NULL; struct target_fpsimd_context *fpsimd = NULL; + uint64_t extra_datap = 0; + bool used_extra = false; target_restore_general_frame(env, sf); ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved; while (ctx) { - uint32_t magic, size; + uint32_t magic, size, extra_size; __get_user(magic, &ctx->magic); __get_user(size, &ctx->size); @@ -1570,7 +1590,12 @@ static int target_restore_sigframe(CPUARMState *env, if (size != 0) { return 1; } - ctx = NULL; + if (used_extra) { + ctx = NULL; + } else { + ctx = extra; + used_extra = true; + } continue; case TARGET_FPSIMD_MAGIC: @@ -1580,6 +1605,17 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd = (struct target_fpsimd_context *)ctx; break; + case TARGET_EXTRA_MAGIC: + if (extra || size != sizeof(struct target_extra_context)) { + return 1; + } + __get_user(extra_datap, + &((struct target_extra_context *)ctx)->datap); + __get_user(extra_size, + &((struct target_extra_context *)ctx)->size); + extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0); + break; + default: /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? @@ -1595,6 +1631,9 @@ static int target_restore_sigframe(CPUARMState *env, } target_restore_fpsimd_record(env, fpsimd); + if (extra) { + unlock_user(extra, extra_datap, 0); + } return 0; } @@ -1621,7 +1660,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, CPUARMState *env) { int size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved); - int fpsimd_ofs, end1_ofs, fr_ofs; + int fpsimd_ofs, end1_ofs, fr_ofs, end2_ofs = 0; + int extra_ofs = 0, extra_base = 0, extra_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -1641,7 +1681,14 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); + if (extra_ofs) { + target_setup_extra_record((void *)frame + extra_ofs, + frame_addr + extra_base, extra_size); + } target_setup_end_record((void *)frame + end1_ofs); + if (end2_ofs) { + target_setup_end_record((void *)frame + end2_ofs); + } /* Set up the stack frame for unwinding. */ fr = (void *)frame + fr_ofs; From patchwork Fri Feb 16 21:56:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128650 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1015994ljc; Fri, 16 Feb 2018 13:56:57 -0800 (PST) X-Google-Smtp-Source: AH8x224sfhuwFlQBRwf421UtywWlCmICWDgQ68qe6MpJVcm+mDHGrBhjyY514bV/IIXTICpAE/4/ X-Received: by 10.37.171.134 with SMTP id v6mr4324703ybi.84.1518818217605; Fri, 16 Feb 2018 13:56:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518818217; cv=none; d=google.com; s=arc-20160816; b=ZapvyR5wO7pgea6roty2Qx1J+YfkYBRx650uEkSVYH3KrstFRxv6oGR50VLLnM1NfW maBg1s+a6HERnz2+QZY48DVCFdmOi9RyttQf5+7WUGgPdUtftiTdb2kMpHGJRUlSq2wO 6zH7rsrz6AVYJotc9RxfmFMs9AbM8dkfrjyHfj4rSLX5MoI5c/Qv+lQFuqzkw4XmZ0Qf V6ZbzLBN/Ik/VtcBmc5CLtM4sNUXNGZyVuVteKr4xdq/aJcpq17cUj+5tKJ3Jg4SVRTs rvQ1XwiiCVrUZAhZWTWWbpxf0D9Gwg0stcX6bexR+hsz6n1tPNwa17kzJpcTrq5x9HVL 2/6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wd0Cr6tBeciGQREFB4f+Qe6nV8z7KNbw9Scu3ohwBps=; b=XFalLDAA4+ML5izKh1lOmZx0BvWNmfo4bABdBM41bqYfuoE0Iuq3y146Xyjuog58qX LCLHxXXFZKrTgArFdshciN9E9LOLGMyeLk6GvleSn9POT7zmk4QfjvKmc2s4OGTlldw9 BZFwEROivPzfgo2LG/HRu6qHrotOkqk/9ytbIqOXPE83zKA1ybc15gXGmSr7Ma52k2hg FE8HnEYtbmCJXsPpLeVm3u4CmBkkJP7NpVK9z/KaunyFSn/r16z7HumSwxE8CJE3uOdY qLiH0i6AZGOXfhIuFvb0wjKZ7VxBmmbUmtAI1sh83owp12gTrkMd1FpsAXaheME1OItu eu1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dCDFqrkW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 5/5] aarch64-linux-user: Add support for SVE signal frame records X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Depending on the currently selected size of the SVE vector registers, we can either store the data within the "standard" allocation, or we may beedn to allocate additional space with an EXTRA record. Signed-off-by: Richard Henderson --- linux-user/signal.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 138 insertions(+), 3 deletions(-) -- 2.14.3 diff --git a/linux-user/signal.c b/linux-user/signal.c index ca0ba28c98..4c9fef4bb2 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1452,6 +1452,30 @@ struct target_extra_context { uint32_t reserved[3]; }; +#define TARGET_SVE_MAGIC 0x53564501 + +struct target_sve_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; +}; + +#define TARGET_SVE_VQ_BYTES 16 + +#define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8)) + +#define TARGET_SVE_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N)) +#define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (N)) +#define TARGET_SVE_SIG_FFR_OFFSET(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 16)) +#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -1526,6 +1550,34 @@ static void target_setup_end_record(struct target_aarch64_ctx *end) __put_user(0, &end->size); } +static void target_setup_sve_record(struct target_sve_context *sve, + CPUARMState *env, int vq, int size) +{ + int i, j; + + __put_user(TARGET_SVE_MAGIC, &sve->head.magic); + __put_user(size, &sve->head.size); + __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + + /* Note that SVE regs are stored as a byte stream, with each byte element + * at a subsequent address. This corresponds to a little-endian store + * of our 64-bit hunks. + */ + for (i = 0; i < 32; ++i) { + uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __put_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i = 0; i <= 16; ++i) { + uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j = 0; j < vq; ++j) { + uint64_t r = env->vfp.pregs[i].p[j >> 2]; + __put_user_e(r >> ((j & 3) * 16), p + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -1569,13 +1621,44 @@ static void target_restore_fpsimd_record(CPUARMState *env, } } +static void target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, int vq) +{ + int i, j; + + /* Note that SVE regs are stored as a byte stream, with each byte element + * at a subsequent address. This corresponds to a little-endian store + * of our 64-bit hunks. + */ + for (i = 0; i < 32; ++i) { + uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __get_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i = 0; i <= 16; ++i) { + uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j = 0; j < vq; ++j) { + uint16_t r; + __get_user_e(r, p + j, le); + if (j & 3) { + env->vfp.pregs[i].p[j >> 2] |= (uint64_t)r << ((j & 3) * 16); + } else { + env->vfp.pregs[i].p[j >> 2] = r; + } + } + } +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra = NULL; struct target_fpsimd_context *fpsimd = NULL; + struct target_sve_context *sve = NULL; uint64_t extra_datap = 0; bool used_extra = false; + int vq = 0, sve_size = 0; target_restore_general_frame(env, sf); @@ -1605,6 +1688,17 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd = (struct target_fpsimd_context *)ctx; break; + case TARGET_SVE_MAGIC: + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq = (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (!sve && size == sve_size) { + sve = (struct target_sve_context *)ctx; + break; + } + } + return 1; + case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { return 1; @@ -1631,13 +1725,19 @@ static int target_restore_sigframe(CPUARMState *env, } target_restore_fpsimd_record(env, fpsimd); + /* SVE data, if present, overwrites FPSIMD data. */ + if (sve) { + target_restore_sve_record(env, sve, vq); + } + if (extra) { unlock_user(extra, extra_datap, 0); } return 0; } -static abi_ulong get_sigframe(struct target_sigaction *ka, CPUARMState *env) +static abi_ulong get_sigframe(struct target_sigaction *ka, + CPUARMState *env, int size) { abi_ulong sp; @@ -1650,7 +1750,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka, CPUARMState *env) sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size; } - sp = (sp - sizeof(struct target_rt_sigframe)) & ~15; + sp = (sp - size) & ~15; return sp; } @@ -1659,21 +1759,53 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUARMState *env) { + int std_size = sizeof(struct target_rt_sigframe); int size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved); int fpsimd_ofs, end1_ofs, fr_ofs, end2_ofs = 0; int extra_ofs = 0, extra_base = 0, extra_size = 0; + int sve_ofs = 0, vq = 0, sve_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; + /* Reserve space for standard exit marker. */ + std_size -= sizeof(struct target_aarch64_ctx); + + /* FPSIMD record is always in the standard space. */ fpsimd_ofs = size; size += sizeof(struct target_fpsimd_context); end1_ofs = size; + + /* SVE state needs saving only if it exists. */ + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq = (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + + /* For VQ <= 6, there is room in the standard space. */ + if (sve_size <= std_size) { + sve_ofs = size; + size += sve_size; + end1_ofs = size; + } else { + /* Otherwise we need to allocate extra space. */ + extra_ofs = size; + size += sizeof(struct target_extra_context); + end1_ofs = size; + size += QEMU_ALIGN_UP(sizeof(struct target_aarch64_ctx), 16); + extra_base = size; + extra_size = sve_size + sizeof(struct target_aarch64_ctx); + + sve_ofs = size; + size += sve_size; + end2_ofs = size; + } + } size += sizeof(struct target_aarch64_ctx); + fr_ofs = size; size += sizeof(struct target_rt_frame_record); - frame_addr = get_sigframe(ka, env); + frame_addr = get_sigframe(ka, env, size); trace_user_setup_frame(env, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv; @@ -1686,6 +1818,9 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, frame_addr + extra_base, extra_size); } target_setup_end_record((void *)frame + end1_ofs); + if (sve_ofs) { + target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size); + } if (end2_ofs) { target_setup_end_record((void *)frame + end2_ofs); }