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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:10 -0800 Message-Id: <20180228193125.20577-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 01/16] target/arm: Add ARM_FEATURE_V8_RDM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not enabled anywhere yet. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + linux-user/elfload.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.3 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b9740878b..7c8e87544a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1427,6 +1427,7 @@ enum arm_features { ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 8bb9a2c3e8..63cadae1b4 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -551,6 +551,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); + GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); #undef GET_FEATURE return hwcaps; From patchwork Wed Feb 28 19:31:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130057 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp133264lja; Wed, 28 Feb 2018 11:38:14 -0800 (PST) X-Google-Smtp-Source: AG47ELv85i6xYV09r+cr0tXTHnAoOxbLr4dukfeW+cy7WvWG08Op+TmD5Nks8jRlN5afMpb4FL6O X-Received: by 10.129.129.6 with SMTP id r6mr12983224ywf.195.1519846694495; Wed, 28 Feb 2018 11:38:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846694; cv=none; d=google.com; s=arc-20160816; b=Si3w+rbs2tkNdn/8JjjPsJqYmSmw+MvlmisvZKALoruYT0bTy6tbdh7ryTR0vvfod3 GPOOQF0hsfb/0SBY4RyV8NG7okX4sqAXMwsa594yzC+dduVwlD84hY9fyeOLJHh2bKHW FlZsDERRzqIj6K1LG0xc6/l5mwXBZwopZsxfZd/1r0bCxnQ7DCctPHechO/PFC+p5sbH i+jnlrjnAw2+x+N2up5B2UBADDtYNdXb82g7ho5PQMrkE1pMc5UdRW9jTbwDHCzLRfpS X8Il1mNxmxE4V9hm0Qn4h+rePiqhcuXre+10v6av1rTR6ZdV3oGRgpVvPeIA3SOJ2IQt uhIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uMvs/o2ddqXyYFNZ707Chol3lmqK9fZj+/t+Dj/gMrw=; b=odsqwR886PFpnbdjxxPzukRqS4bjUYUeVZ70TJcT+C2IkqJzDmPMaxUIOzxh22Ym87 KkzGLZPJNQN8II09T/0O/kCfU3d4UKkOzTxo8J38Ki8wI7pChNFyD2KjFdNbghGSPRP6 FspOi+xwdzZAI9+S0dgAVHNLiaHxGG4zoXLUgnr9hAnv6amLIcbY0FKZqkuVLtO+G8dB CAiN6aDkQNSTcJKwrfvo3mfzKRGcrLGQEx6GikGB0J1W6NnjCT/IL684MJX8nFfR40wr WiO09vaUj7WgbkTfaK7LfPiN8xv7tgQmuW72ZL7w/zhdO+us2+gbYmYzJ7SLFWHNj2Wq wmzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H5GQDLRG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:11 -0800 Message-Id: <20180228193125.20577-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 02/16] target/arm: Refactor disas_simd_indexed decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Include the U bit in the switches rather than testing separately. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------ 1 file changed, 61 insertions(+), 68 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 32811dc8b0..fc928b61f6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11787,49 +11787,39 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) int index; TCGv_ptr fpst; - switch (opcode) { - case 0x0: /* MLA */ - case 0x4: /* MLS */ - if (!u || is_scalar) { + switch (16 * u + opcode) { + case 0x08: /* MUL */ + case 0x10: /* MLA */ + case 0x14: /* MLS */ + if (is_scalar) { unallocated_encoding(s); return; } break; - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ + case 0x02: /* SMLAL, SMLAL2 */ + case 0x12: /* UMLAL, UMLAL2 */ + case 0x06: /* SMLSL, SMLSL2 */ + case 0x16: /* UMLSL, UMLSL2 */ + case 0x0a: /* SMULL, SMULL2 */ + case 0x1a: /* UMULL, UMULL2 */ if (is_scalar) { unallocated_encoding(s); return; } is_long = true; break; - case 0x3: /* SQDMLAL, SQDMLAL2 */ - case 0x7: /* SQDMLSL, SQDMLSL2 */ - case 0xb: /* SQDMULL, SQDMULL2 */ + case 0x03: /* SQDMLAL, SQDMLAL2 */ + case 0x07: /* SQDMLSL, SQDMLSL2 */ + case 0x0b: /* SQDMULL, SQDMULL2 */ is_long = true; - /* fall through */ - case 0xc: /* SQDMULH */ - case 0xd: /* SQRDMULH */ - if (u) { - unallocated_encoding(s); - return; - } break; - case 0x8: /* MUL */ - if (u || is_scalar) { - unallocated_encoding(s); - return; - } + case 0x0c: /* SQDMULH */ + case 0x0d: /* SQRDMULH */ break; - case 0x1: /* FMLA */ - case 0x5: /* FMLS */ - if (u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x9: /* FMUL, FMULX */ + case 0x01: /* FMLA */ + case 0x05: /* FMLS */ + case 0x09: /* FMUL */ + case 0x19: /* FMULX */ if (size == 1) { unallocated_encoding(s); return; @@ -11909,21 +11899,20 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) read_vec_element(s, tcg_op, rn, pass, MO_64); - switch (opcode) { - case 0x5: /* FMLS */ + switch (16 * u + opcode) { + case 0x05: /* FMLS */ /* As usual for ARM, separate negation for fused multiply-add */ gen_helper_vfp_negd(tcg_op, tcg_op); /* fall through */ - case 0x1: /* FMLA */ + case 0x01: /* FMLA */ read_vec_element(s, tcg_res, rd, pass, MO_64); gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); break; - case 0x9: /* FMUL, FMULX */ - if (u) { - gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); - } + case 0x09: /* FMUL */ + gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); + break; + case 0x19: /* FMULX */ + gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); break; default: g_assert_not_reached(); @@ -11966,10 +11955,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); - switch (opcode) { - case 0x0: /* MLA */ - case 0x4: /* MLS */ - case 0x8: /* MUL */ + switch (16 * u + opcode) { + case 0x08: /* MUL */ + case 0x10: /* MLA */ + case 0x14: /* MLS */ { static NeonGenTwoOpFn * const fns[2][2] = { { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, @@ -11991,8 +11980,8 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) genfn(tcg_res, tcg_op, tcg_res); break; } - case 0x5: /* FMLS */ - case 0x1: /* FMLA */ + case 0x05: /* FMLS */ + case 0x01: /* FMLA */ read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : MO_32); switch (size) { @@ -12023,39 +12012,43 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) g_assert_not_reached(); } break; - case 0x9: /* FMUL, FMULX */ + case 0x09: /* FMUL */ switch (size) { case 1: - if (u) { - if (is_scalar) { - gen_helper_advsimd_mulxh(tcg_res, tcg_op, - tcg_idx, fpst); - } else { - gen_helper_advsimd_mulx2h(tcg_res, tcg_op, - tcg_idx, fpst); - } + if (is_scalar) { + gen_helper_advsimd_mulh(tcg_res, tcg_op, + tcg_idx, fpst); } else { - if (is_scalar) { - gen_helper_advsimd_mulh(tcg_res, tcg_op, - tcg_idx, fpst); - } else { - gen_helper_advsimd_mul2h(tcg_res, tcg_op, - tcg_idx, fpst); - } + gen_helper_advsimd_mul2h(tcg_res, tcg_op, + tcg_idx, fpst); } break; case 2: - if (u) { - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); - } + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); break; default: g_assert_not_reached(); } break; - case 0xc: /* SQDMULH */ + case 0x19: /* FMULX */ + switch (size) { + case 1: + if (is_scalar) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, + tcg_idx, fpst); + } else { + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, + tcg_idx, fpst); + } + break; + case 2: + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); + break; + default: + g_assert_not_reached(); + } + break; + case 0x0c: /* SQDMULH */ if (size == 1) { gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, tcg_op, tcg_idx); @@ -12064,7 +12057,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_op, tcg_idx); } break; - case 0xd: /* SQRDMULH */ + case 0x0d: /* SQRDMULH */ if (size == 1) { gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, tcg_op, tcg_idx); From patchwork Wed Feb 28 19:31:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130052 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp128093lja; Wed, 28 Feb 2018 11:32:24 -0800 (PST) X-Google-Smtp-Source: AG47ELvD3QtDB13Gn8S5gBw+pub+O03/sl4szHmnyFGNgpwOxjlIjVU5QYi+E3Xp66Mi7OMJCHrp X-Received: by 2002:a25:ef48:: with SMTP id w8-v6mr12777599ybm.323.1519846344813; Wed, 28 Feb 2018 11:32:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846344; cv=none; d=google.com; s=arc-20160816; b=rqKXYwbLWl+X0wG614f09CTbwWz2wHjTTGFdiyxDEI3ssNk/SBXYq48auWmwm85v1Z kvT6Xp3Cc/LwAHYmjLge0h069wuNWw5AMzgsOgcZ01vN57QMvWNfimyFm+6dP+ACRawE frJI8CSJhEkSfy+bXb3XWFivYWakxI44WxYRTvk9tk6G9LWWmWbn9rJt+7TUrYulGmyn f37KYxjaA/De4hbOZ4sEeWx1UUh6dDeiV9XvTo8OvFjUpLCSfcYuWLM9uJ46Ol/WntJw RoXnMGJWS+bnn1KRaLbyRdhLQXaoeA5cR0URMLeJSeJ3tEf2dner92DuvvLwMRpdxdSW HnDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aDbouliVWWr3hNOE8ldscKdsfFLWXw8zhcxRCOLGT0M=; b=gPzR2+ZWltNjnHZ+7nhseYNxux5vgJa9HSqhraihKXylG23ySzbOwBNDo0KVRlJp2f wf3yCBsZdtI3Y47irdtdtx0fekiEfoDbJaTbdJUdkamFlgk2+zLzNg9HAyL0vG3r+K12 1D8GO55UqhRWvl67G2/4BFmA+VXvtCZg1Hv++6oBAEuRg1rDy3Y3MNouyamkZgX2UmkS HF8M6+lvL0vRhbgArabSTtdwMb6kn0wmAcHud2DxODv/SheEWREctsH9hgn0tiwqkaFo omP/ix3D2LF/dT5k98rWOwec3U/UP6H40mG5RCWfGysJLRjkM7XPNowjveMVvf9BFS73 KW0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wnn94taC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:12 -0800 Message-Id: <20180228193125.20577-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 03/16] target/arm: Refactor disas_simd_indexed size checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The integer size check was already outside of the opcode switch; move the floating-point size check outside as well. Unify the size vs index adjustment between fp and integer paths. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 +++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 33 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fc928b61f6..cbb4510e3a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11820,10 +11820,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x05: /* FMLS */ case 0x09: /* FMUL */ case 0x19: /* FMULX */ - if (size == 1) { - unallocated_encoding(s); - return; - } is_fp = true; break; default: @@ -11834,45 +11830,48 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) if (is_fp) { /* convert insn encoded size to TCGMemOp size */ switch (size) { - case 2: /* single precision */ - size = MO_32; - index = h << 1 | l; - rm |= (m << 4); - break; - case 3: /* double precision */ - size = MO_64; - if (l || !is_q) { + case 0: /* half-precision */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } - index = h; - rm |= (m << 4); - break; - case 0: /* half precision */ size = MO_16; - index = h << 2 | l << 1 | m; - is_fp16 = true; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { - break; - } - /* fallthru */ - default: /* unallocated */ - unallocated_encoding(s); - return; - } - } else { - switch (size) { - case 1: - index = h << 2 | l << 1 | m; break; - case 2: - index = h << 1 | l; - rm |= (m << 4); + case MO_32: /* single precision */ + case MO_64: /* double precision */ break; default: unallocated_encoding(s); return; } + } else { + switch (size) { + case MO_8: + case MO_64: + unallocated_encoding(s); + return; + } + } + + /* Given TCGMemOp size, adjust register and indexing. */ + switch (size) { + case MO_16: + index = h << 2 | l << 1 | m; + break; + case MO_32: + index = h << 1 | l; + rm |= m << 4; + break; + case MO_64: + if (l || !is_q) { + unallocated_encoding(s); + return; + } + index = h; + rm |= m << 4; + break; + default: + g_assert_not_reached(); } if (!fp_access_check(s)) { From patchwork Wed Feb 28 19:31:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130053 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp128370lja; Wed, 28 Feb 2018 11:32:43 -0800 (PST) X-Google-Smtp-Source: AG47ELuuIxcsLeUsuyHN0jhXZyNN4maltQVUnCFG6gHTsf6Z4rWHP7uTtXG2oUnQ39dc9D2bpEcY X-Received: by 2002:a25:ef48:: with SMTP id w8-v6mr12778163ybm.323.1519846363542; Wed, 28 Feb 2018 11:32:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846363; cv=none; d=google.com; s=arc-20160816; b=SNuZbOWtYRYrikCeLC3L23Qku1HPutl8hqcZVxliyBbxrKZvIbfHXGcDvC2sxdCo1U A7nawaiMQmcoYZ3ijqYpNyFSVKtX2dYM+u7o7Wev8cFng3XSkn8hIs3zQka1l7IEcVNX kc6YKXnVr9m9PUgsIcqn9vUNUjwNuzZImhNutxWvWAztKq3iMOgXCjvrymuqtkq8svbv rragSZWpxFOXEDiY4UnX5niAelaLFWk8CGnVuAAv1ofgMx3wAHr3OadpSRo05/LJUnSD e/7qdwpp0OywnQ7Rlr6osmaThrQ4rfLW7vmjjWoS6KwHFFiE7srW3AQpN9HOjgdJDQW7 EN5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LagkVmHd1ZJZtS9aXV4ueStBZ7NeGvIZxUcN/7ftV6Y=; b=qNER4sAvBv31Ycv6GXi/SLGYOCnNpLfMjll5g7tvndCeCkumTcD8CXDR8j4UXg+OwL NJG7VnJqwpoje90bz3OouC2Ik4YBAvXPH1X1FIYJtXqwv41CYz2HcWL8NNd3Wf7vkZjl F3PMTM7bDi5Y+AfuT4LUxHGEN7ASXQJ55fYrWM8pUtEjUU5bxvXx/nsEfjVrHjUq4Wlc 95NlP1OzVu4ZjlEUs+wf1gOarnJQQDDwRY1yeHpm1QjHEWnX7SPveBlNzGQ7dU371e7K jWzUCcohXR+lFBrWMPgwycMXLI9P5m6r2wJ3X+NnXXxRM1Wps7yjXzPyMrF5Sizd+713 x/eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EBo54WO7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:13 -0800 Message-Id: <20180228193125.20577-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 04/16] target/arm: Decode aa64 armv8.1 scalar three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++ target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 2 +- 4 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 target/arm/vec_helper.c -- 2.14.3 diff --git a/target/arm/helper.h b/target/arm/helper.h index 6dd8504ec3..2075c143d7 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -365,8 +365,12 @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) DEF_HELPER_1(neon_narrow_u8, i32, i64) DEF_HELPER_1(neon_narrow_u16, i32, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cbb4510e3a..746ab0e63a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7971,6 +7971,89 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, tcg_temp_free_ptr(fpst); } +/* AdvSIMD scalar three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, + uint32_t insn) +{ + int rd = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int opcode = extract32(insn, 11, 4); + int rm = extract32(insn, 16, 5); + int size = extract32(insn, 22, 2); + bool u = extract32(insn, 29, 1); + TCGv_i32 ele1, ele2, ele3; + TCGv_i64 res; + int feature; + + switch (u * 16 + opcode) { + case 0x10: /* SQRDMLAH (vector) */ + case 0x11: /* SQRDMLSH (vector) */ + if (size != 1 && size != 2) { + unallocated_encoding(s); + return; + } + feature = ARM_FEATURE_V8_RDM; + break; + default: + unallocated_encoding(s); + return; + } + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + /* Do a single operation on the lowest element in the vector. + * We use the standard Neon helpers and rely on 0 OP 0 == 0 + * with no side effects for all these operations. + * OPTME: special-purpose helpers would avoid doing some + * unnecessary work in the helper for the 16 bit cases. + */ + ele1 = tcg_temp_new_i32(); + ele2 = tcg_temp_new_i32(); + ele3 = tcg_temp_new_i32(); + + read_vec_element_i32(s, ele1, rn, 0, size); + read_vec_element_i32(s, ele2, rm, 0, size); + read_vec_element_i32(s, ele3, rd, 0, size); + + switch (opcode) { + case 0x0: /* SQRDMLAH */ + if (size == 1) { + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + case 0x1: /* SQRDMLSH */ + if (size == 1) { + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_i32(ele1); + tcg_temp_free_i32(ele2); + + res = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(res, ele3); + tcg_temp_free_i32(ele3); + + write_fp_dreg(s, rd, res); + tcg_temp_free_i64(res); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -12798,6 +12881,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, { 0x2e000000, 0xbf208400, disas_simd_ext }, { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c new file mode 100644 index 0000000000..9febdff69c --- /dev/null +++ b/target/arm/vec_helper.c @@ -0,0 +1,109 @@ +/* + * ARM AdvSIMD / SVE Vector Operations + * + * Copyright (c) 2018 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q + +/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Simplify: + * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 + * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret = (int32_t)src1 * src2; + ret = ((int32_t)src3 << 15) + ret + (1 << 14); + ret >>= 15; + if (ret != (int16_t)ret) { + SET_QC(); + ret = (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3); + uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); + return deposit32(e1, 16, 16, e2); +} + +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Similarly, using subtraction: + * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 + * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret = (int32_t)src1 * src2; + ret = ((int32_t)src3 << 15) - ret + (1 << 14); + ret >>= 15; + if (ret != (int16_t)ret) { + SET_QC(); + ret = (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3); + uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16); + return deposit32(e1, 16, 16, e2); +} + +/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlah_s16 above. */ + int64_t ret = (int64_t)src1 * src2; + ret = ((int64_t)src3 << 31) + ret + (1 << 30); + ret >>= 31; + if (ret != (int32_t)ret) { + SET_QC(); + ret = (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} + +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlsh_s16 above. */ + int64_t ret = (int64_t)src1 * src2; + ret = ((int64_t)src3 << 31) - ret + (1 << 30); + ret >>= 31; + if (ret != (int32_t)ret) { + SET_QC(); + ret = (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 847fb52ee0..1297bead5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += neon_helper.o iwmmxt_helper.o +obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-y += crypto_helper.o From patchwork Wed Feb 28 19:31:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130051 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp127986lja; Wed, 28 Feb 2018 11:32:17 -0800 (PST) X-Google-Smtp-Source: AH8x224vThtzwu+LtCB6PR0jiQgOa9GZU07RB/++hoCXLTGmXd4wPQ6whK70a+BV4cuRu6zJoqeC X-Received: by 10.129.175.3 with SMTP id n3mr12496286ywh.343.1519846337075; Wed, 28 Feb 2018 11:32:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846337; cv=none; d=google.com; s=arc-20160816; b=NEgOJTCs6jp9UwuR5Lz7LxHPV2XaPEa3+z5Dfb6OOi9T66bn7JpO+zxXQrRoQ2YrZZ nE76asyj2Ta9fpPK+98vhIeSoUNXW+WodMcyOnDjPCJF36wrTISTB9hbQ1jLSSrcZxjD 4AyXQtuGFSi8rOppI/Wa23zX085asC+WaEGc1gUtAE2Al9EyD7HrCs0vwrGLLyLhg8DJ p+oSFEN0LxMH90BxZOIQqpw+HPsQwPTnRVhi8YWD4J6ajrdjzDDrfthOEi2r0/LsNjqE Uob6VceNcexz/jsVrI77KG0AE7n6RaPW/qMdLoork5YEWDYoFLdKO+aAUnhly4WMgjFJ k0jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Ox43frcyBBsRXXtU/rzifJmIzkl03Y9N3CmA2i1brdA=; b=I4S9zrJngyTnFfHJq1BZNODBItDMo/JyXTJDU1BsrBL+j/73XszGTv+QPOg+mxrsCe dEsNhIegj5SFjH/DDJ3PiX9YRX7HXwe1wQ/MQPtRi0WQWGZBdLtLi+/e7JD8g/WM/UEo EPerEPdRK03yFLOr+TMoIVWanMdQnhtCsC6WCUIj8NRyjmJmNIi6Mji+2NjyVSGu0TM0 kfqhK6tMcua97Mf0Uat0OdyKY52+I+esPDqqLAg5Z7Lfi2Of3HqN+rsdZeCE3yXl91Q1 jDqwBuw1g1JmSpCuIWkTT5SI0BMSvjv0HmGTJwv2GcE9fYMOcppcvr0BqYrX0AgK5M8v CS3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AVyE6hu1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:14 -0800 Message-Id: <20180228193125.20577-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 05/16] target/arm: Decode aa64 armv8.1 three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 9 +++++ target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 166 insertions(+) -- 2.14.3 diff --git a/target/arm/helper.h b/target/arm/helper.h index 2075c143d7..7f0d3b2d84 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -569,6 +569,15 @@ DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 746ab0e63a..ae16313eb0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -701,6 +701,18 @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd, vec_full_reg_size(s), gvec_op); } +/* Expand a 3-operand + env pointer operation using + * an out-of-line helper. + */ +static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, + int rn, int rm, gen_helper_gvec_3_ptr *fn) +{ + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), cpu_env, + is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); +} + /* Set ZF and NF based on a 64 bit result. This is alas fiddlier * than the 32 bit equivalent. */ @@ -10789,6 +10801,76 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) clear_vec_high(s, is_q, rd); } +/* AdvSIMD three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) +{ + int rd = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int opcode = extract32(insn, 11, 4); + int rm = extract32(insn, 16, 5); + int size = extract32(insn, 22, 2); + bool u = extract32(insn, 29, 1); + bool is_q = extract32(insn, 30, 1); + int feature; + + switch (u * 16 + opcode) { + case 0x10: /* SQRDMLAH (vector) */ + case 0x11: /* SQRDMLSH (vector) */ + if (size != 1 && size != 2) { + unallocated_encoding(s); + return; + } + feature = ARM_FEATURE_V8_RDM; + break; + default: + unallocated_encoding(s); + return; + } + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + switch (size) { + case 1: + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16); + break; + case 2: + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32); + break; + default: + g_assert_not_reached(); + } + return; + + case 0x1: /* SQRDMLSH (vector) */ + switch (size) { + case 1: + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16); + break; + case 2: + gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32); + break; + default: + g_assert_not_reached(); + } + return; + + default: + g_assert_not_reached(); + } +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -12869,6 +12951,7 @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) static const AArch64DecodeTable data_proc_simd[] = { /* pattern , mask , fn */ { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9febdff69c..3072df4d77 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -26,6 +26,16 @@ #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) +{ + uint64_t *d = vd + opr_sz; + uintptr_t i; + + for (i = opr_sz; i < max_sz; i += 8) { + *d++ = 0; + } +} + /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) @@ -52,6 +62,22 @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, return deposit32(e1, 16, 16, e2); } +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + int16_t *d = vd; + int16_t *n = vn; + int16_t *m = vm; + CPUARMState *env = ve; + uintptr_t i; + + for (i = 0; i < opr_sz / 2; ++i) { + d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-subtract high half, 16-bit */ static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) @@ -78,6 +104,22 @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, return deposit32(e1, 16, 16, e2); } +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + int16_t *d = vd; + int16_t *n = vn; + int16_t *m = vm; + CPUARMState *env = ve; + uintptr_t i; + + for (i = 0; i < opr_sz / 2; ++i) { + d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) @@ -93,6 +135,22 @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, return ret; } +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + int32_t *d = vd; + int32_t *n = vn; + int32_t *m = vm; + CPUARMState *env = ve; + uintptr_t i; + + for (i = 0; i < opr_sz / 4; ++i) { + d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-subtract high half, 32-bit */ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) @@ -107,3 +165,19 @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, } return ret; } + +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + int32_t *d = vd; + int32_t *n = vn; + int32_t *m = vm; + CPUARMState *env = ve; + uintptr_t i; + + for (i = 0; i < opr_sz / 4; ++i) { + d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} From patchwork Wed Feb 28 19:31:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130055 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp130989lja; Wed, 28 Feb 2018 11:35:40 -0800 (PST) X-Google-Smtp-Source: AG47ELtzv1SwGTI9snY6g1JmF0lcP4G3PZ4U4MfQs0/QMWe1djEWuvygAjfPt1AMX2fLu54/shK/ X-Received: by 2002:a25:d6c7:: with SMTP id n190-v6mr12578120ybg.368.1519846539650; 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:15 -0800 Message-Id: <20180228193125.20577-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 06/16] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.14.3 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ae16313eb0..e4d2d548ba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11987,6 +11987,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x19: /* FMULX */ is_fp = true; break; + case 0x1d: /* SQRDMLAH */ + case 0x1f: /* SQRDMLSH */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -12230,6 +12237,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_op, tcg_idx); } break; + case 0x1d: /* SQRDMLAH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + if (size == 1) { + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } else { + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } + break; + case 0x1f: /* SQRDMLSH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + if (size == 1) { + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } else { + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } + break; default: g_assert_not_reached(); } From patchwork Wed Feb 28 19:31:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130060 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp135349lja; Wed, 28 Feb 2018 11:40:44 -0800 (PST) X-Google-Smtp-Source: AG47ELuSrIco2kWPoTMadcw1FRoa96uX+UaFD3AY6pa+f3hfsu84n9uelhXU+t5+k6+SyUm/NrSb X-Received: by 2002:a25:7649:: with SMTP id r70-v6mr12757123ybc.342.1519846844503; Wed, 28 Feb 2018 11:40:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846844; cv=none; d=google.com; s=arc-20160816; b=SF46Bwr8aGcOi31Y3S6ZYgls70wYW8i1b6nHtDn/4FyUoTTgXD10PTJo+hZa19R+ZN xoDMfCdwuJc7FNziQPW3jyLFjLMrmzoipsvWkxEnmabMUjDTSc1AyFToEHjGp5kv5bL+ xisEZQnNOLAEfyja2smDMO3TlqQSq+FLEvbS8PJynUOyQDjtx+1Lg4a1qz4M5GpQxB0Z MbCexVja32C9PgDwAwp7S1FgN2hhKkslqC8/NFl1haPFXs4Y7xm578kpc7C/At1mRl8b 6e3U9VKdXcJ1JK6reLC5gf28KRxmnjImBYzQSQL8AwBz8PCU8v1OVfkvMKIRCkNuHw6b eG9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qFjrf0fj3fYEerkSuVByoHWTY8OEKjQxncc02aLcsbE=; b=qHyiCm231+Y8zu1+Z+gu++5tGozC9gP7Eww9CYLy32qYhgkoNiA/BObF3jvCFOKIRP lmycNmk8bBOfxFS04ZyOFTFbwk1+/Qsw9LxBMbmyo1RMITNGRXJUimmW7fV4jxKpACD9 L20yQbjuXN6M/jvgPmjCwvf7pIDp+rl59m90kQofYmWb+uaiESkE7/ZmYCs9SLseZCyX 5PWPLrDcIR857twXhdOXuHfImr2sSo1zkeX+dyWdJbbYtXYUVNdA2kFo60UbhSbBktCP qOtlSCEYDnr4tHTbvPCLghrK55Q1ypuzA4gigELE/iiKWaEVoz3novx+NlONcGQHP51B OpNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e7yJ5CRH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 07/16] target/arm: Decode aa32 armv8.1 three same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 19 deletions(-) -- 2.14.3 diff --git a/target/arm/translate.c b/target/arm/translate.c index aa6dcaa577..05fa6a53f9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -25,6 +25,7 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "qemu/bitops.h" #include "arm_ldst.h" @@ -5374,9 +5375,9 @@ static void gen_neon_narrow_op(int op, int u, int size, #define NEON_3R_VPMAX 20 #define NEON_3R_VPMIN 21 #define NEON_3R_VQDMULH_VQRDMULH 22 -#define NEON_3R_VPADD 23 +#define NEON_3R_VPADD_VQRDMLAH 23 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */ -#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */ +#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */ #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */ #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */ #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ @@ -5408,9 +5409,9 @@ static const uint8_t neon_3r_sizes[] = { [NEON_3R_VPMAX] = 0x7, [NEON_3R_VPMIN] = 0x7, [NEON_3R_VQDMULH_VQRDMULH] = 0x6, - [NEON_3R_VPADD] = 0x7, + [NEON_3R_VPADD_VQRDMLAH] = 0x7, [NEON_3R_SHA] = 0xf, /* size field encodes op type */ - [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */ + [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */ [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ @@ -5589,6 +5590,22 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VCVT_UF] = 0x4, }; + +/* Expand v8.1 simd helper. */ +static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, + int q, int rd, int rn, int rm) +{ + if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + int opr_sz = (1 + q) * 8; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), cpu_env, + opr_sz, opr_sz, 0, fn); + return 0; + } + return 1; +} + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -5641,12 +5658,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (q && ((rd | rn | rm) & 1)) { return 1; } - /* - * The SHA-1/SHA-256 3-register instructions require special treatment - * here, as their size field is overloaded as an op type selector, and - * they all consume their input in a single pass. - */ - if (op == NEON_3R_SHA) { + switch (op) { + case NEON_3R_SHA: + /* The SHA-1/SHA-256 3-register instructions require special + * treatment here, as their size field is overloaded as an + * op type selector, and they all consume their input in a + * single pass. + */ if (!q) { return 1; } @@ -5683,6 +5701,40 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(ptr2); tcg_temp_free_ptr(ptr3); return 0; + + case NEON_3R_VPADD_VQRDMLAH: + if (!u) { + break; /* VPADD */ + } + /* VQRDMLAH */ + switch (size) { + case 1: + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16, + q, rd, rn, rm); + case 2: + return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32, + q, rd, rn, rm); + } + return 1; + + case NEON_3R_VFM_VQRDMLSH: + if (!u) { + /* VFM, VFMS */ + if (size == 1) { + return 1; + } + break; + } + /* VQRDMLSH */ + switch (size) { + case 1: + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16, + q, rd, rn, rm); + case 2: + return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32, + q, rd, rn, rm); + } + return 1; } if (size == 3 && op != NEON_3R_LOGIC) { /* 64-bit element instructions. */ @@ -5768,11 +5820,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) rm = rtmp; } break; - case NEON_3R_VPADD: - if (u) { - return 1; - } - /* Fall through */ + case NEON_3R_VPADD_VQRDMLAH: case NEON_3R_VPMAX: case NEON_3R_VPMIN: pairwise = 1; @@ -5806,8 +5854,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; } break; - case NEON_3R_VFM: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) { + case NEON_3R_VFM_VQRDMLSH: + if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { return 1; } break; @@ -6004,7 +6052,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } } break; - case NEON_3R_VPADD: + case NEON_3R_VPADD_VQRDMLAH: switch (size) { case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break; case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break; @@ -6103,7 +6151,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } } break; - case NEON_3R_VFM: + case NEON_3R_VFM_VQRDMLSH: { /* VFMA, VFMS: fused multiply-add */ TCGv_ptr fpstatus = get_fpstatus_ptr(1); From patchwork Wed Feb 28 19:31:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130054 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp130648lja; Wed, 28 Feb 2018 11:35:15 -0800 (PST) X-Google-Smtp-Source: AG47ELtnjjkUsJ7x37LkGMnG37fMAOCN9jLCVfsKUZcfhdk0Xnu1Gviuu9hvsL0KqohduwavdoTY X-Received: by 10.129.201.11 with SMTP id o11mr13066773ywi.2.1519846515846; Wed, 28 Feb 2018 11:35:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846515; cv=none; d=google.com; s=arc-20160816; b=vwrSrehIhvmR0Pd+Qwy7jRpRs/HeiVPYL/ac3Cr7imuQUc8W8zhU3dptvih72mhC19 uQykJdA8m/NTRsuptiWgGHw7blzNdqTJcGPJGcUcw7Y9tYCr09sV7fzPqvOXmwoTJdqp HcPlyW/++xtDRRq7OdkL3QZ2Fhmr402qWnU7g1dpwucpmq481AEShA6NhPNPuey3umKX tFj7nxmSja3aKvwiXW6aoYPyWTJAR8uGbYk/zOHHPsIThM4TyRsy4cvPFHnrpLQW0cfJ u+63AxLZBq2UpkykUUxRBETd6meXKUa+veUtFm6lJFqAGc/bEuFDbljZze3P1KQHccpB tDhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mQkoNHAW8gt1UnT6vN1GNxitBesZm1YW8MnE7dIye3Q=; b=MGa8hMp5R6i+bw544nqbpTImbj2CA/3lM5oiHXs6YeF6YX2Z18yDIK2RlUANg4NSv1 FtPPMXTUpIM9Ifosk4SJlH00Jh42N/5jZmMtzgAaTPvV0DBFDbkDBKv+wwqd3L+Ztka4 1tUprnlYvKKAEoGos8oh3Pbh+48s+73vwc0LLDzp1mm1GsLK19u8UIo0bqBDyzgivPYt bdpeYom8WUl5wuM/LC3Z1fijR66XMgNpTkt/RcZClc0V0T5V4DvdzQJjWW5dtYS3hykp DMNC6OOWrKoHGWs0Y1loLCqap5p+uuQI8DLZ9B5UTFXfzFShE7dkq1HY7RptR+kcju+w KyMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eZ2//YmX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:17 -0800 Message-Id: <20180228193125.20577-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 08/16] target/arm: Decode aa32 armv8.1 two reg and a scalar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/arm/translate.c b/target/arm/translate.c index 05fa6a53f9..9169b6b367 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -76,6 +76,10 @@ static const char *regnames[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; +/* Function prototypes for gen_ functions calling Neon helpers. */ +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, + TCGv_i32, TCGv_i32); + /* initialize TCG globals. */ void arm_translate_init(void) { @@ -6985,11 +6989,45 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } neon_store_reg64(cpu_V0, rd + pass); } - - break; - default: /* 14 and 15 are RESERVED */ - return 1; + case 14: /* VQRDMLAH scalar */ + case 15: /* VQRDMLSH scalar */ + { + NeonGenThreeOpEnvFn *fn; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + return 1; + } + if (u && ((rd | rn) & 1)) { + return 1; + } + if (op == 14) { + if (size == 1) { + fn = gen_helper_neon_qrdmlah_s16; + } else { + fn = gen_helper_neon_qrdmlah_s32; + } + } else { + if (size == 1) { + fn = gen_helper_neon_qrdmlsh_s16; + } else { + fn = gen_helper_neon_qrdmlsh_s32; + } + } + + tmp2 = neon_get_scalar(size, rm); + for (pass = 0; pass < (u ? 4 : 2); pass++) { + tmp = neon_load_reg(rn, pass); + tmp3 = neon_load_reg(rd, pass); + fn(tmp, cpu_env, tmp, tmp2, tmp3); + tcg_temp_free_i32(tmp3); + neon_store_reg(rd, pass, tmp); + } + tcg_temp_free_i32(tmp2); + } + break; + default: + g_assert_not_reached(); } } } else { /* size == 3 */ From patchwork Wed Feb 28 19:31:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130059 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp134822lja; Wed, 28 Feb 2018 11:40:10 -0800 (PST) X-Google-Smtp-Source: AH8x2276m5JW7KurKYpou2CsW1K/4m7PRL1VzkZUqMpWUxdiuM+e8d/UF7xz9N3uq14awmsiY5dw X-Received: by 10.13.250.70 with SMTP id k67mr12675865ywf.79.1519846810567; Wed, 28 Feb 2018 11:40:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846810; cv=none; d=google.com; s=arc-20160816; b=FeTOIwEfp+/nImmLdvcPsHwRcmo+HJvPxK7u8+Z3MiodYI4daNzPNDzZ0N6posPe1i sD31ie/Et0juw+0p0xBBTbqmrML+JiUTWvYsg8kYJRZffkaa4hMno9jom0QmgKJxwxMq GtnmXB7nVxRQUlCUSbigb1R3Z4jhrq4gVYRs5L1dhc29JAzW4h4XWAt+VPSywKYcE1iH yBkHrf6DHZTYlEOUHvBjJuvExxefGLcU5JOcRgQcfC/OfadODQIPPbhf3YAte0tywjSn aSkCdHFkEGEA4VlRD/yqZQOJsDjKeMW71hH1iW7S8VHLnhGICPbzZC8poeEtUtAopQJf dwwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uWNctFB6decpe82M6S7kdxtgGEuN6xi73BI0m6CkSkA=; b=CJY5+3sZqCAg0O7sg3aLENvdrpWute7Vmep+eq14orrcNwJfLjuRIpzzSLRh4SQPQu 3uNCSyxSApshu40pjMLalDy6Lqp11fnNc5MZsRfukOkU/UBEUOwUohuFVaRuXbpV0rJl PFuiGEtBHPFptp3FclS8UmwKaZg7ReFPrF277wSqkkZcJfXLIUSb4Lm7IeTNzWUBOElK lXo/0TkBal1jEoQm7dkYjN+aFgeCL22so19lDFVSVY6a5eb4U/RNx09EMXOKzyg6cino tegwhJRrRc8Ns6CDqmGXjCJl60K0kVPVaZpiwwXKE17oJ6i6ki4AAjfSXwb4qJovJYw9 b0EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5Dxy+nE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:18 -0800 Message-Id: <20180228193125.20577-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable it for the "any" CPU used by *-linux-user. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b3ae62db6..ca5fb1162a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1650,6 +1650,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); cpu->midr = 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9743bdc8c3..7246866e7d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ From patchwork Wed Feb 28 19:31:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130062 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp137096lja; Wed, 28 Feb 2018 11:42:46 -0800 (PST) X-Google-Smtp-Source: AG47ELtx49H2EjrbDO7LyZiM3sqPW1jhQZwrMCUmxY8qNLnT1F+LrS/u9UtcjIG1oOGb/oFa+/Ud X-Received: by 2002:a25:650b:: with SMTP id z11-v6mr13010905ybb.201.1519846966285; Wed, 28 Feb 2018 11:42:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846966; cv=none; d=google.com; s=arc-20160816; b=p9j6GjfzU2ZP1jh9sGwRaQ42WgTzbz64UoDLKU4FD8RdytZSaXQRwFoaLo+baQk70b TbQES4i3v6XeND0KjcUHX2z9RVE8eHph4sbStiipwycRas7poVe7RThiDxKagnMFCaEu imVBYPAPw1Jyxy856+Ac2zvkH9Jlky89U7Q8ZanQrgULh0KYIw3tSIGd5lZpu6M/rlJ4 BkL2MPLCaE/yYOLelDkfe3XvUhUeM6mE6Ix+aJDPFldsEfN33fmoVSHbO6n+0+mFSsI5 Q5QxtvVQryGb5kpFbAROEuiBx2FmgymW+yB8q6bg+ieQneQ1jsMnwUihfZZ1LLjLl1UQ gUPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6tTd5rziva4Db2NHAtyuaXfDAQYshirVeyQ6cgwAcZ8=; b=wr/7hty4gwjKvHm6FijGN821KUmyu9Uo+DqquHkBV9dX7fvBvaix2GUfzUX3CLfkxl q/X7zxI6Zv8Kr80uFsfZlSK/nN88yhL125wofVxCxFrp4lWFV7oYLOBvhB9ja7F11LAV XSGupj8Sed2Ohq1OWWzOsV7Vvk/gp1TDER9ooXDE9n21d0bIWKVeLFNKYqprX+ha6SjK B38aybpfK5ZqBjbcOvpQKqkvLSDVDPmg/++ReFrWLFK2UdV3Yo+c48axegDPcRbik/cH M7VeWAj2QaC8VbusjvIfPf3tymUl0+2Dd1npds22INgQqCPgtMljiTy6Y1DQKAJn0VHC 86JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RRvhdOoz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:19 -0800 Message-Id: <20180228193125.20577-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 10/16] target/arm: Add ARM_FEATURE_V8_FCMA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not enabled anywhere yet. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + linux-user/elfload.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.3 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7c8e87544a..f67f357724 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1429,6 +1429,7 @@ enum arm_features { ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 63cadae1b4..3ead6ed807 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -552,6 +552,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); #undef GET_FEATURE return hwcaps; From patchwork Wed Feb 28 19:31:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130064 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp137676lja; Wed, 28 Feb 2018 11:43:30 -0800 (PST) X-Google-Smtp-Source: AG47ELsdULFr5x8E4cTFOiU5SuOk5COZY/UDkgzIBQ+VENVzSJpuQGUEq9F2w7oD6vhlHauZhsdg X-Received: by 2002:a25:7705:: with SMTP id s5-v6mr4085000ybc.154.1519847009980; Wed, 28 Feb 2018 11:43:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519847009; cv=none; d=google.com; s=arc-20160816; b=LlWnIXn44w+ly527QXZavQS4Bg2/xnD32Mz0Pyk54kaC401iqFEPcLVJ7v8SUoaANw FfZaYPjFhKOPK17tdxCFLzSRQxFCiL8IGAKnpbhRisiNGHOwNkDY6kfK7qOZNrmrMQEA swl2Lh4aOB24WSDQziKLO/saKyxHn5jFAKiuAZ7cyljVTwvNUxZROyQ28z+PAvXEd5YW ZIibA4eyNydtq/r6uBjF/Ig6bX3M/BAfmxEATchWYBER7FIm/35+BkryV8mjQcJZtIny Vs+kpJm0ihdYCFtxb79McDx3NjnGH2d5Ke0RAOwwEcOmO0h7ugdAVYIQrv2tuT2PIPrH 2rhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QMAdSyPvdtTXN/SBmTeRs6Mr28hDgbHsVbc83bn/70I=; b=mkAlx/Mv4e4GyY6f7Yg/iQavHxe1dTuB++U3DfA5W403Vpiix9LcxPFE5P1oCAKU2T 2SZxU0nuDGb3NtXdkBHyqwUjI+bwQykFqDnkiqH1Po5xWEZeIhWImk4F9qgWJq6GJcYY lK7oJCWtToB0FEE3o+Sktwv79DDnIfbcF8Gv/1QGb3rQLrtFb3tqU6l6G7cyNhjfw4Wh AnSueYa0HPrO+XhC87IP1KJjOfbvf+gAp3S3zc1ZkRCD6FsuM1aUdYAXW6AzVS11meY/ hwQypUquiVSCpmDqXq5CNGf3meLV+Rim8CTH+TCohGUYdKyIbgIcf4VStqOhXnrA5ztM Z6BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b+Zrrf+X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:20 -0800 Message-Id: <20180228193125.20577-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 11/16] target/arm: Decode aa64 armv8.3 fcadd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 ++++ target/arm/translate-a64.c | 48 ++++++++++++++++++++++- target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/arm/helper.h b/target/arm/helper.h index 7f0d3b2d84..1e2d7025de 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -578,6 +578,13 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e4d2d548ba..efed4fd9d2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -713,6 +713,21 @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); } +/* Expand a 3-operand + fpstatus pointer + simd data value operation using + * an out-of-line helper. + */ +static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn, + int rm, bool is_fp16, int data, + gen_helper_gvec_3_ptr *fn) +{ + TCGv_ptr fpst = get_fpstatus_ptr(is_fp16); + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); + tcg_temp_free_ptr(fpst); +} + /* Set ZF and NF based on a 64 bit result. This is alas fiddlier * than the 32 bit equivalent. */ @@ -10816,7 +10831,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) int size = extract32(insn, 22, 2); bool u = extract32(insn, 29, 1); bool is_q = extract32(insn, 30, 1); - int feature; + int feature, rot; switch (u * 16 + opcode) { case 0x10: /* SQRDMLAH (vector) */ @@ -10827,6 +10842,16 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = ARM_FEATURE_V8_RDM; break; + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + if (size == 0 + || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) + || (size == 3 && !is_q)) { + unallocated_encoding(s); + return; + } + feature = ARM_FEATURE_V8_FCMA; + break; default: unallocated_encoding(s); return; @@ -10866,6 +10891,27 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } return; + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + rot = extract32(opcode, 1, 1); + switch (size) { + case 1: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, + gen_helper_gvec_fcaddh); + break; + case 2: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, + gen_helper_gvec_fcadds); + break; + case 3: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot, + gen_helper_gvec_fcaddd); + break; + default: + g_assert_not_reached(); + } + return; + default: g_assert_not_reached(); } diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 3072df4d77..a868ca6aac 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -22,8 +22,21 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" +#include "fpu/softfloat.h" +/* Note that vector data is stored in host-endian 64-bit chunks, + so addressing units smaller than that needs a host-endian fixup. */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) @@ -181,3 +194,87 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float16 *d = vd; + float16 *n = vn; + float16 *m = vm; + float_status *fpst = vfpst; + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = neg_real ^ 1; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 15; + neg_imag <<= 15; + + for (i = 0; i < opr_sz / 2; i += 2) { + float16 e0 = n[H2(i)]; + float16 e1 = m[H2(i + 1)] ^ neg_imag; + float16 e2 = n[H2(i + 1)]; + float16 e3 = m[H2(i)] ^ neg_real; + + d[H2(i)] = float16_add(e0, e1, fpst); + d[H2(i + 1)] = float16_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float32 *d = vd; + float32 *n = vn; + float32 *m = vm; + float_status *fpst = vfpst; + uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = neg_real ^ 1; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 31; + neg_imag <<= 31; + + for (i = 0; i < opr_sz / 4; i += 2) { + float32 e0 = n[H4(i)]; + float32 e1 = m[H4(i + 1)] ^ neg_imag; + float32 e2 = n[H4(i + 1)]; + float32 e3 = m[H4(i)] ^ neg_real; + + d[H4(i)] = float32_add(e0, e1, fpst); + d[H4(i + 1)] = float32_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float64 *d = vd; + float64 *n = vn; + float64 *m = vm; + float_status *fpst = vfpst; + uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag = neg_real ^ 1; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 63; + neg_imag <<= 63; + + for (i = 0; i < opr_sz / 8; i += 2) { + float64 e0 = n[i]; + float64 e1 = m[i + 1] ^ neg_imag; + float64 e2 = n[i + 1]; + float64 e3 = m[i] ^ neg_real; + + d[i] = float64_add(e0, e1, fpst); + d[i + 1] = float64_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} From patchwork Wed Feb 28 19:31:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130061 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp135430lja; Wed, 28 Feb 2018 11:40:50 -0800 (PST) X-Google-Smtp-Source: AG47ELvbOfbbG3lgLinDAmlEia9cvxPBe2yJ5lvMPWolMXDmKd1vtQI4SxFsrwJLJiNilYQNkvMi X-Received: by 2002:a25:688:: with SMTP id 130-v6mr12871957ybg.387.1519846850385; Wed, 28 Feb 2018 11:40:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846850; cv=none; d=google.com; s=arc-20160816; b=g7dBuF2Kg5EdGYDXAMIXMvaplo+xfo+cqEBzyKrOZNgF0PZkanEZaP3J0klvkHb60Z mVaLQyLewJoaFZEZegNjIhN7PFnj+BYq/xthEDq2dAgSmrcEUSCVCq2Dt1sJd3FK2yar ZEFQ+JOEMETPZtdvEmOc5UXr3oJU1xL5qQUASUrH9+h4YbrNz6xBeAl1Ygm7YRGYoGjg o0EQ+2emdft5ZrU0uMonR4oMz0PCl5ZlpMhFB+JeYedoCyeUuK7d+l5Q1fNCTuz5nNTM ZpZKAod51SgrIv8s9E9UEGe0uGj4vW6mkTCYdWcV20Zuyy3Wa+xC/andV7jD3TAUAdqf SDuA== ARC-Message-Signature: i=1; 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:21 -0800 Message-Id: <20180228193125.20577-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.h | 11 ++++ target/arm/translate-a64.c | 94 +++++++++++++++++++++++++--- target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+), 8 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.h b/target/arm/helper.h index 1e2d7025de..0d2094f2be 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -585,6 +585,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index efed4fd9d2..31ff0479e6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10842,6 +10842,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = ARM_FEATURE_V8_RDM; break; + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ if (size == 0 @@ -10891,6 +10895,29 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } return; + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ + rot = extract32(opcode, 0, 2); + switch (size) { + case 1: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot, + gen_helper_gvec_fcmlah); + break; + case 2: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, + gen_helper_gvec_fcmlas); + break; + case 3: + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot, + gen_helper_gvec_fcmlad); + break; + default: + g_assert_not_reached(); + } + return; + case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ rot = extract32(opcode, 1, 1); @@ -11993,7 +12020,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); bool is_long = false; - bool is_fp = false; + int is_fp = 0; bool is_fp16 = false; int index; TCGv_ptr fpst; @@ -12031,7 +12058,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x05: /* FMLS */ case 0x09: /* FMUL */ case 0x19: /* FMULX */ - is_fp = true; + is_fp = 1; break; case 0x1d: /* SQRDMLAH */ case 0x1f: /* SQRDMLSH */ @@ -12040,20 +12067,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) return; } break; + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { + unallocated_encoding(s); + return; + } + is_fp = 2; + break; default: unallocated_encoding(s); return; } - if (is_fp) { + switch (is_fp) { + case 1: /* normal fp */ /* convert insn encoded size to TCGMemOp size */ switch (size) { case 0: /* half-precision */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { - unallocated_encoding(s); - return; - } size = MO_16; + is_fp16 = true; break; case MO_32: /* single precision */ case MO_64: /* double precision */ @@ -12062,13 +12097,39 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - } else { + break; + + case 2: /* complex fp */ + /* Each indexable element is a complex pair. */ + size <<= 1; + switch (size) { + case MO_32: + if (h && !is_q) { + unallocated_encoding(s); + return; + } + is_fp16 = true; + break; + case MO_64: + break; + default: + unallocated_encoding(s); + return; + } + break; + + default: /* integer */ switch (size) { case MO_8: case MO_64: unallocated_encoding(s); return; } + break; + } + if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; } /* Given TCGMemOp size, adjust register and indexing. */ @@ -12102,6 +12163,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) fpst = NULL; } + switch (16 * u + opcode) { + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_reg_offset(s, rm, index, size), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), + extract32(insn, 13, 2), /* rot */ + size == MO_64 + ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); + tcg_temp_free_ptr(fpst); + return; + } + if (size == 3) { TCGv_i64 tcg_idx = tcg_temp_new_i64(); int pass; diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index a868ca6aac..d81eb7730d 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -278,3 +278,152 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float16 *d = vd; + float16 *n = vn; + float16 *m = vm; + float_status *fpst = vfpst; + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real = flip ^ neg_imag; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 15; + neg_imag <<= 15; + + for (i = 0; i < opr_sz / 2; i += 2) { + float16 e1 = n[H2(i + flip)]; + float16 e2 = m[H2(i + flip)] ^ neg_real; + float16 e3 = e1; + float16 e4 = m[H2(i + 1 - flip)] ^ neg_imag; + + d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst); + d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float16 *d = vd; + float16 *n = vn; + float16 *m = vm; + float_status *fpst = vfpst; + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real = flip ^ neg_imag; + uintptr_t i; + float16 e2 = m[H2(flip)]; + float16 e4 = m[H2(1 - flip)]; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 15; + neg_imag <<= 15; + e2 ^= neg_real; + e4 ^= neg_imag; + + for (i = 0; i < opr_sz / 2; i += 2) { + float16 e1 = n[H2(i + flip)]; + float16 e3 = e1; + + d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst); + d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float32 *d = vd; + float32 *n = vn; + float32 *m = vm; + float_status *fpst = vfpst; + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real = flip ^ neg_imag; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 31; + neg_imag <<= 31; + + for (i = 0; i < opr_sz / 4; i += 2) { + float32 e1 = n[H4(i + flip)]; + float32 e2 = m[H4(i + flip)] ^ neg_real; + float32 e3 = e1; + float32 e4 = m[H4(i + 1 - flip)] ^ neg_imag; + + d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst); + d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float32 *d = vd; + float32 *n = vn; + float32 *m = vm; + float_status *fpst = vfpst; + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real = flip ^ neg_imag; + uintptr_t i; + float32 e2 = m[H4(flip)]; + float32 e4 = m[H4(1 - flip)]; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 31; + neg_imag <<= 31; + e2 ^= neg_real; + e4 ^= neg_imag; + + for (i = 0; i < opr_sz / 4; i += 2) { + float32 e1 = n[H4(i + flip)]; + float32 e3 = e1; + + d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst); + d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz = simd_oprsz(desc); + float64 *d = vd; + float64 *n = vn; + float64 *m = vm; + float_status *fpst = vfpst; + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint64_t neg_real = flip ^ neg_imag; + uintptr_t i; + + /* Shift boolean to the sign bit so we can xor to negate. */ + neg_real <<= 63; + neg_imag <<= 63; + + for (i = 0; i < opr_sz / 8; i += 2) { + float64 e1 = n[i + flip]; + float64 e2 = m[i + flip] ^ neg_real; + float64 e3 = e1; + float64 e4 = m[i + 1 - flip] ^ neg_imag; + + d[i] = float64_muladd(e1, e2, d[i], 0, fpst); + d[i + 1] = float64_muladd(e3, e4, d[i + 1], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} From patchwork Wed Feb 28 19:31:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130058 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp133776lja; Wed, 28 Feb 2018 11:38:51 -0800 (PST) X-Google-Smtp-Source: AG47ELs0Yso7Wx3yS4GJr3uWiP0uRIrgg477S4R7OWd0nyTRWm8U2LzA4Fqs4eMC28j8nIxbdu7J X-Received: by 2002:a25:1f86:: with SMTP id f128-v6mr12648124ybf.255.1519846731587; Wed, 28 Feb 2018 11:38:51 -0800 (PST) ARC-Seal: i=1; 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:22 -0800 Message-Id: <20180228193125.20577-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 9169b6b367..45513c9d86 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7680,6 +7680,68 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 0; } +/* Advanced SIMD three registers of the same length extension. + * 31 25 23 22 20 16 12 11 10 9 8 3 0 + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ + */ +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) +{ + gen_helper_gvec_3_ptr *fn_gvec_ptr; + int rd, rn, rm, rot, size, opr_sz; + TCGv_ptr fpst; + bool q; + + q = extract32(insn, 6, 1); + VFP_DREG_D(rd, insn); + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rd | rn | rm) & q) { + return 1; + } + + if ((insn & 0xfe200f10) == 0xfc200800) { + /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ + size = extract32(insn, 20, 1); + rot = extract32(insn, 23, 2); + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + return 1; + } + fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; + } else if ((insn & 0xfea00f10) == 0xfc800800) { + /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ + size = extract32(insn, 20, 1); + rot = extract32(insn, 24, 1); + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + return 1; + } + fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; + } else { + return 1; + } + + if (s->fp_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + return 0; + } + if (!s->vfp_enabled) { + return 1; + } + + opr_sz = (1 + q) * 8; + fpst = get_fpstatus_ptr(1); + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), fpst, + opr_sz, opr_sz, rot, fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + return 0; +} + static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; @@ -8424,6 +8486,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } } + } else if ((insn & 0x0e000a00) == 0x0c000800 + && arm_dc_feature(s, ARM_FEATURE_V8)) { + if (disas_neon_insn_3same_ext(s, insn)) { + goto illegal_op; + } + return; } else if ((insn & 0x0fe00000) == 0x0c400000) { /* Coprocessor double register transfer. */ ARCH(5TE); From patchwork Wed Feb 28 19:31:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130066 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp141421lja; Wed, 28 Feb 2018 11:47:46 -0800 (PST) X-Google-Smtp-Source: AG47ELu+Cx8Z9rnOoT8Q9aUN2Z0zmx64Ee+xT8d810mzgV3YntIV1UxG55D8skNcFdPw53Z0moIP X-Received: by 2002:a25:9185:: with SMTP id w5-v6mr12924018ybl.352.1519847266397; Wed, 28 Feb 2018 11:47:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519847266; cv=none; d=google.com; s=arc-20160816; b=oTSryETTc+2+4Vyw/Ayzgerq2nH0yVlgehGEhQREwhogwrjkmlpFgfTmyhYxjqQmQs stpgPlw0UXvdh1OmKW+iEayF77lIuOnFIQhr1jI/fNtuPNHEDOGcSOCA268HI4tcOLnU 9yfeTJxDFlMJrSmPYQ/sPGXyLxvm7hLbkXdCnrMv33QFijABO00/3K9bcDK6pV6pfu75 YQT8oSXvc5JW+AWNvf3bQQmubdUW6JzV+xZUFU6IAZZERd1icbcE/iQEnaqXJvRPZxjm uCRU+JGTgSQnysoHc4rA+wBMLfWCDHjkM+YJfK2vJPrxYZOJbAdtiidfExpD8jB+x82o 1hSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MR0QyCTB5IcqskwTEuIEWG45RpBZgoQ7B3ACJOcXyLw=; b=q9guZe6dHvw5NumJ8XaWwlykbZW7y3o4+AXvAjNHcwWxdS0WBp3rquCLvWW6CyoCz1 GfhKEghemfA5mBQNz0QcRTkpnaF0b5bTLtIqTCL/cnmfwlIFlcP9Gd5RT2lTGVSOfo2X 9rxFr8h45SQ+EwmrrsUdSfZozoBHfGysPEzhISySxwmKZirntfFlm0jVw8/EY636nkuY Lbh8h30BBaE9D8WopTNzoXeD3w/4ZEgeeFmZpCOz4Yw37u/zqsbDXfKmns8ZlXGzrFxm sejFLcVbA2/vhlTzRV6+R9pL2kjrOQQbaDBzTtiZ0o1XBtHyy2C8gN/XRO1wQUqNL89a 8GSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=arH32oIb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:23 -0800 Message-Id: <20180228193125.20577-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 45513c9d86..3ad8b4031c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7742,6 +7742,61 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) return 0; } +/* Advanced SIMD two registers and a scalar extension. + * 31 24 23 22 20 16 12 11 10 9 8 3 0 + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ + * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | + * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ + * + */ + +static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) +{ + int rd, rn, rm, rot, size, opr_sz; + TCGv_ptr fpst; + bool q; + + q = extract32(insn, 6, 1); + VFP_DREG_D(rd, insn); + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rd | rn) & q) { + return 1; + } + + if ((insn & 0xff000f10) == 0xfe000800) { + /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ + rot = extract32(insn, 20, 2); + size = extract32(insn, 23, 1); + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) + || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + return 1; + } + } else { + return 1; + } + + if (s->fp_excp_el) { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + return 0; + } + if (!s->vfp_enabled) { + return 1; + } + + opr_sz = (1 + q) * 8; + fpst = get_fpstatus_ptr(1); + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), + vfp_reg_offset(1, rn), + vfp_reg_offset(1, rm), fpst, + opr_sz, opr_sz, rot, + size ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); + tcg_temp_free_ptr(fpst); + return 0; +} + static int disas_coproc_insn(DisasContext *s, uint32_t insn) { int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; @@ -8492,6 +8547,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } return; + } else if ((insn & 0x0f000a00) == 0x0e000800 + && arm_dc_feature(s, ARM_FEATURE_V8)) { + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { + goto illegal_op; + } + return; } else if ((insn & 0x0fe00000) == 0x0c400000) { /* Coprocessor double register transfer. */ ARCH(5TE); From patchwork Wed Feb 28 19:31:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130063 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp137447lja; Wed, 28 Feb 2018 11:43:12 -0800 (PST) X-Google-Smtp-Source: AG47ELukRLJJwduJxnlp4V9YJNprhyJcaWQ69+s9b+0yQejFuUUtjkOMk8vjZya0tDJgNMfd0WjQ X-Received: by 10.129.1.21 with SMTP id 21mr12820925ywb.286.1519846992693; Wed, 28 Feb 2018 11:43:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519846992; cv=none; d=google.com; s=arc-20160816; b=IB9P/FusVgkB2P1vMDX3CSToT2YqHEIanlxOOJcfpDGZ5/qMJvHnFuq62pN6S7Ui2K Byv/fU2AStGR4Q+ic/iLhGvvjfziLlthhD+YommgeIxgxB/1+8ktSfwt3Eb8X7eK4C10 1f/xyZmpGfq+DatKyKSHyeomDp37Hw+k2EP6XHFooMrKiyBzxU/EaIOPTyAJiF/q3r7e 3nrJyI7Tf91PoYY80WFyszt3OAZZ5yjYVQQrx65kFMB6hcsd8wWU+wUveni1+BK91pgd KbaqkX+zl/gmGD4HQgf9Ddl1R9i7b5NWjygDB08P1uH3uHFcQuXh37UULGFTebdpayZw lS1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=G8wDRM28kIfKn4QAnTQXP7Nr7iSo1v6usJSUJDiitjY=; b=y3jJQVryZSSnQw1EPyoMrcditTQDa93lkMum6jjX7yuptmaTfTye1chmaj5MfJumBk 20ch0T00rZFs/aL5PgThK68qnfK1d/uyiEsjOtIoRiCjQqlicwfc5kryOWEN8eZojerM SNRSTfvv52ojmbKd3NXwtTBiWFcqtVnr2hGmrwBWkJ1m2NqzZ0foss/db/1v0RItmoQS id3I6HyDl6BP3plgjmhIxepemBqvRzDMkiCG9b/gYEinTZS9/E1kve5867cf5Yp4+Pr9 g7HcSpciiuBHjmWoF3Umn+q5rd/Rk8VpzWfAE9VUrQa7lOw7EgatGkc1DeOstZnNcxZj AnLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ky/BiErS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:24 -0800 Message-Id: <20180228193125.20577-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Happily, the bits are in the same places compared to a32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 3ad8b4031c..ba6ab7d287 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) default_exception_el(s)); break; } - if (((insn >> 24) & 3) == 3) { + if ((insn & 0xfe000a00) == 0xfc000800 + && arm_dc_feature(s, ARM_FEATURE_V8)) { + /* The Thumb2 and ARM encodings are identical. */ + if (disas_neon_insn_3same_ext(s, insn)) { + goto illegal_op; + } + } else if ((insn & 0xff000a00) == 0xfe000800 + && arm_dc_feature(s, ARM_FEATURE_V8)) { + /* The Thumb2 and ARM encodings are identical. */ + if (disas_neon_insn_2reg_scalar_ext(s, insn)) { + goto illegal_op; + } + } else if (((insn >> 24) & 3) == 3) { /* Translate into the equivalent ARM encoding. */ insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); if (disas_neon_data_insn(s, insn)) { From patchwork Wed Feb 28 19:31:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130065 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp137725lja; Wed, 28 Feb 2018 11:43:35 -0800 (PST) X-Google-Smtp-Source: AG47ELsBOhNRWxotACszBAKPIkNmd/624FwHUNgVjfp/SACLNfHajtPp+/SJNPJafd6Cb1qHY0g+ X-Received: by 10.129.197.73 with SMTP id o9mr9965081ywj.66.1519847015215; Wed, 28 Feb 2018 11:43:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519847015; cv=none; d=google.com; s=arc-20160816; b=ppMkPDbnSieKxPCASlAgoTI4ymwCSZqeEiUSchGQUciRlKjScnnG4RNeAhdPpVyp6D DoeNQGJaeuhF/9umH7tzn085bqVNATw7/7Xv22mveipQElLvdJy6grzx4iQ1Zq3DOY+J l7YtY59Vxoq7QQFnf/EtDmrJYD4tKIU67W9+ZtmizFW1Su5U3zPx20tunq318Y0EQsPT fOwUwTfMVgbdKUzIpa4k3InuEFkZeXZJu01G7pyM6oeGUyaiE3Q4i82Lb0RWWEuI5Xat WSW28mFwhrh2pCJSFV8v+L3Fnb/qdTh2v7qGFoUSu79O2scU3hhCVno1N+dXEdzcmwGZ BLig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jJ6CE3xc0WzrR9rdC8JrfrZyPps0vJLzi6MVauEfbYg=; b=yz8U5vKbl3AET+vTeVcQzPDLoHeNnJv3gCraeC9w8+S46uc0K96ZOUxURaqxmC0+3C uLZQwEW19lBS29img9gwAkAeAVHSVCdXF1wNVn72P3Uyraxj6ki4eJvMDYs60IFKyhps pofwLbzpBifomEUwICIZ7/R1ZhPTcpMLrTP/iAuBVHK88h0SyPxT7DCYXZGIdObtF9Bt 5XVKuaWORoluyyl+jeS4JifyQ8Q4kq6hebW3SqW7wR3zwU/sfrqBbohmoPUogSaUuNqj AkQZ/GJT4QaavXMhmdtkTucllWH0TJ/XkOGLZlO3uMmk8qr87iFnycyJ+iuWctLnCvJ6 2sTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KIh/WMeU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:25 -0800 Message-Id: <20180228193125.20577-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable it for the "any" CPU used by *-linux-user. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ca5fb1162a..452bc32f10 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1651,6 +1651,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->midr = 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7246866e7d..4228713b19 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -232,6 +232,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_RDM); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }