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Fixes: b9083ea5e084 ("net/dpaa: further push mode optimizations") Cc: stable@dpdk.org Signed-off-by: Hemant Agrawal --- drivers/bus/dpaa/base/qbman/qman.c | 5 +++-- drivers/bus/dpaa/base/qbman/qman_driver.c | 5 +---- 2 files changed, 4 insertions(+), 6 deletions(-) -- 2.7.4 Acked-by: Shreyansh Jain diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c index 2b97671..2810fdd 100644 --- a/drivers/bus/dpaa/base/qbman/qman.c +++ b/drivers/bus/dpaa/base/qbman/qman.c @@ -1087,7 +1087,7 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit, shadow[rx_number]->fd.opaque = be32_to_cpu(dq[rx_number]->fd.opaque); #else - shadow = dq; + shadow[rx_number] = dq[rx_number]; #endif /* SDQCR: context_b points to the FQ */ @@ -1095,7 +1095,8 @@ unsigned int qman_portal_poll_rx(unsigned int poll_limit, fq[rx_number] = qman_fq_lookup_table[be32_to_cpu( dq[rx_number]->contextB)]; #else - fq[rx_number] = (void *)(uintptr_t)be32_to_cpu(dq->contextB); + fq[rx_number] = (void *)be32_to_cpu( + dq[rx_number]->contextB); #endif fq[rx_number]->cb.dqrr_prepare(shadow[rx_number], &bufs[rx_number]); diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c index 7cfa8ee..66838d2 100644 --- a/drivers/bus/dpaa/base/qbman/qman_driver.c +++ b/drivers/bus/dpaa/base/qbman/qman_driver.c @@ -246,7 +246,6 @@ int fsl_qman_portal_destroy(struct qman_portal *qp) int qman_global_init(void) { const struct device_node *dt_node; - int ret = 0; size_t lenp; const u32 *chanid; static int ccsr_map_fd; @@ -352,9 +351,7 @@ int qman_global_init(void) qman_clk = be32_to_cpu(*clk); #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP - ret = qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX); - if (ret) - return ret; + return qman_setup_fq_lookup_table(CONFIG_FSL_QMAN_FQ_LOOKUP_MAX); #endif return 0; } From patchwork Thu Mar 1 07:33:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130122 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2481945edc; Wed, 28 Feb 2018 23:35:36 -0800 (PST) X-Google-Smtp-Source: AG47ELvvT5FzXvjRP2XTExB/EpIrqdaUfRJirFME8NlsxKPf9sPez6aY3+UPovn3ZiLFhsTsJZE0 X-Received: by 10.223.176.77 with SMTP id g13mr809587wra.21.1519889736566; Wed, 28 Feb 2018 23:35:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519889736; cv=none; d=google.com; s=arc-20160816; b=RMVxCraSFw3dJqN/O/K694TrlBegJldb3UiIzCoWCP0fN0jXpWm34EP540VooWiD6b fWzDJaYlCCobpvpTWOqNRd7ElnrorMY7oLXLY0+Pajgge9PxOzWYYspZW8BfAXef+U0c hv2BRaBGUgA+i1cNZ2Q4Vg52kPAQWbnEky5B5Nn6YxdwGKgls4nz1kGPkVz5FJJs8lZL XZlD4+0ng4dme/Qe018y1KTiyNnSzLYLsXqfnF7wudxeKTkeiqrEBadC5NBsPhiyWOBq aa9GQtc5uVnEF/x/8GQUmHs0NS/16OacC2R8ylOXU+f0mSLZ3oCGVVeTe0zGtrKqPWvz iv2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature:arc-authentication-results; bh=ww0NlpCVN/kzUqKdV7D23a9TIVnTI5AYGEJOZZotE3I=; b=Jl5bEw5otJEI0lpehSN0SKchTMJs/E12kqH2BvfLj+RkXsrzBZkSmBTid5iTWCs3al AWBb9BFFD6P4u0nvCw0km333nm1TRyMe+myKAi4ILUjHU2k7cEjnGmKBqw7NqV4vyMtO oSWgU4xF3FedqZ6ghkUVXzei8JhtDjVKFhxGxcFiuwCIsuA37FkqylQAHlullou/94df CkTmLdTXHDiBnfgmGg5eEKp0MqAwmJm2QJFokKdCasY+2mAzIoC9E9NTjaIz8VPudvWV iwxRlhD+CtrxSykFF0ix0PSQ1AwBHdAFikJHM2amCjlJHmiF45r4sTzwJ3CJAWv3Xg/m 5XVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=YeoBzkdr; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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Signed-off-by: Hemant Agrawal --- drivers/bus/dpaa/base/fman/fman.c | 2 +- drivers/bus/dpaa/base/qbman/bman_driver.c | 2 +- drivers/bus/dpaa/dpaa_bus.c | 3 +-- drivers/crypto/dpaa_sec/dpaa_sec.c | 30 +++++++++++++++--------------- drivers/mempool/dpaa/dpaa_mempool.c | 10 +++++----- drivers/mempool/dpaa/dpaa_mempool.h | 2 +- drivers/net/dpaa/dpaa_rxtx.c | 17 ++++++++--------- 7 files changed, 32 insertions(+), 34 deletions(-) -- 2.7.4 diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c index bda62e0..e6fd5f3 100644 --- a/drivers/bus/dpaa/base/fman/fman.c +++ b/drivers/bus/dpaa/base/fman/fman.c @@ -300,7 +300,7 @@ fman_if_init(const struct device_node *dpa_node) _errno = fman_get_mac_index(regs_addr_host, &__if->__if.mac_idx); if (_errno) { - FMAN_ERR(-EINVAL, "Invalid register address: %lu", + FMAN_ERR(-EINVAL, "Invalid register address: %" PRIx64, regs_addr_host); goto err; } diff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c index a1ef392..1381da3 100644 --- a/drivers/bus/dpaa/base/qbman/bman_driver.c +++ b/drivers/bus/dpaa/base/qbman/bman_driver.c @@ -161,7 +161,7 @@ int bman_init_ccsr(const struct device_node *node) PROT_WRITE, MAP_SHARED, ccsr_map_fd, phys_addr); if (bman_ccsr_map == MAP_FAILED) { pr_err("Can not map BMan CCSR base Bman: " - "0x%x Phys: 0x%lx size 0x%lx", + "0x%x Phys: 0x%" PRIx64 " size 0x%" PRIu64, *bman_addr, phys_addr, regs_size); return -EINVAL; } diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c index f2bb3b1..3535da5 100644 --- a/drivers/bus/dpaa/dpaa_bus.c +++ b/drivers/bus/dpaa/dpaa_bus.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -235,7 +234,7 @@ int rte_dpaa_portal_init(void *arg) BUS_INIT_FUNC_TRACE(); - if ((uint64_t)arg == 1 || cpu == LCORE_ID_ANY) + if ((size_t)arg == 1 || cpu == LCORE_ID_ANY) cpu = rte_get_master_lcore(); /* if the core id is not supported */ else diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c index 18681cf..c5191ce 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.c +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c @@ -84,7 +84,7 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses) dcbz_64(&ctx->job.sg[SG_CACHELINE_3]); ctx->ctx_pool = ses->ctx_pool; - ctx->vtop_offset = (uint64_t) ctx + ctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx); return ctx; @@ -97,7 +97,7 @@ dpaa_mem_vtop(void *vaddr) uint64_t vaddr_64, paddr; int i; - vaddr_64 = (uint64_t)vaddr; + vaddr_64 = (size_t)vaddr; for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) { if (vaddr_64 >= memseg[i].addr_64 && vaddr_64 < memseg[i].addr_64 + memseg[i].len) { @@ -107,14 +107,14 @@ dpaa_mem_vtop(void *vaddr) return (rte_iova_t)paddr; } } - return (rte_iova_t)(NULL); + return (size_t)NULL; } /* virtual address conversin when mempool support is available for ctx */ static inline phys_addr_t dpaa_mem_vtop_ctx(struct dpaa_sec_op_ctx *ctx, void *vaddr) { - return (uint64_t)vaddr - ctx->vtop_offset; + return (size_t)vaddr - ctx->vtop_offset; } static inline void * @@ -125,8 +125,8 @@ dpaa_mem_ptov(rte_iova_t paddr) for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) { if (paddr >= memseg[i].iova && - (char *)paddr < (char *)memseg[i].iova + memseg[i].len) - return (void *)(memseg[i].addr_64 + + paddr < memseg[i].iova + memseg[i].len) + return (void *)(size_t)(memseg[i].addr_64 + (paddr - memseg[i].iova)); } return NULL; @@ -406,7 +406,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) return -ENOTSUP; } - alginfo_c.key = (uint64_t)ses->cipher_key.data; + alginfo_c.key = (size_t)ses->cipher_key.data; alginfo_c.keylen = ses->cipher_key.length; alginfo_c.key_enc_flags = 0; alginfo_c.key_type = RTA_DATA_IMM; @@ -424,7 +424,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) return -ENOTSUP; } - alginfo_a.key = (uint64_t)ses->auth_key.data; + alginfo_a.key = (size_t)ses->auth_key.data; alginfo_a.keylen = ses->auth_key.length; alginfo_a.key_enc_flags = 0; alginfo_a.key_type = RTA_DATA_IMM; @@ -439,7 +439,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) PMD_TX_LOG(ERR, "not supported aead alg\n"); return -ENOTSUP; } - alginfo.key = (uint64_t)ses->aead_key.data; + alginfo.key = (size_t)ses->aead_key.data; alginfo.keylen = ses->aead_key.length; alginfo.key_enc_flags = 0; alginfo.key_type = RTA_DATA_IMM; @@ -463,7 +463,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) return -ENOTSUP; } - alginfo_c.key = (uint64_t)ses->cipher_key.data; + alginfo_c.key = (size_t)ses->cipher_key.data; alginfo_c.keylen = ses->cipher_key.length; alginfo_c.key_enc_flags = 0; alginfo_c.key_type = RTA_DATA_IMM; @@ -474,7 +474,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) return -ENOTSUP; } - alginfo_a.key = (uint64_t)ses->auth_key.data; + alginfo_a.key = (size_t)ses->auth_key.data; alginfo_a.keylen = ses->auth_key.length; alginfo_a.key_enc_flags = 0; alginfo_a.key_type = RTA_DATA_IMM; @@ -493,15 +493,15 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) if (cdb->sh_desc[2] & 1) alginfo_c.key_type = RTA_DATA_IMM; else { - alginfo_c.key = (uint64_t)dpaa_mem_vtop( - (void *)alginfo_c.key); + alginfo_c.key = (size_t)dpaa_mem_vtop( + (void *)(size_t)alginfo_c.key); alginfo_c.key_type = RTA_DATA_PTR; } if (cdb->sh_desc[2] & (1<<1)) alginfo_a.key_type = RTA_DATA_IMM; else { - alginfo_a.key = (uint64_t)dpaa_mem_vtop( - (void *)alginfo_a.key); + alginfo_a.key = (size_t)dpaa_mem_vtop( + (void *)(size_t)alginfo_a.key); alginfo_a.key_type = RTA_DATA_PTR; } cdb->sh_desc[0] = 0; diff --git a/drivers/mempool/dpaa/dpaa_mempool.c b/drivers/mempool/dpaa/dpaa_mempool.c index fb3b6ba..7b82f4b 100644 --- a/drivers/mempool/dpaa/dpaa_mempool.c +++ b/drivers/mempool/dpaa/dpaa_mempool.c @@ -115,7 +115,8 @@ dpaa_buf_free(struct dpaa_bp_info *bp_info, uint64_t addr) struct bm_buffer buf; int ret; - DPAA_MEMPOOL_DEBUG("Free 0x%lx to bpid: %d", addr, bp_info->bpid); + DPAA_MEMPOOL_DEBUG("Free 0x%" PRIx64 " to bpid: %d", + addr, bp_info->bpid); bm_buffer_set64(&buf, addr); retry: @@ -154,8 +155,7 @@ dpaa_mbuf_free_bulk(struct rte_mempool *pool, if (unlikely(!bp_info->ptov_off)) { /* buffers are from single mem segment */ if (bp_info->flags & DPAA_MPOOL_SINGLE_SEGMENT) { - bp_info->ptov_off - = (uint64_t)obj_table[i] - phy; + bp_info->ptov_off = (size_t)obj_table[i] - phy; rte_dpaa_bpid_info[bp_info->bpid].ptov_off = bp_info->ptov_off; } @@ -282,8 +282,8 @@ dpaa_register_memory_area(const struct rte_mempool *mp, bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size; - DPAA_MEMPOOL_DEBUG("Req size %lu vs Available %u\n", - len, total_elt_sz * mp->size); + DPAA_MEMPOOL_DEBUG("Req size %" PRIx64 " vs Available %u\n", + (uint64_t)len, total_elt_sz * mp->size); /* Detect pool area has sufficient space for elements in this memzone */ if (len >= total_elt_sz * mp->size) diff --git a/drivers/mempool/dpaa/dpaa_mempool.h b/drivers/mempool/dpaa/dpaa_mempool.h index 9435dd2..092f326 100644 --- a/drivers/mempool/dpaa/dpaa_mempool.h +++ b/drivers/mempool/dpaa/dpaa_mempool.h @@ -46,7 +46,7 @@ static inline void * DPAA_MEMPOOL_PTOV(struct dpaa_bp_info *bp_info, uint64_t addr) { if (bp_info->ptov_off) - return ((void *)(addr + bp_info->ptov_off)); + return ((void *) (size_t)(addr + bp_info->ptov_off)); return rte_dpaa_mem_ptov(addr); } diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c index 0dea8e7..8d53137 100644 --- a/drivers/net/dpaa/dpaa_rxtx.c +++ b/drivers/net/dpaa/dpaa_rxtx.c @@ -90,11 +90,10 @@ static inline void dpaa_slow_parsing(struct rte_mbuf *m __rte_unused, /*TBD:XXX: to be implemented*/ } -static inline void dpaa_eth_packet_info(struct rte_mbuf *m, - uint64_t fd_virt_addr) +static inline void dpaa_eth_packet_info(struct rte_mbuf *m, void *fd_virt_addr) { struct annotations_t *annot = GET_ANNOTATIONS(fd_virt_addr); - uint64_t prs = *((uint64_t *)(&annot->parse)) & DPAA_PARSE_MASK; + uint64_t prs = *((uintptr_t *)(&annot->parse)) & DPAA_PARSE_MASK; DPAA_DP_LOG(DEBUG, " Parsing mbuf: %p with annotations: %p", m, annot); @@ -351,7 +350,7 @@ dpaa_eth_sg_to_mbuf(const struct qm_fd *fd, uint32_t ifid) prev_seg = cur_seg; } - dpaa_eth_packet_info(first_seg, (uint64_t)vaddr); + dpaa_eth_packet_info(first_seg, vaddr); rte_pktmbuf_free_seg(temp); return first_seg; @@ -394,7 +393,7 @@ dpaa_eth_fd_to_mbuf(const struct qm_fd *fd, uint32_t ifid) mbuf->ol_flags = 0; mbuf->next = NULL; rte_mbuf_refcnt_set(mbuf, 1); - dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr); + dpaa_eth_packet_info(mbuf, mbuf->buf_addr); return mbuf; } @@ -455,7 +454,7 @@ dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr, mbuf->ol_flags = 0; mbuf->next = NULL; rte_mbuf_refcnt_set(mbuf, 1); - dpaa_eth_packet_info(mbuf, (uint64_t)mbuf->buf_addr); + dpaa_eth_packet_info(mbuf, mbuf->buf_addr); } } @@ -593,7 +592,7 @@ uint16_t dpaa_eth_queue_rx(void *q, static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info) { int ret; - uint64_t buf = 0; + size_t buf = 0; struct bm_buffer bufs; ret = bman_acquire(bp_info->bp, &bufs, 1, 0); @@ -602,10 +601,10 @@ static void *dpaa_get_pktbuf(struct dpaa_bp_info *bp_info) return (void *)buf; } - DPAA_DP_LOG(DEBUG, "got buffer 0x%lx from pool %d", + DPAA_DP_LOG(DEBUG, "got buffer 0x%" PRIx64 " from pool %d", (uint64_t)bufs.addr, bufs.bpid); - buf = (uint64_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr) + buf = (size_t)DPAA_MEMPOOL_PTOV(bp_info, bufs.addr) - bp_info->meta_data_size; if (!buf) goto out; From patchwork Thu Mar 1 07:33:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130123 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2482195edc; Wed, 28 Feb 2018 23:35:55 -0800 (PST) X-Google-Smtp-Source: AG47ELuq3eh3NNuY47aGk8w7wGuAqhtBm2AEAcxVlZWbqU9IVyqqwoA9sGGzYOS3LsiiAWzeq4G+ X-Received: by 10.28.155.66 with SMTP id d63mr800127wme.144.1519889755110; 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Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/fslmc_vfio.c | 10 ++--- drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++++++--------- drivers/bus/fslmc/qbman/qbman_portal.c | 14 +++---- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 60 ++++++++++++++--------------- drivers/event/dpaa2/dpaa2_eventdev.c | 6 +-- drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 ++-- drivers/net/dpaa2/Makefile | 1 - drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +- drivers/net/dpaa2/dpaa2_ethdev.c | 6 +-- drivers/net/dpaa2/dpaa2_rxtx.c | 38 ++++++++---------- 12 files changed, 90 insertions(+), 98 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index 1241295..e840ad6 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -76,7 +76,7 @@ fslmc_get_container_group(int *groupid) if (!g_container) { container = getenv("DPRC"); if (container == NULL) { - RTE_LOG(WARNING, EAL, "DPAA2: DPRC not available\n"); + RTE_LOG(DEBUG, EAL, "DPAA2: DPRC not available\n"); return -EINVAL; } @@ -270,7 +270,7 @@ int rte_fslmc_vfio_dmamap(void) static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj) { - int64_t v_addr = (int64_t)MAP_FAILED; + intptr_t v_addr = (intptr_t)MAP_FAILED; int32_t ret, mc_fd; struct vfio_device_info d_info = { .argsz = sizeof(d_info) }; @@ -301,7 +301,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj) FSLMC_VFIO_LOG(DEBUG, "region offset = %llx , region size = %llx", reg_info.offset, reg_info.size); - v_addr = (uint64_t)mmap(NULL, reg_info.size, + v_addr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, mc_fd, reg_info.offset); @@ -469,7 +469,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev) static int fslmc_process_mcp(struct rte_dpaa2_device *dev) { - int64_t v_addr; + intptr_t v_addr; char *dev_name; struct fsl_mc_io dpmng = {0}; struct mc_version mc_ver_info = {0}; @@ -489,7 +489,7 @@ fslmc_process_mcp(struct rte_dpaa2_device *dev) } v_addr = vfio_map_mcp_obj(&vfio_group, dev_name); - if (v_addr == (int64_t)MAP_FAILED) { + if (v_addr == (intptr_t)MAP_FAILED) { FSLMC_VFIO_LOG(ERR, "Error mapping region (errno = %d)", errno); free(rte_mcp_ptr_list); diff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h index a3c3e79..ac91961 100644 --- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h +++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h @@ -27,7 +27,7 @@ #define le32_to_cpu rte_le_to_cpu_32 #define le16_to_cpu rte_le_to_cpu_16 -#define BITS_PER_LONG 64 +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index eefde15..9bbc219 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -427,7 +427,7 @@ dpaa2_create_dpio_device(int vdev_fd, } dpio_dev->ce_size = reg_info.size; - dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, + dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, vdev_fd, reg_info.offset); @@ -439,7 +439,7 @@ dpaa2_create_dpio_device(int vdev_fd, } dpio_dev->ci_size = reg_info.size; - dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, + dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, vdev_fd, reg_info.offset); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index d421dbf..3191ead 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -174,7 +174,7 @@ enum qbman_fd_format { }; /*Macros to define operations on FD*/ #define DPAA2_SET_FD_ADDR(fd, addr) do { \ - (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \ + (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \ (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \ } while (0) #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length) @@ -193,33 +193,32 @@ enum qbman_fd_format { #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16)) #define DPAA2_SET_FD_FLC(fd, addr) do { \ - (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \ + (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \ (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \ } while (0) #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len))) #define DPAA2_GET_FLE_ADDR(fle) \ (uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo) #define DPAA2_SET_FLE_ADDR(fle, addr) do { \ - (fle)->addr_lo = lower_32_bits((uint64_t)addr); \ - (fle)->addr_hi = upper_32_bits((uint64_t)addr); \ + (fle)->addr_lo = lower_32_bits((size_t)addr); \ + (fle)->addr_hi = upper_32_bits((uint64_t)addr); \ } while (0) #define DPAA2_GET_FLE_CTXT(fle) \ - (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \ - (fle)->reserved[0]) + ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0]) #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \ - (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \ - (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \ + (fle)->reserved[0] = lower_32_bits((size_t)addr); \ + (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \ } while (0) #define DPAA2_SET_FLE_OFFSET(fle, offset) \ ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16) -#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid) +#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid) #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff) -#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31) +#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31) #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000)) #define DPAA2_SET_FD_COMPOUND_FMT(fd) \ ((fd)->simple.bpid_offset |= (uint32_t)1 << 28) #define DPAA2_GET_FD_ADDR(fd) \ -((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo)) +((size_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo)) #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len) #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF)) @@ -231,7 +230,7 @@ enum qbman_fd_format { (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0) #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \ - ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size))) + ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size))) #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64) @@ -265,14 +264,14 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr) int i; if (dpaa2_virt_mode) - return (void *)paddr; + return (void *)(size_t)paddr; memseg = rte_eal_get_physmem_layout(); for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) { if (paddr >= memseg[i].iova && - (char *)paddr < (char *)memseg[i].iova + memseg[i].len) - return (void *)(memseg[i].addr_64 + paddr < memseg[i].iova + memseg[i].len) + return (void *)(size_t)(memseg[i].addr_64 + (paddr - memseg[i].iova)); } return NULL; @@ -295,7 +294,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) return memseg[i].iova + (vaddr - memseg[i].addr_64); } - return (phys_addr_t)(NULL); + return (size_t)(NULL); } /** @@ -311,18 +310,18 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) /** * macro to convert Virtual address to IOVA */ -#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr)) +#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr)) /** * macro to convert IOVA to Virtual address */ -#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova)) +#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova)) /** * macro to convert modify the memory containing IOVA to Virtual address */ #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \ - {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); } + {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); } #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index e221733..713ec96 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -553,10 +553,9 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, /* Flush all the cacheline without load/store in between */ eqcr_pi = s->eqcr.pi; - addr_cena = (uint64_t)s->sys.addr_cena; + addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((uint64_t *)(addr_cena + - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); eqcr_pi++; eqcr_pi &= 0xF; } @@ -620,10 +619,9 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, /* Flush all the cacheline without load/store in between */ eqcr_pi = s->eqcr.pi; - addr_cena = (uint64_t)s->sys.addr_cena; + addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((uint64_t *)(addr_cena + - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); eqcr_pi++; eqcr_pi &= 0xF; } @@ -690,7 +688,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, dma_addr_t storage_phys, int stash) { - d->pull.rsp_addr_virt = (uint64_t)storage; + d->pull.rsp_addr_virt = (size_t)storage; if (!storage) { d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT); @@ -749,7 +747,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) } d->pull.tok = s->sys.idx + 1; - s->vdq.storage = (void *)d->pull.rsp_addr_virt; + s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt; p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); memcpy(&p[1], &cl[1], 12); diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 9a790dd..a7f3b04 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -77,11 +77,11 @@ build_proto_fd(dpaa2_sec_session *sess, DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); DPAA2_SET_FD_OFFSET(fd, sym_op->m_src->data_off); DPAA2_SET_FD_LEN(fd, sym_op->m_src->pkt_len); - DPAA2_SET_FD_FLC(fd, ((uint64_t)flc)); + DPAA2_SET_FD_FLC(fd, (ptrdiff_t)flc); /* save physical address of mbuf */ op->sym->aead.digest.phys_addr = mbuf->buf_iova; - mbuf->buf_iova = (uint64_t)op; + mbuf->buf_iova = (size_t)op; return 0; } @@ -118,7 +118,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_SG_MEM_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -269,7 +269,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_POOL_BUF_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; if (likely(bpid < MAX_BPID)) { @@ -414,7 +414,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_SG_MEM_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -563,7 +563,7 @@ build_authenc_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_POOL_BUF_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; if (likely(bpid < MAX_BPID)) { @@ -692,7 +692,7 @@ static inline int build_auth_sg_fd( memset(fle, 0, FLE_SG_MEM_SIZE); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; sge = fle + 3; @@ -773,7 +773,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, * We can have a better approach to use the inline Mbuf */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; if (likely(bpid < MAX_BPID)) { @@ -865,7 +865,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, memset(fle, 0, FLE_SG_MEM_SIZE); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -987,7 +987,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, * We can have a better approach to use the inline Mbuf */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; @@ -1206,7 +1206,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id) DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)), rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size); - op = (struct rte_crypto_op *)mbuf->buf_iova; + op = (struct rte_crypto_op *)(size_t)mbuf->buf_iova; mbuf->buf_iova = op->sym->aead.digest.phys_addr; op->sym->aead.digest.phys_addr = 0L; @@ -1276,7 +1276,7 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id) /* free the fle memory */ if (likely(rte_pktmbuf_is_contiguous(src))) { - priv = (struct ctxt_priv *)DPAA2_GET_FLE_CTXT(fle - 1); + priv = (struct ctxt_priv *)(size_t)DPAA2_GET_FLE_CTXT(fle - 1); rte_mempool_put(priv->fle_pool, (void *)(fle-1)); } else rte_free((void *)(fle-1)); @@ -1455,7 +1455,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, dev->data->queue_pairs[qp_id] = qp; cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX; - cfg.user_ctx = (uint64_t)(&qp->rx_vq); + cfg.user_ctx = (size_t)(&qp->rx_vq); retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token, qp_id, &cfg); return retcode; @@ -1536,7 +1536,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, memcpy(session->cipher_key.data, xform->cipher.key.data, xform->cipher.key.length); - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -1595,10 +1595,10 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; @@ -1651,7 +1651,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, memcpy(session->auth_key.data, xform->auth.key.data, xform->auth.key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -1720,10 +1720,10 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -1786,7 +1786,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, session->aead_key.length = aead_xform->key.length; ctxt->auth_only_len = aead_xform->aad_length; - aeaddata.key = (uint64_t)session->aead_key.data; + aeaddata.key = (size_t)session->aead_key.data; aeaddata.keylen = session->aead_key.length; aeaddata.key_enc_flags = 0; aeaddata.key_type = RTA_DATA_IMM; @@ -1840,10 +1840,10 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, session->digest_length); flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -1928,7 +1928,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, memcpy(session->auth_key.data, auth_xform->key.data, auth_xform->key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -1988,7 +1988,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, auth_xform->algo); goto error_out; } - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -2066,10 +2066,10 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -2202,7 +2202,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, memcpy(session->auth_key.data, auth_xform->key.data, auth_xform->key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -2261,7 +2261,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, auth_xform->algo); goto out; } - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -2345,10 +2345,10 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, /* Enable the stashing control bit */ DPAA2_SET_FLC_RSC(flc); flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq) | 0x14); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); /* Set EWS bit i.e. enable write-safe */ diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index c3e6fbf..9bdc014 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -126,7 +126,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], goto send_partial; } rte_memcpy(ev_temp, event, sizeof(struct rte_event)); - DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp); + DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp); DPAA2_SET_FD_LEN((&fd_arr[loop]), sizeof(struct rte_event)); } @@ -258,7 +258,7 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[], qbman_swp_prefetch_dqrr_next(swp); fd = qbman_result_DQ_fd(dq); - rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq); + rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq); if (rxq) { rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]); } else { @@ -736,7 +736,7 @@ dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev, dpaa2_eventdev_process_atomic; for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) { - rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]); + rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->queue[i]); ret = dpci_set_rx_queue(&dpci_dev->dpci, CMD_PRI_LOW, dpci_dev->token, i, diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c index 2bd62e8..1a618ae 100644 --- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c +++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c @@ -242,7 +242,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, #endif struct qbman_swp *swp; uint16_t bpid; - uint64_t bufs[DPAA2_MBUF_MAX_ACQ_REL]; + size_t bufs[DPAA2_MBUF_MAX_ACQ_REL]; int i, ret; unsigned int n = 0; struct dpaa2_bp_info *bp_info; @@ -270,10 +270,10 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, * then the remainder. */ if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) { - ret = qbman_swp_acquire(swp, bpid, bufs, + ret = qbman_swp_acquire(swp, bpid, (void *)bufs, DPAA2_MBUF_MAX_ACQ_REL); } else { - ret = qbman_swp_acquire(swp, bpid, bufs, + ret = qbman_swp_acquire(swp, bpid, (void *)bufs, count - n); } /* In case of less than requested number of buffers available @@ -290,7 +290,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, } /* assigning mbuf from the acquired objects */ for (i = 0; (i < ret) && bufs[i]; i++) { - DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], uint64_t); + DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], size_t); obj_table[n] = (struct rte_mbuf *) (bufs[i] - bp_info->meta_data_size); PMD_TX_LOG(DEBUG, "Acquired %p address %p from BMAN", diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile index 5a93a0b..068e9d3 100644 --- a/drivers/net/dpaa2/Makefile +++ b/drivers/net/dpaa2/Makefile @@ -25,7 +25,6 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2 -CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2 CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal # versioning export map diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c index b93376d..4b60f56 100644 --- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c @@ -50,7 +50,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg); if (ret) { - PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported", + PMD_INIT_LOG(ERR, "given rss_hf (%" PRIx64 ") not supported", req_dist_set); rte_free(p_params); return ret; diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 09a11d6..fd5897e 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -445,7 +445,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, memset(&cfg, 0, sizeof(struct dpni_queue)); options = options | DPNI_QUEUE_OPT_USER_CTX; - cfg.user_context = (uint64_t)(dpaa2_q); + cfg.user_context = (size_t)(dpaa2_q); /*if ls2088 or rev2 device, enable the stashing */ @@ -560,7 +560,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, */ cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; cong_notif_cfg.message_ctx = 0; - cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn; + cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn; cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; cong_notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | @@ -1702,7 +1702,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, } options |= DPNI_QUEUE_OPT_USER_CTX; - cfg.user_context = (uint64_t)(dpaa2_ethq); + cfg.user_context = (size_t)(dpaa2_ethq); ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, dpaa2_ethq->tc_index, flow_id, options, &cfg); diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 183293c..f33b1fd 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -21,7 +21,6 @@ #include #include #include -#include #include "dpaa2_ethdev.h" #include "base/dpaa2_hw_dpni_annot.h" @@ -104,11 +103,9 @@ dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc) } static inline uint32_t __attribute__((hot)) -dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr) +dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation) { uint32_t pkt_type = RTE_PTYPE_UNKNOWN; - struct dpaa2_annot_hdr *annotation = - (struct dpaa2_annot_hdr *)hw_annot_addr; PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4); if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) { @@ -167,7 +164,7 @@ dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr) } static inline uint32_t __attribute__((hot)) -dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr) +dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr) { struct dpaa2_annot_hdr *annotation = (struct dpaa2_annot_hdr *)hw_annot_addr; @@ -207,25 +204,24 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr) break; } - return dpaa2_dev_rx_parse_slow(hw_annot_addr); + return dpaa2_dev_rx_parse_slow(annotation); } static inline struct rte_mbuf *__attribute__((hot)) eth_sg_fd_to_mbuf(const struct qbman_fd *fd) { struct qbman_sge *sgt, *sge; - dma_addr_t sg_addr; + size_t sg_addr, fd_addr; int i = 0; - uint64_t fd_addr; struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp; - fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); /* Get Scatter gather table address */ sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd)); sge = &sgt[i++]; - sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge)); + sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge)); /* First Scatter gather entry */ first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr, @@ -243,14 +239,14 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd) DPAA2_GET_FD_FRC_PARSE_SUM(fd)); else first_seg->packet_type = dpaa2_dev_rx_parse(first_seg, - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) - + DPAA2_FD_PTA_SIZE); + (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + + DPAA2_FD_PTA_SIZE)); rte_mbuf_refcnt_set(first_seg, 1); cur_seg = first_seg; while (!DPAA2_SG_IS_FINAL(sge)) { sge = &sgt[i++]; - sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR( + sg_addr = (size_t)DPAA2_IOVA_TO_VADDR( DPAA2_GET_FLE_ADDR(sge)); next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr, rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size); @@ -299,8 +295,8 @@ eth_fd_to_mbuf(const struct qbman_fd *fd) dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd)); else mbuf->packet_type = dpaa2_dev_rx_parse(mbuf, - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) - + DPAA2_FD_PTA_SIZE); + (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + + DPAA2_FD_PTA_SIZE)); PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d," "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n", @@ -340,7 +336,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf, DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg); /*Set Scatter gather table and Scatter gather entries*/ sgt = (struct qbman_sge *)( - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + DPAA2_GET_FD_OFFSET(fd)); for (i = 0; i < mbuf->nb_segs; i++) { @@ -523,8 +519,8 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } dq_storage = q_storage->active_dqs; - rte_prefetch0((void *)((uint64_t)(dq_storage))); - rte_prefetch0((void *)((uint64_t)(dq_storage + 1))); + rte_prefetch0((void *)(size_t)(dq_storage)); + rte_prefetch0((void *)(size_t)(dq_storage + 1)); /* Prepare next pull descriptor. This will give space for the * prefething done on DQRR entries @@ -554,7 +550,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) */ while (!qbman_check_new_result(dq_storage)) ; - rte_prefetch0((void *)((uint64_t)(dq_storage + 2))); + rte_prefetch0((void *)((size_t)(dq_storage + 2))); /* Check whether Last Pull command is Expired and * setting Condition for Loop termination */ @@ -569,7 +565,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) next_fd = qbman_result_DQ_fd(dq_storage + 1); /* Prefetch Annotation address for the parse results */ - rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd) + rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd) + DPAA2_FD_PTA_SIZE + 16)); if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)) @@ -726,7 +722,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) fd_arr[loop].simple.frc = 0; DPAA2_RESET_FD_CTRL((&fd_arr[loop])); - DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL); + DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL); if (likely(RTE_MBUF_DIRECT(*bufs))) { mp = (*bufs)->pool; /* Check the basic scenario and set From patchwork Thu Mar 1 07:33:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130124 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2482387edc; Wed, 28 Feb 2018 23:36:12 -0800 (PST) X-Google-Smtp-Source: AG47ELuatF1+Q1Y7Tk1AX3PG4J6aGXKfljjJg5oYic5XBt42TJTYJxot9en2ds47c2lLzG4CzK97 X-Received: by 10.223.184.88 with SMTP id u24mr727812wrf.3.1519889772176; Wed, 28 Feb 2018 23:36:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519889772; cv=none; d=google.com; s=arc-20160816; b=M+ZI0DMtEr9eiEPQLzPmRqWdLai8zMEvZDiRYPh4t1VAWoHo5g7fQzzgbBASzwjaaW j2vxpFG9QPnVqoLanRb6EIH5Qykku+p36hRBprWJ7Z3EKi1YjPS0VoUyUfKy1egRR7sB Efjx4Zy9gdQjGyRU5ojuU095NG110KVVGjLrFy2vWiNgSAGt3WfBS+HGxa61t8onSrWV xXkTjWw4nhrjEIZZrYLB5X0HyCDUFxr4R3K8Z+rGew+iu6608k5YbSyzqfb+RtOcx0Si UTLyY/+l68lWwygJQGMHb7Oa4f96PiE7atyL/7+9kJbehRcjroTP2B/x9l6EWXKozWlJ ggrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature:arc-authentication-results; bh=R3kl7+RrA6nHHRVWDDkrvpFcgPguwq4jMgmI6xgwWQo=; b=x3RNBTErATTcsOjG2N7v9o4QvuY5qMhR476l+kW7W+cCbupNZWU7BU5+fxhoKsz9sf yCaZ7fLe0wAPV9sMxSTbn30Vovb3zOAOI+AIi0S+FtWB9/ffSjN4jsmThfNjJXvfneHU yKhvGrMeybDNUqyVEspNkgxjspOB5e1UxbDk/OiKDN28hRhB/qTrF4dE4ul+jUi+IWcX av7NkfCh/ajNLYQAcpNqP9iwXbaEjFm1m0lC5fjQ41pnA2DcK0dnKoKpzvJbUW5r1HQl nnr4t0StKeSCv510qJChrAJXri0jk3LZHG2i1287BTvpVFsrvg00vDfJ7NjeZWb64GVj /LvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=GVsR5iRt; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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AM2PR04MB0753; 6:FOe2Y2SbhQsyZ03YVntZS+dmaONl+ftVQeM1HJ4zkXK1Y4BPTB6B9tjQfVoMqCjcf2PreNNpbypmd2PyB8a1HPSSggCHzu/WM4K7Eeo5D2GMZWD9BakbvVjHbXu+jxyZq0fOeMCPf0BykMo/BVDTm51dWs0zWYWEHNO6XtubSfYke6Nk54L2Cs3wrBua5pEYQiB2RbYW2l+iH8ywZ+RPdPTIbRoABmCpxnuOQbICJC0EXjUD4LFpG8jxJAFKAJKYLsmdFj0TckOFKoz6tzCRNc83dfDfQ7bnC6eRjr+Qq89n/WTAvNfROIbp5/B8r1CKQiUIs9jjkdMoCRXNXcPwsYp/thuCEx8KPi/ipg8CI8Q=; 5:6uAa7JoIzaq8Peme/P6Ug1Oppw62h/cPdHEn/0BDCnGlUnfb0qj7jd4CaFnZaFgD9Mbs1HO8r/J1uUoUh224t4MDYK1/7yLYJrzRg3Fc3dgimECfmkxp6YdpwKYYkpMEHINgsZmjfWZjy7A/0wM1EHHfWqUBm/Vaf5FqEf/pbw8=; 24:GMlTPX0nvybR98ZkKZBO/7CUSHjwen51qyzIfUyiduz5khS7ZjWxFycIbb2/FGO5m7ADofiujm90Bck6PFV1h36AIpOMG8Qrte/tBz3R36E=; 7:nnQmHEhascCJ+jIcWTj55lIVG4ZAObIsHG180MZ0JRZLAJRT67FSa0kSIKat+nHtQIJFw4kdsjmFyrLL8gzfOxN05mLCW47PWGcHTNpwWPWuR9Yk8gdIQQM8A0zwgOBRCO2A4giL6d8T7x0qlVnoNrzsBEWD6fl1nTTBYdpqijsZaAWj3wG90qdSYBKjvEVjdeg7+C0GdDbTLel1AIArruUVSNwz2RTqx65ykucfA+CQiO2bAKsRoyVTrGeocknq SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2018 07:35:00.9123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cc737ef-8fd8-451a-95d4-08d57f46f161 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0753 Subject: [dpdk-dev] [PATCH v2 05/10] bus/fslmc: add 32 bit functional support for ARM X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the functional logic to make the dpaa2 drivers work on 32bit machine. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/qbman/qbman_sys.h | 30 ++++++++++++++++++++++++++++-- drivers/bus/fslmc/qbman/qbman_sys_decl.h | 9 +++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 846788e..0b460c4 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -20,6 +20,9 @@ #include "qbman_sys_decl.h" +#define CENA_WRITE_ENABLE 0 +#define CINH_WRITE_ENABLE 1 + /* Debugging assists */ static inline void __hexdump(unsigned long start, unsigned long end, unsigned long p, size_t sz, const unsigned char *c) @@ -178,7 +181,11 @@ static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s, s->addr_cena, s->idx, offset); #endif QBMAN_BUG_ON(offset & 63); +#ifdef RTE_ARCH_64 return (s->addr_cena + offset); +#else + return (s->addr_cinh + offset); +#endif } static inline void qbman_cena_write_complete(struct qbman_swp_sys *s, @@ -191,11 +198,19 @@ static inline void qbman_cena_write_complete(struct qbman_swp_sys *s, s->addr_cena, s->idx, offset, shadow); hexdump(cmd, 64); #endif +#ifdef RTE_ARCH_64 for (loop = 15; loop >= 1; loop--) __raw_writel(shadow[loop], s->addr_cena + offset + loop * 4); lwsync(); __raw_writel(shadow[0], s->addr_cena + offset); +#else + for (loop = 15; loop >= 1; loop--) + __raw_writel(shadow[loop], s->addr_cinh + + offset + loop * 4); + lwsync(); + __raw_writel(shadow[0], s->addr_cinh + offset); +#endif dcbf(s->addr_cena + offset); } @@ -224,9 +239,15 @@ static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset) s->addr_cena, s->idx, offset, shadow); #endif +#ifdef RTE_ARCH_64 for (loop = 0; loop < 16; loop++) shadow[loop] = __raw_readl(s->addr_cena + offset + loop * 4); +#else + for (loop = 0; loop < 16; loop++) + shadow[loop] = __raw_readl(s->addr_cinh + offset + + loop * 4); +#endif #ifdef QBMAN_CENA_TRACE hexdump(shadow, 64); #endif @@ -313,6 +334,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, uint8_t dqrr_size) { uint32_t reg; +#ifndef RTE_ARCH_64 + uint8_t wn = CENA_WRITE_ENABLE; +#else + uint8_t wn = CINH_WRITE_ENABLE; +#endif s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; @@ -333,10 +359,10 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, QBMAN_BUG_ON(reg); #endif if (s->eqcr_mode == qman_eqcr_vb_array) - reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1, + reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1, 1, 1); else - reg = qbman_set_swp_cfg(dqrr_size, 0, 1, 3, 2, 2, 1, 1, 1, 1, + reg = qbman_set_swp_cfg(dqrr_size, wn, 2, 3, 2, 2, 1, 1, 1, 1, 1, 1); qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h index f82bb18..5640b04 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h +++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h @@ -15,6 +15,7 @@ /****************/ /* arch assists */ /****************/ +#if defined(RTE_ARCH_ARM64) #define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); } #define lwsync() { asm volatile("dmb st" : : : "memory"); } #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); } @@ -28,3 +29,11 @@ static inline void prefetch_for_store(void *p) { asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p)); } +#elif defined(RTE_ARCH_ARM) +#define dcbz(p) memset(p, 0, 64) +#define lwsync() { asm volatile("dmb st" : : : "memory"); } +#define dcbf(p) RTE_SET_USED(p) +#define dccivac(p) RTE_SET_USED(p) +#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); } +#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); } +#endif From patchwork Thu Mar 1 07:33:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130125 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2482553edc; Wed, 28 Feb 2018 23:36:26 -0800 (PST) X-Google-Smtp-Source: AG47ELvnGcB42nOEAzVujA05inqk5qN3DSyUobsLPyJOb3B7J3Ct9G42v6JEU3OcoVTDPxKGVKG4 X-Received: by 10.28.142.135 with SMTP id q129mr977931wmd.112.1519889786386; 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AM2PR04MB0753; 6:4l126dXyAu6ygnBfyCV2zxoChEaFOtuzBu5vF0H212DAkA8hbpai7eghMqivIAjag8TcARWOyPUA8W4j0dSttGh73zpB2P20RpATTQxTdiLH11YM1zimJ8m6l12j4e3Du3RwCxPWk+ZGviPSGKXQGvDeJY+3xDVPLD+nge+whWwqv+m8dzNRy6UdEZHD0cKwVux732F0DMwizgCew8b9ch+KWStWEVYYm+sMdjQmb1wHv8Ek8FXyQTibsks4CW5KN88ERtcYbUZ3qksX4BYMFsTUWQz63pekSXhFCk5/lchTfiLvErNwMdlRKUEDoe54sOIXZbkaNCSOHY7app2dBTp3MSp+I0dd0jFtc0ZjYLg=; 5:4ge9DkZfqv3HlOHFIlFqWj0qzyhhUt1QUOy4FHQiM3b/EGJV9ZzJctuFeYJZrgar92XZi4kmKwqv8ksDyBSPcH42zIA+HJtqe2utrMnoJYlP2f3aTVThtRlyLi0/fL33TAUvJLGQxuxrM2LrCe1DW0zBuVqNmUECmf54PLHe9PM=; 24:7s88bFYE5FaxRmp/ImHlvEaoLM837EsSSxpzC6U/UGhzwIq2B5nb7lka5+Gh92owrT/oqBEHq7GOp9q8YMNKTm6NgCw1tnwuY5BwXB6qKTs=; 7:S3f0ymWwm/MK2jPK3iueCDZRCI+HPqzH1QRQtS8UTH4fto8gy2r7NQA4HdJD15RC3g3hLAV1OmngS2fv++S/IpIJIZbZ323b2Y5qN4oOiC7r/xwUjUh3lqPXTgb1faLTRQ0zOBYmXvhKp3dCpnwUxztzsXxR5o7SrHXKowO6z4PHvwgYko8kXb3pHeyBthJHukzTeH5dWU0wVhDsGpjaqHvA0+kf9mkuFpLdUAP1uFgWpCAN6oEBr8YA7ZOeE/N1 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2018 07:35:02.0373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6538b73b-7e9a-47aa-7b70-08d57f46f208 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0753 Subject: [dpdk-dev] [PATCH v2 06/10] bus/dpaa: enabling dpaa compilation for other platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/bus/dpaa/include/compat.h | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/dpaa/include/compat.h b/drivers/bus/dpaa/include/compat.h index 53707bb..e4b5702 100644 --- a/drivers/bus/dpaa/include/compat.h +++ b/drivers/bus/dpaa/include/compat.h @@ -39,6 +39,7 @@ #include #include #include +#include /* The following definitions are primarily to allow the single-source driver * interfaces to be included by arbitrary program code. Ie. for interfaces that @@ -127,13 +128,15 @@ static inline void out_be32(volatile void *__p, u32 val) *p = rte_cpu_to_be_32(val); } +#define hwsync() rte_rmb() +#define lwsync() rte_wmb() + #define dcbt_ro(p) __builtin_prefetch(p, 0) #define dcbt_rw(p) __builtin_prefetch(p, 1) +#if defined(RTE_ARCH_ARM64) #define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); } #define dcbz_64(p) dcbz(p) -#define hwsync() rte_rmb() -#define lwsync() rte_wmb() #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); } #define dcbf_64(p) dcbf(p) #define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); } @@ -144,9 +147,27 @@ static inline void out_be32(volatile void *__p, u32 val) asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \ } while (0) +#elif defined(RTE_ARCH_ARM) +#define dcbz(p) memset((p), 0, 32) +#define dcbz_64(p) memset((p), 0, 64) +#define dcbf(p) RTE_SET_USED(p) +#define dcbf_64(p) dcbf(p) +#define dccivac(p) RTE_SET_USED(p) +#define dcbit_ro(p) RTE_SET_USED(p) + +#else +#define dcbz(p) RTE_SET_USED(p) +#define dcbz_64(p) dcbz(p) +#define dcbf(p) RTE_SET_USED(p) +#define dcbf_64(p) dcbf(p) +#define dccivac(p) RTE_SET_USED(p) +#define dcbit_ro(p) RTE_SET_USED(p) +#endif + #define barrier() { asm volatile ("" : : : "memory"); } #define cpu_relax barrier +#if defined(RTE_ARCH_ARM64) static inline uint64_t mfatb(void) { uint64_t ret, ret_new, timeout = 200; @@ -160,6 +181,11 @@ static inline uint64_t mfatb(void) DPAA_BUG_ON(!timeout && (ret != ret_new)); return ret * 64; } +#else + +#define mfatb rte_rdtsc + +#endif /* Spin for a few cycles without bothering the bus */ static inline void cpu_spin(int cycles) From patchwork Thu Mar 1 07:33:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130126 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2482759edc; Wed, 28 Feb 2018 23:36:41 -0800 (PST) X-Google-Smtp-Source: AG47ELu++8htig1hJbchPjz9XtjqSwTtVj24pLI2rMy8TvDOVE/HsN9oSoHFAhUfWmMs81rVpA8B X-Received: by 10.223.208.132 with SMTP id y4mr696096wrh.185.1519889801428; Wed, 28 Feb 2018 23:36:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519889801; cv=none; d=google.com; s=arc-20160816; b=y5e9oEwPLB/9GqrVs+19xmvUAeZAl7y6NQR7bre+1qQADron8a5l/wuw13PUtMuRnZ dYKmorD2q62HKXiYW0kXIPhsGwFyB7jLYJcF+huEp5+x5yL+Lz9fBBGI+EjVVuKLYtDJ RMd1bmvIgBc5dWt7wg7r4Sy9wg9oyGJRaR53JFATvRohFtVNHioE/kliMl+sKzyYvW/N /23tIYj2Nx3+x5EEDx9dDr/1i8AOkAOSn0LDYlHJi9L+Q6dpKA7oz7NAdnQ3EGUECDrm sBqDy1JIKdoqPxkmKfCM+lMJ6T13jxRUf1tvu/aFyHfEY1LlRgOueEsPwcDz2WnT5frX THvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature:arc-authentication-results; bh=MjmjqcIGob+uoQE6xVPSpAX0+Fx7g6gjkoE6LLToVQI=; b=mUsTL1/GMsIBGE5EsFrf2y8jFmLDZ7hefHCEcavaHWY8u1ThhJxYMLocNcm5ihruK0 NpV9wHbt0C3F+/8iLAjdofanXLc+ucVWWZInwLUvrzKZu3RoHNHF4dgPzycd8/uKtYVM aq5WevNuXOfmHloXIQzX6jBS6NaMMK0sw7rZvD0KG+0eA8VY1RibQ8mAcl8+RuJpcmGV UYFsGAMEpQ0XplwQUMAXrsTlGjHn4U6pJMGYMyaYjCFvLt+o3hAdiV4bZxHTv70+kEtX SE22sV/6qNWejWqbMM+RA3bZKK89r85wszcLIE3YT0Gh+cmOBb8Uxy0wP/5uc5uh4o6+ tLMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=Z/Sz2pMV; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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} #define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); } + +#else +#define dcbz(p) RTE_SET_USED(p) +#define lwsync() +#define dcbf(p) RTE_SET_USED(p) +#define dccivac(p) RTE_SET_USED(p) +static inline void prefetch_for_load(void *p) +{ + RTE_SET_USED(p); +} +static inline void prefetch_for_store(void *p) +{ + RTE_SET_USED(p); +} #endif From patchwork Thu Mar 1 07:33:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 130127 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2483000edc; Wed, 28 Feb 2018 23:36:59 -0800 (PST) X-Google-Smtp-Source: AG47ELtsIwJt8RBguuUanlsos+V8TOIsqrcsI0manfX6kXXDslz2PN9+LxDRlX5mrxTGIUIqggOK X-Received: by 10.223.201.15 with SMTP id m15mr721398wrh.54.1519889819439; Wed, 28 Feb 2018 23:36:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519889819; cv=none; d=google.com; s=arc-20160816; b=rwPRGQq15hZ9UqLEVH+BTtE78x4wKJJBJNAQkeDIJja6KixETdAZNISJwNHvSLko2Y wZsWClmeDuTOd9C6+w91VsNObGFBsY4UKj7OYrmYGJKXwgqmUsEFdEIDXPwlkMVqTIXc iuZLvrL+6JJ+iPIJZ6ZUgqfOFRDUSLxByMKGQAbs/iaCQrbr1QSjBDCOpac5D+zOHUBB Hk4SwMx8voR3e/DYAlmvKbqq1mHhNsvDJYRowTf5j0U2gzBl2R6HPhMrRl5+wN+PScRW Xt8TLIzAYIFZCwoC54VmvxzhcSzRn1l+QmJZJm4cnncCN56cepx8kalGA3Gss4Cr38Ew NaLg== ARC-Message-Signature: i=1; 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SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2018 07:35:05.5061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fcc8bc04-8938-4e40-a049-08d57f46f431 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0753 Subject: [dpdk-dev] [PATCH v2 09/10] build: add meson support for dpaaX platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Akhil Goyal Signed-off-by: Hemant Agrawal --- app/test-pmd/meson.build | 3 +++ config/arm/meson.build | 13 +++++++++++++ config/rte_config.h | 12 +++++++++++- drivers/bus/dpaa/meson.build | 29 +++++++++++++++++++++++++++++ drivers/bus/fslmc/meson.build | 27 +++++++++++++++++++++++++++ drivers/bus/meson.build | 2 +- drivers/crypto/dpaa2_sec/meson.build | 14 ++++++++++++++ drivers/crypto/dpaa_sec/meson.build | 13 +++++++++++++ drivers/crypto/meson.build | 4 +++- drivers/event/dpaa/meson.build | 10 ++++++++++ drivers/event/dpaa2/meson.build | 11 +++++++++++ drivers/event/meson.build | 2 +- drivers/mempool/dpaa/meson.build | 9 +++++++++ drivers/mempool/dpaa2/meson.build | 9 +++++++++ drivers/mempool/meson.build | 2 +- drivers/net/dpaa/meson.build | 14 ++++++++++++++ drivers/net/dpaa2/meson.build | 15 +++++++++++++++ drivers/net/meson.build | 2 +- 18 files changed, 185 insertions(+), 6 deletions(-) create mode 100644 drivers/bus/dpaa/meson.build create mode 100644 drivers/bus/fslmc/meson.build create mode 100644 drivers/crypto/dpaa2_sec/meson.build create mode 100644 drivers/crypto/dpaa_sec/meson.build create mode 100644 drivers/event/dpaa/meson.build create mode 100644 drivers/event/dpaa2/meson.build create mode 100644 drivers/mempool/dpaa/meson.build create mode 100644 drivers/mempool/dpaa2/meson.build create mode 100644 drivers/net/dpaa/meson.build create mode 100644 drivers/net/dpaa2/meson.build -- 2.7.4 diff --git a/app/test-pmd/meson.build b/app/test-pmd/meson.build index 7ed74db..83f8bb1 100644 --- a/app/test-pmd/meson.build +++ b/app/test-pmd/meson.build @@ -32,6 +32,9 @@ if dpdk_conf.has('RTE_LIBRTE_SOFTNIC_PMD') sources += files('tm.c') deps += 'pmd_softnic' endif +if dpdk_conf.has('RTE_LIBRTE_DPAA_PMD') + deps += ['bus_dpaa', 'mempool_dpaa', 'pmd_dpaa'] +endif dep_objs = [] foreach d:deps diff --git a/config/arm/meson.build b/config/arm/meson.build index 4e788a4..c1ab6ed 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -54,6 +54,17 @@ flags_cavium = [ ['RTE_MAX_LCORE', 96], ['RTE_MAX_VFIO_GROUPS', 128], ['RTE_RING_USE_C11_MEM_MODEL', false]] +flags_dpaa = [ + ['RTE_MACHINE', '"dpaa"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 16]] +flags_dpaa2 = [ + ['RTE_MACHINE', '"dpaa2"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 16], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', 'n']] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -69,6 +80,8 @@ impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic] impl_0x53 = ['Samsung', flags_generic, machine_args_generic] impl_0x56 = ['Marvell', flags_generic, machine_args_generic] impl_0x69 = ['Intel', flags_generic, machine_args_generic] +impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic] +impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic] if cc.get_define('__clang__') != '' diff --git a/config/rte_config.h b/config/rte_config.h index 699878a..72c0aa2 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -74,10 +74,20 @@ /* * Number of sessions to create in the session memory pool - * on a single QuickAssist device. + * on a single instance of crypto HW device. */ +/* QuickAssist device */ #define RTE_QAT_PMD_MAX_NB_SESSIONS 2048 +/* DPAA2_SEC */ +#define RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS 2048 + +/* DPAA_SEC */ +#define RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS 2048 + +/* DPAA SEC max cryptodev devices*/ +#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 + /* fm10k defines */ #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 diff --git a/drivers/bus/dpaa/meson.build b/drivers/bus/dpaa/meson.build new file mode 100644 index 0000000..f5c6d7b --- /dev/null +++ b/drivers/bus/dpaa/meson.build @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['ethdev', 'eventdev'] +sources = files('base/fman/fman.c', + 'base/fman/fman_hw.c', + 'base/fman/netcfg_layer.c', + 'base/fman/of.c', + 'base/qbman/bman.c', + 'base/qbman/bman_driver.c', + 'base/qbman/dpaa_alloc.c', + 'base/qbman/dpaa_sys.c', + 'base/qbman/process.c', + 'base/qbman/qman.c', + 'base/qbman/qman_driver.c', + 'dpaa_bus.c') + +allow_experimental_apis = true + +if cc.has_argument('-Wno-cast-qual') + cflags += '-Wno-cast-qual' +endif + +includes += include_directories('include', 'base/qbman') +cflags += ['-D_GNU_SOURCE'] diff --git a/drivers/bus/fslmc/meson.build b/drivers/bus/fslmc/meson.build new file mode 100644 index 0000000..e94340e --- /dev/null +++ b/drivers/bus/fslmc/meson.build @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['ethdev', 'eventdev', 'kvargs'] +sources = files('fslmc_bus.c', + 'fslmc_vfio.c', + 'mc/dpbp.c', + 'mc/dpci.c', + 'mc/dpcon.c', + 'mc/dpio.c', + 'mc/dpmng.c', + 'mc/mc_sys.c', + 'portal/dpaa2_hw_dpbp.c', + 'portal/dpaa2_hw_dpci.c', + 'portal/dpaa2_hw_dpio.c', + 'qbman/qbman_portal.c', + 'qbman/qbman_debug.c') + +allow_experimental_apis = true + +includes += include_directories('../../../lib/librte_eal/linuxapp/eal') +includes += include_directories('mc', 'qbman/include', 'portal') +cflags += ['-D_GNU_SOURCE'] diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build index c6af500..58dfbe2 100644 --- a/drivers/bus/meson.build +++ b/drivers/bus/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['pci', 'vdev'] +drivers = ['dpaa', 'fslmc', 'pci', 'vdev'] std_deps = ['eal'] config_flag_fmt = 'RTE_LIBRTE_@0@_BUS' driver_name_fmt = 'rte_bus_@0@' diff --git a/drivers/crypto/dpaa2_sec/meson.build b/drivers/crypto/dpaa2_sec/meson.build new file mode 100644 index 0000000..0fb4d96 --- /dev/null +++ b/drivers/crypto/dpaa2_sec/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_fslmc', 'security', 'mempool_dpaa2'] +sources = files('dpaa2_sec_dpseci.c', + 'mc/dpseci.c') + +allow_experimental_apis = true + +includes += include_directories('mc', 'hw') diff --git a/drivers/crypto/dpaa_sec/meson.build b/drivers/crypto/dpaa_sec/meson.build new file mode 100644 index 0000000..8a57098 --- /dev/null +++ b/drivers/crypto/dpaa_sec/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_dpaa', 'security'] +sources = files('dpaa_sec.c') + +allow_experimental_apis = true + +includes += include_directories('../dpaa2_sec/') diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 17041ad..736c9f5 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -1,7 +1,9 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['qat', 'null', 'openssl'] +drivers = ['dpaa_sec', 'dpaa2_sec', + 'openssl', 'null', 'qat'] + std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt = 'RTE_LIBRTE_@0@_PMD' driver_name_fmt = 'rte_pmd_@0@' diff --git a/drivers/event/dpaa/meson.build b/drivers/event/dpaa/meson.build new file mode 100644 index 0000000..9bbd6c2 --- /dev/null +++ b/drivers/event/dpaa/meson.build @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif +deps += ['mempool_dpaa', 'bus_dpaa', 'pmd_dpaa'] +sources = files('dpaa_eventdev.c') + +allow_experimental_apis = true diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build new file mode 100644 index 0000000..835460c --- /dev/null +++ b/drivers/event/dpaa2/meson.build @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif +deps += ['mempool_dpaa2', 'bus_fslmc', 'bus_vdev', 'pmd_dpaa2'] +sources = files('dpaa2_hw_dpcon.c', + 'dpaa2_eventdev.c') + +allow_experimental_apis = true diff --git a/drivers/event/meson.build b/drivers/event/meson.build index d7bc485..e951199 100644 --- a/drivers/event/meson.build +++ b/drivers/event/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['skeleton', 'sw', 'octeontx'] +drivers = ['dpaa', 'dpaa2', 'octeontx', 'skeleton', 'sw'] std_deps = ['eventdev', 'kvargs'] config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD' driver_name_fmt = 'rte_pmd_@0@_event' diff --git a/drivers/mempool/dpaa/meson.build b/drivers/mempool/dpaa/meson.build new file mode 100644 index 0000000..08423c2 --- /dev/null +++ b/drivers/mempool/dpaa/meson.build @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_dpaa'] +sources = files('dpaa_mempool.c') diff --git a/drivers/mempool/dpaa2/meson.build b/drivers/mempool/dpaa2/meson.build new file mode 100644 index 0000000..dee3a88 --- /dev/null +++ b/drivers/mempool/dpaa2/meson.build @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['mbuf', 'bus_fslmc'] +sources = files('dpaa2_hw_mempool.c') diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build index 5991856..693a861 100644 --- a/drivers/mempool/meson.build +++ b/drivers/mempool/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['ring', 'stack', 'octeontx'] +drivers = ['dpaa', 'dpaa2', 'octeontx', 'ring', 'stack'] std_deps = ['mempool'] config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL' driver_name_fmt = 'rte_mempool_@0@' diff --git a/drivers/net/dpaa/meson.build b/drivers/net/dpaa/meson.build new file mode 100644 index 0000000..a4c40a6 --- /dev/null +++ b/drivers/net/dpaa/meson.build @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif +deps += ['bus_dpaa', 'mempool_dpaa'] + +sources = files('dpaa_ethdev.c', + 'dpaa_rxtx.c') + +allow_experimental_apis = true + +install_headers('rte_pmd_dpaa.h') diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build new file mode 100644 index 0000000..ad1724d --- /dev/null +++ b/drivers/net/dpaa2/meson.build @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +deps += ['bus_fslmc', 'mempool_dpaa2'] +sources = files('base/dpaa2_hw_dpni.c', + 'dpaa2_ethdev.c', + 'dpaa2_rxtx.c', + 'mc/dpkg.c', + 'mc/dpni.c') + +includes += include_directories('base', 'mc') diff --git a/drivers/net/meson.build b/drivers/net/meson.build index 704cbe3..4ea6dcf 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -drivers = ['af_packet', 'bonding', +drivers = ['af_packet', 'bonding', 'dpaa', 'dpaa2', 'e1000', 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AM2PR04MB0753; 6:7qbBRbAq5c598rsMf4BdGr7ygRpfuY4XBpDc/DHX0P75iJSsxrwO6r6UzAp00RqNyP93CuDHPR2cDJ8O/i+4sMXg/doTzK8P8t1KVGUmYwfnCEFrr1q7OZpGgIVJz+D+rdLhelMrePLTfDoOxflj/Oo+6+a6ci2rHfzILK20ApAgdDopKYUvQS0h6p/ZJbbDanbs324M3xBnUamB3oClKor15OlLBgcg0t2z15gbRDGwB/IpM0t16UKeT/i2pA9OKzpeFu966YBoIPSnc0+lVqTYooatewItljjlcWqdVz+vodGJP6Q/ogKhb/hXNVvF8hMa7LuSDvuSfCeJX/FC+gvWjxbxSrvdnjmhN7UeaL4=; 5:Ii9iGydDPWWCynoCEz1Yd75IvMHmge1a1zNg193Ln/FTy0KKZGSVyyCeWX2bDyqA9eGuVN3fJzw4wQJu6lgkfS+JOA26OAXx7gpLB+Xg1CK7bTvgQReOfYgWFkcEm54/GA3SuntJja27rD9zNdvNXk85++OGymGlaJPiIxaRVA0=; 24:NPJMc7d7MxcnrJNgNNFB83hA/gvM0L+e5VkV2frpvDFP7H4/synvDhK74fL+jcZw3ePmtULXWxKLosTR87aGQotKbO6HHwAKBmrTYQAxLzA=; 7:zudLO4CpW7h2iydeBpxPXwcnXIFl1W7Aun54SmywcoXXAEYbx1padZgEUaIsyMSr//GLCjYB6irIXtWBZvg/DR+7vU/pHm2/y3cHO9qnuGw+wjza06ww40mtQNdFoehRgHleQPUVdnOwmg3Igr6I/Z+XZN32IdOJjSPiRUdFIJhpbDbUQwy63z0KpTsMdyUEpV8Pk0d8NZd14XAAR2DI26EHSl3H3fRd5To23IErhxt3h9LyZNS+LVWlzWpA8bmL SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2018 07:35:06.7405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 981f456c-349a-4940-c12a-08d57f46f4d3 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0753 Subject: [dpdk-dev] [PATCH v2 10/10] build: add meson cross compile config for dpaaX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- config/arm/arm64_dpaa2_linuxapp_gcc | 13 +++++++++++++ config/arm/arm64_dpaa_linuxapp_gcc | 14 ++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 config/arm/arm64_dpaa2_linuxapp_gcc create mode 100644 config/arm/arm64_dpaa_linuxapp_gcc -- 2.7.4 diff --git a/config/arm/arm64_dpaa2_linuxapp_gcc b/config/arm/arm64_dpaa2_linuxapp_gcc new file mode 100644 index 0000000..87337fb --- /dev/null +++ b/config/arm/arm64_dpaa2_linuxapp_gcc @@ -0,0 +1,13 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = 'dpaa2' diff --git a/config/arm/arm64_dpaa_linuxapp_gcc b/config/arm/arm64_dpaa_linuxapp_gcc new file mode 100644 index 0000000..f769435 --- /dev/null +++ b/config/arm/arm64_dpaa_linuxapp_gcc @@ -0,0 +1,14 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = 'dpaa'