From patchwork Tue Mar 13 12:04:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131443 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp643470ljb; Tue, 13 Mar 2018 05:06:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELtwSCVViKyb/IWoDFd1f+iUD4OpC1+vnU8dThszdUCkadudVO36Sg7O3qQpo/2q/PisDUzj X-Received: by 10.98.63.75 with SMTP id m72mr395765pfa.122.1520942766079; Tue, 13 Mar 2018 05:06:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942766; cv=none; d=google.com; s=arc-20160816; b=y/z9lymGOEsX3TV60C/tbsZvGcnkv1e97j3aquWQU2b2yRnb9t1XcdQTsXCrwTL0nD 7IigaeYUfPyvdWWo+9tFW7SFKcoQ3IroG3enhREqmigiuHoA/Ss3heD0d2YNWbm5MsoC PcVWQbYkTIhKjSiUJDm6hhedhxACKCLnILOjXCxjUEIBm/Hf9R2Q7Xx+rJiZfMS1JGJl rOmCoheP4YF8JEVONjHdDMjQHFcrW28j9JcdIj10Pqx6CnOX048gEUv91qjBiuJBN/Nt dXvwRT4kad8HNmFZ5WyrMgd6Gg2YBOACeZ5kCOEMzfPe54BiUI3IJkhx0RodqVGotNy8 nu1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=Vu0+mB8kYK9pH5trUxh3liUQcq4I15eYyKzTQXpUZbc=; b=yajPHbdB3js95qyKF9DMq53NgxHqIVROBNDE6o8Gq973+S/EYMsbkSWnUKncfVDNmr vJYn8KoOu+rS2mFvSqs8njML9PdZu/PPsO1+j7B5Nkbun6Jt098v4b7OP3oES6uXFXZd DMw6TwIxsbDcb/8iGYzQlT/lHW3wZH/S973+3xtP0AILsLOND8VkC6BMqZXPhG8AqF3e UGI9wFjcr5PKmYktAUI0NhJYjbHjbxwYGwPLz0sFiDveJ78gbm3xtgcLFx14ptUHLetL LFZpaSGXXiN5e8LBxToP8a2Dov3uhGO9KLt7nn8OE+iACaAznSxjObCYPUUo5KvSUo26 LJdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e61-v6si49075plb.190.2018.03.13.05.06.05; Tue, 13 Mar 2018 05:06:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933225AbeCMMGC (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:54698 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933198AbeCMMF7 (ORCPT ); Tue, 13 Mar 2018 08:05:59 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 41608204EF; Tue, 13 Mar 2018 12:05:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 41608204EF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 11/31] perf vendor events: Drop incomplete multiple mapfile support Date: Tue, 13 Mar 2018 09:04:48 -0300 Message-Id: <20180313120508.29327-12-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry Currently jevents supports multiple mapfiles, but this is only in the form where mapfile basename starts with 'mapfile.csv' At the moment, no architectures actually use multiple mapfiles, so drop the support for now. This patch also solves a nuisance where, when the mapfile is edited and the text editor may create a backup, jevents may use the backup, as shown: jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv Signed-off-by: John Garry Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-2-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/README | 5 ++--- tools/perf/pmu-events/jevents.c | 10 ++-------- 2 files changed, 4 insertions(+), 11 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index c2ee3e4417fe..2407abc1d441 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - - Regular files with basename starting with 'mapfile.csv' are assumed - to be a CSV file that maps a specific CPU to its set of PMU events. - (see below for mapfile format) + - The CSV file that maps a specific CPU to its set of PMU events is to + be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored. diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index b578aa26e375..9e0a21e74a67 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb, * after processing all JSON files (so we can write out the * mapping table after all PMU events tables). * - * TODO: Allow for multiple mapfiles? Punt for now. */ if (level == 1 && is_file) { - if (!strncmp(bname, "mapfile.csv", 11)) { - if (mapfile) { - pr_info("%s: Many mapfiles? Using %s, ignoring %s\n", - prog, mapfile, fpath); - } else { - mapfile = strdup(fpath); - } + if (!strcmp(bname, "mapfile.csv")) { + mapfile = strdup(fpath); return 0; } From patchwork Tue Mar 13 12:04:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131460 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp651516ljb; Tue, 13 Mar 2018 05:12:36 -0700 (PDT) X-Google-Smtp-Source: AG47ELuq/WMnt6h8IjGZIL77RghBtf1aVVyeJuhIvVVhApxsQsAlt1T7OQYwzP1kH6/FRg6yr+Bs X-Received: by 2002:a17:902:1c5:: with SMTP id b63-v6mr346016plb.311.1520943156201; Tue, 13 Mar 2018 05:12:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520943156; cv=none; d=google.com; s=arc-20160816; b=ZIK8bfURk8kgmvOQDLwRmVrfTqCSpehMBqW0Nj/7lJUGlfd5XTj33EtODFTjdp6me1 OhMfZCntmgvAeVSggamP5V2USwrLnmv6c5MpF5j+lOdh6mqEM66inh2CHPoeSB279LfN rVLSag++OanKUC3qTwRIOz56KQhsW/AqPVck5OOQQIKu+sHK/pR+jiXDCQ0aRM6P3lCv Sj0GIgYn3/8Yygqf+wUTrgjwW0GIPTvcT1GJifT/WKSIXBlQARxu97n1Q7lnd8B05KH6 jFJNiEuDh2SQwBNEoh0fhFxyG1tyRqlg1Fwum57vO4wSadqNxcuswXFiinxlRpCYN8P+ NCzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=1DuhYB5rou/GYFAvv9B0rpxFrtAVBAT5X6w9+sxUQc4=; b=qe5nyom95tvfpksruzGSrwQWkFP1vNqJI1w1wRvSbUZLT5CwB1WGUz3Pw39vU0qVBZ 1s9//xLdi8kVGD9uUla1lIRsc2Hp41v0lqZDyMN38Jg6BklbiLi1O4NoGZdDNlnko/E3 DUmcf1SgS0z48JW5Q4TXOZOryRFI5LAv909PGIAqev6yqaAs24iwImjjaw+pHKHJIVUv hb53ADOlRUDs8hy2+mGrcaCbNeIPeJ2xXImGWcBtTjflSFZXcA56eWLUUB92Obk7ArlQ 57lI49PP9AHfULnJyyTHN9+6fRJiSw8UTY5y8PRbnuoLd6SuIZf0ULZ/nhniVi4lIrPP fvdg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k66si42010pfa.415.2018.03.13.05.12.35; Tue, 13 Mar 2018 05:12:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933249AbeCMMGG (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:54776 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933198AbeCMMGE (ORCPT ); Tue, 13 Mar 2018 08:06:04 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A52DE21783; Tue, 13 Mar 2018 12:05:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A52DE21783 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 12/31] perf vendor events: Fix error code in json_events() Date: Tue, 13 Mar 2018 09:04:49 -0300 Message-Id: <20180313120508.29327-13-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry When EXPECT macro fails an assertion, the error code is not properly set after the first loop of tokens in function json_events(). This is because err is set to the return value from func function pointer call, which must be 0 to continue to loop, yet it is not reset for for each loop. I assume that this was not the intention, so change the code so err is set appropriately in EXPECT macro itself. In addition to this, the indention in EXPECT macro is tidied. The current indention alludes that the 2 statements following the if statement are in the body, which is not true. Signed-off-by: John Garry Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-3-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 9e0a21e74a67..edff989fbcea 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) jsmntok_t *loc = (t); \ if (!(t)->start && (t) > tokens) \ loc = (t) - 1; \ - pr_err("%s:%d: " m ", got %s\n", fn, \ - json_line(map, loc), \ - json_name(t)); \ + pr_err("%s:%d: " m ", got %s\n", fn, \ + json_line(map, loc), \ + json_name(t)); \ + err = -EIO; \ goto out_free; \ } } while (0) @@ -416,7 +417,7 @@ int json_events(const char *fn, char *metric_name, char *metric_group), void *data) { - int err = -EIO; + int err; size_t size; jsmntok_t *tokens, *tok; int i, j, len; From patchwork Tue Mar 13 12:04:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131445 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp643667ljb; Tue, 13 Mar 2018 05:06:17 -0700 (PDT) X-Google-Smtp-Source: AG47ELs0U2FCgu2E0Knup6gxWpT1JqPo5r59MpRPspm2MO0+jyxQQbSwFqOYqoiB4vqWQIWbm17o X-Received: by 10.98.1.88 with SMTP id 85mr382267pfb.226.1520942776941; Tue, 13 Mar 2018 05:06:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942776; cv=none; d=google.com; s=arc-20160816; b=eALqCgGDUL3VYlkb5KtXuTKYXOmOiHivjId0ru6bxZ2QztMWIWuUbcZA2FLNTgUatG ktOj6V+5u4KXIyrewEXQ+TvAHL74nKt+TZcHyzqBYQwVIZx6aGdDtvPyELt//vOoviJL i+xJPG43asmht3icPgIFl/9ulrITu4obfknbAvBc0c104BTRC5IwH0OiIXWo5SUYzH+z 00VhBmClBaOivwzdMlYbvnIlqxlVg2yXew0+JDXvC9WPofNAN17AWzHHsCxS+Po5qqOL i2ieWkP/U4RHw+UYW8vLawNu8jQBFkrXZGrxKgbM0X8KQrRFLwrMnHEWbu2mDSsJuE91 EG4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=0ovJVhiOIQLS4qbGHE8Mvzl3SvYvUK+icZyFPhsdf60=; b=H16pux+O1Q00HBA+Iio/HMoNu8/DCJrAP1KES6cmNnlVvpkaSGngjyOJ0CXIEyS/9Y +SJjlA/i8P//FnS2Uhs9zVBdbYzkGnBGynLDiZQMjQArvQUh7zWakDtp8CiEFjROv7Ry j03sXGDmzRPQfgLLcMytlkmGSzXKELLLZB3f+9LxcBR2mahmsv2y6rj0ulYaJbzKUBP1 iitnavDkb4vnv15T94tPx7TARN/cY5ABog1bVw3sFQzk6LKQhUsg/8k9673JUw8MnFM1 HeUzjr8QRGKB1MRy/S9DF2/nKpC/skkH2gbTZ/r39WHClMjAIb3cSgMGJhfbEGmHCPMH TKOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6-v6si49970plr.174.2018.03.13.05.06.13; Tue, 13 Mar 2018 05:06:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933291AbeCMMGK (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:54834 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933266AbeCMMGI (ORCPT ); Tue, 13 Mar 2018 08:06:08 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1617121796; Tue, 13 Mar 2018 12:06:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1617121796 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 13/31] perf vendor events: Drop support for unused topic directories Date: Tue, 13 Mar 2018 09:04:50 -0300 Message-Id: <20180313120508.29327-14-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry Currently a topic subdirectory is supported in the pmu-events dir, in the following sample structure: /arch/platform/subtopic/mysubtopic.json Upto 256 levels of topic subdirectories are supported. So this means that JSONs may be located in a topic dir as well as the platform dir. This topic subdirectory causes problems if we want to add support for a vendor dir in the pmu-events structure (in the form arch/platform/vendor), in that we cannot differentiate between a vendor dir and a topic dir. Since the topic dir feature is not used, drop it so it does not block adding vendor subdirectory support. Signed-off-by: John Garry Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-4-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.c | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index edff989fbcea..1d02fafdc34d 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) goto out_free; \ } } while (0) -#define TOPIC_DEPTH 256 -static char *topic_array[TOPIC_DEPTH]; -static int topic_level; +static char *topic; static char *get_topic(void) { - char *tp_old, *tp = NULL; + char *tp; int i; - for (i = 0; i < topic_level + 1; i++) { - int n; - - tp_old = tp; - n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]); - if (n < 0) { - pr_info("%s: asprintf() error %s\n", prog); - return NULL; - } - free(tp_old); + /* tp is free'd in process_one_file() */ + i = asprintf(&tp, "%s", topic); + if (i < 0) { + pr_info("%s: asprintf() error %s\n", prog); + return NULL; } for (i = 0; i < (int) strlen(tp); i++) { @@ -291,25 +284,15 @@ static char *get_topic(void) return tp; } -static int add_topic(int level, char *bname) +static int add_topic(char *bname) { - char *topic; - - level -= 2; - - if (level >= TOPIC_DEPTH) - return -EINVAL; - + free(topic); topic = strdup(bname); if (!topic) { pr_info("%s: strdup() error %s for file %s\n", prog, strerror(errno), bname); return -ENOMEM; } - - free(topic_array[topic_level]); - topic_array[topic_level] = topic; - topic_level = level; return 0; } @@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, } } - if (level > 1 && add_topic(level, bname)) + if (level > 1 && add_topic(bname)) return -ENOMEM; /* From patchwork Tue Mar 13 12:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131446 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp643796ljb; Tue, 13 Mar 2018 05:06:22 -0700 (PDT) X-Google-Smtp-Source: AG47ELtEWEsIcG2WeXTEtdufg73sz7/kgjqOwvEWW0a3rSvHItkyrbosR4A/QmZzwv50uks8uQMx X-Received: by 2002:a17:902:7883:: with SMTP id q3-v6mr320969pll.361.1520942782218; Tue, 13 Mar 2018 05:06:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942782; cv=none; d=google.com; s=arc-20160816; b=RoBAM8A6ZXgPfPzIRb8CU0l28sGG7MKrX6OVNTcn3r4a6UE11S2znkXGYnT7+I6MP3 xtHViAZMf1CEGXaCbI/xD03tpqzsbmMKYznViAUqLaZuQe969jzzqqs9ZBGGBQkM3svn Y8FO5f2TAUUfE3GacTiOw2W3dapnReCMQhGiM6dgyHi5pl2unqXFeO6w9xptLefV/uHR 5OZBXB1VKrhp+usccJI+EnvGuI7ZoWWepwc3Q7Kyf3jdbjezcvJ34en7IYVDnyO0OFqo J45H0RdN5C/ekI+mgqukRuWWgLCT8QyYAKdNCI0yzZJ4/0Pq+NihcBdc6ieyqcWclKUW QygA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=OExuZsbe5z9Ke4ixWJTTh0VP+2duvL1unFeJmYcdZto=; b=eZkCrVHo9NS81Rs4YRjWtYgfjqDTUmBGvXx7IAhxd3DMSkciKA8qRX6oZ5I9iK3IaN 4L7ViXlmX0z1pCdFzNGvGs8UXI8wZRFnQW+fLz05g9pCSGcjJO2mMJR/asmEV8plLamk 6IzZqps7Cq32N6TUe8sDZNME+DyO8Mm5GkQ+Us65eY0WgmNKTGAw4oC778UK8izt5UrR 9Vbf4mTUkiLbnaXtIQ34tn5SAJjhJ8XR0Xs8bQ051Nx1GC3nsf/iCrCruRUpbCpAvQpH izsQu8lpF5R819kzySHmaMQMiUVyREQjUmOfuv35g+tLlrYeFtsaj69V19YgZzWkB1Mx c4Kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f1si22767pgr.761.2018.03.13.05.06.21; Tue, 13 Mar 2018 05:06:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933318AbeCMMGS (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:54890 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933209AbeCMMGM (ORCPT ); Tue, 13 Mar 2018 08:06:12 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7797421778; Tue, 13 Mar 2018 12:06:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7797421778 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 14/31] perf vendor events: Add support for pmu events vendor subdirectory Date: Tue, 13 Mar 2018 09:04:51 -0300 Message-Id: <20180313120508.29327-15-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry For some architectures (like arm), it is required to support a vendor subdirectory and not locate all the JSONs for a specific vendor in the same folder. This is because all the events for the same vendor will be placed in the same pmu events table, which may cause conflict. This conflict would be in the instance that a vendor's custom implemented events do have the same meaning on different platforms, so events in the pmu table would conflict. In addition, per list command may show events which are not even supported for a given platform. This patch adds support for a arch/vendor/platform directory hierarchy, while maintaining backwards-compatibility for existing arch/platform structure. In this, each platform would always have its own pmu events table. In generated file pmu_events.c, each platform table name is in the format pme{_vendor}_platform, like this: struct pmu_events_map pmu_events_map[] = { { .cpuid = "0x00000000420f5160", .version = "v1", .type = "core", .table = pme_cavium_thunderx2 }, { .cpuid = 0, .version = 0, .type = 0, .table = 0, }, }; Signed-off-by: John Garry Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-5-git-send-email-john.garry@huawei.com [ Add missing limits.h include, fixing the build on at least all Alpine Linux versions tested (3.4 to 3.7 + edge) ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/README | 4 +++ tools/perf/pmu-events/jevents.c | 65 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 63 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 2407abc1d441..655286ff8767 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU: Cache.json Memory.json Virtual-Memory.json Frontend.json Pipeline.json +The JSONs folder for a CPU model/family may be placed in the root arch +folder, or may be placed in a vendor sub-folder under the arch folder +for instances where the arch and vendor are not the same. + Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 1d02fafdc34d..b08dffeac4bd 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include /* getrlimit */ #include /* getrlimit */ @@ -572,7 +573,7 @@ static char *file_name_to_table_name(char *fname) * Derive rest of table name from basename of the JSON file, * replacing hyphens and stripping out .json suffix. */ - n = asprintf(&tblname, "pme_%s", basename(fname)); + n = asprintf(&tblname, "pme_%s", fname); if (n < 0) { pr_info("%s: asprintf() error %s for file %s\n", prog, strerror(errno), fname); @@ -582,7 +583,7 @@ static char *file_name_to_table_name(char *fname) for (i = 0; i < strlen(tblname); i++) { c = tblname[i]; - if (c == '-') + if (c == '-' || c == '/') tblname[i] = '_'; else if (c == '.') { tblname[i] = '\0'; @@ -739,25 +740,77 @@ static int get_maxfds(void) static FILE *eventsfp; static char *mapfile; +static int is_leaf_dir(const char *fpath) +{ + DIR *d; + struct dirent *dir; + int res = 1; + + d = opendir(fpath); + if (!d) + return 0; + + while ((dir = readdir(d)) != NULL) { + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') { + res = 0; + break; + } else if (dir->d_type == DT_UNKNOWN) { + char path[PATH_MAX]; + struct stat st; + + sprintf(path, "%s/%s", fpath, dir->d_name); + if (stat(path, &st)) + break; + + if (S_ISDIR(st.st_mode)) { + res = 0; + break; + } + } + } + + closedir(d); + + return res; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { - char *tblname, *bname = (char *) fpath + ftwbuf->base; + char *tblname, *bname; int is_dir = typeflag == FTW_D; int is_file = typeflag == FTW_F; int level = ftwbuf->level; int err = 0; + if (level == 2 && is_dir) { + /* + * For level 2 directory, bname will include parent name, + * like vendor/platform. So search back from platform dir + * to find this. + */ + bname = (char *) fpath + ftwbuf->base - 2; + for (;;) { + if (*bname == '/') + break; + bname--; + } + bname++; + } else + bname = (char *) fpath + ftwbuf->base; + pr_debug("%s %d %7jd %-20s %s\n", is_file ? "f" : is_dir ? "d" : "x", level, sb->st_size, bname, fpath); - /* base dir */ - if (level == 0) + /* base dir or too deep */ + if (level == 0 || level > 3) return 0; + /* model directory, reset topic */ - if (level == 1 && is_dir) { + if ((level == 1 && is_dir && is_leaf_dir(fpath)) || + (level == 2 && is_dir)) { if (close_table) print_events_table_suffix(eventsfp); From patchwork Tue Mar 13 12:04:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131458 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp650470ljb; Tue, 13 Mar 2018 05:11:45 -0700 (PDT) X-Google-Smtp-Source: AG47ELs3O+Uq6kdV4C5ux7koS8y0oJL+bpqO72GVtpaj7KktKhfOxCJNQ2E7wOK4bQ8MI4B3O02p X-Received: by 10.101.66.136 with SMTP id j8mr293080pgp.409.1520943105644; Tue, 13 Mar 2018 05:11:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520943105; cv=none; d=google.com; s=arc-20160816; b=UmRYGrWAyF0og2DeeiRrB1JKX9EnFKbnn8RY+m6t2SxZKeH3xIB3YugbSiEVFV+fYY 6d1wsjwYrnZ3ozdUTdxSqn6iF7JPqLkFwqq825J04MNWpAPmBzl/jyqG1V9yP3k2lENe g7EMN94eeFiyW+8HrALj62i6PNntcuOJt+VQ8bDgTLmgk1/EeOGOCBrvS691uWTgsbAL YnH+vid8Azgg6PCttFGjUm9sLHuNcPO8BbQMOHRRkGmrLi2ZAsMkKlCGL5NXENWcuDdF OaxhQsvXKzRbJbSASG+3NBQSOKVuBh2uK8me/D7XfFzXkF3xoJa8vqufzDdbLVR0w5VI VCrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=QiQYHdP8HDYEWT8tk5sOpW/mGnD2xnt/2Aw1/6fv+/I=; b=Rq1ENHH4mmUYAr30uLRUGstC40NA6/3xkFlGdrPgFsHP7YOvuQmErgW6foXQ1Qi9im na/7+WUd4BtcfLPkLcQBCilSAWr8hz3U+IJwyP9bn7x9bbYGT4FbIIpeieNftKPAMrab pkRT/ro1Dkh+Hvl5T+cNvGUOoGnPYOXDIPx1acSg/u8K6jncuFIKTll1T+bNzocVQNkX NumW++11uVf4DXVjVnc6iQKiFPlMDaMP+ob3HgN6+ScYhT8hBC4RuAd8IWtCwFcWNnho LMxbrzho+U2GOfm2YJpDjilZyJo3Z7LQ3LBR65CBFTs6ITL4mOcrZDZPT/igtcFFtrFt 7ArQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h1-v6si55370pln.216.2018.03.13.05.11.44; Tue, 13 Mar 2018 05:11:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933355AbeCMMLm (ORCPT + 28 others); Tue, 13 Mar 2018 08:11:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:54938 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933295AbeCMMGR (ORCPT ); Tue, 13 Mar 2018 08:06:17 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D9CDE2176F; Tue, 13 Mar 2018 12:06:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D9CDE2176F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 15/31] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory Date: Tue, 13 Mar 2018 09:04:52 -0300 Message-Id: <20180313120508.29327-16-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry Since jevents now supports vendor subdirectory, relocate the ThunderX2 JSON to Cavium subdirectory. Signed-off-by: John Garry Tested-by: Ganapatrao Kulkarni Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-6-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} | 0 tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename tools/perf/pmu-events/arch/arm64/cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} (100%) -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json rename to tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index e61c9ca6cf9e..952a05cbf675 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Tue Mar 13 12:04:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131447 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp643936ljb; Tue, 13 Mar 2018 05:06:28 -0700 (PDT) X-Google-Smtp-Source: AG47ELuj81GpRRj03WC8QOnU6zatXF+dH6UdI6wmAC4D8HK424m8K/BZdqthI5iVYf9OBe6iko1J X-Received: by 10.98.93.87 with SMTP id r84mr363309pfb.131.1520942788663; Tue, 13 Mar 2018 05:06:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942788; cv=none; d=google.com; s=arc-20160816; b=e5HepAyd1UXgdVJBwh8jlgIqGqa9FAtLek2CON9ZEaumdAjIc4wcOeaqToV4rX8P8e kKGwBdN3ROy0v2ONQs7T8w8x2PK4ANqWm+Ydp2Fwr/XI4UR/HMbGWUSI0LK66+bWpbhW ckU04n9QS8qnWXxmBwqQXY14rw46ULAwhpBafw9Fo5Fu+YrvClAi8+TMeNGrRnMr/R99 N0JxbL4e60d6vL9c9Zvp5MQaDFbe4GUFfK7kNHBZy6KekweSH1S5sN/r+U8CR16pUfqG GIDRTKjNbkL6+Hsdia9ZdR6MPSUWx8AgMZBKGtAz4/0o8aKH/e7V7iGEcgPz6Ya+jbXB Xrgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=SsWGSmR8P7179gVyhbCQue5NCXyhd/drseix/h/WPY8=; b=KvOGFLvDtqipEtQRU1s6WyYo87GAWlrqe+AObWcPwfhy0rwLikbEEmE3fm9wJCEYb7 KTGAbL0qEhm0qxg26+6mnt/gj6YV9cNeVYUzHe4gxiTmb1X+0ziBCHIFwc5b6wVGjfso EjDapzV0QyYdKOUL90N/poFq0gFH5TzymBJ1Ca70dXe1KvY1BMUBupbG2pt57NfVxwMd DpEKgoHfAE43IvaCxHBA94NDXQwrsvU4NBFwSh7+ipDjc4f37fyJ+YoypCtGcVJVt9Er QhvB+KfUUbD2uvp+9Fu76SE3T9kiRbqUa83NTTTKGgXM5twtXhOI5FIgYixK8KnkmCVy VA4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f1si22767pgr.761.2018.03.13.05.06.28; Tue, 13 Mar 2018 05:06:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933339AbeCMMGZ (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:54970 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933209AbeCMMGW (ORCPT ); Tue, 13 Mar 2018 08:06:22 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3BA032178D; Tue, 13 Mar 2018 12:06:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3BA032178D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 16/31] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory Date: Tue, 13 Mar 2018 09:04:53 -0300 Message-Id: <20180313120508.29327-17-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm subdirectory. Signed-off-by: John Garry Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-7-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json | 0 tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json | 0 tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json | 0 tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json | 0 tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json | 0 tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json | 0 tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 7 files changed, 1 insertion(+), 1 deletion(-) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json (100%) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json (100%) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json (100%) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json (100%) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json (100%) rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json (100%) -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/other.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json rename to tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 952a05cbf675..cf14e23b6404 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core -0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Tue Mar 13 12:04:54 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id o2si31266pgf.658.2018.03.13.05.11.20; Tue, 13 Mar 2018 05:11:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933356AbeCMMGb (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:55028 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933209AbeCMMG0 (ORCPT ); Tue, 13 Mar 2018 08:06:26 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C2D7421797; Tue, 13 Mar 2018 12:06:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C2D7421797 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 17/31] perf vendor events: Add support for arch standard events Date: Tue, 13 Mar 2018 09:04:54 -0300 Message-Id: <20180313120508.29327-18-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry For some architectures (like arm), there are architecture- defined events. Sometimes these events may be "recommended" according to the architecture standard, in that the implementer is free ignore the "recommendation" and create its custom event. This patch adds support for parsing standard events from arch-defined JSONs, and fixing up vendor events when they have implemented these events as standard. Support is also ensured that the vendor may implement their own custom events. A new step is added to the pmu events parsing to fix up the vendor events with the arch-standard events. The arch-defined JSONs must be placed in the arch root folder for preprocessing prior to tree JSON processing. In the vendor JSON, to specify that the arch event is supported, the keyword "ArchStdEvent" should be used, like this: [ { "ArchStdEvent": "L1D_CACHE_WR", }, ] Matching is based on the "EventName" field in the architecture JSON. No other JSON objects are strictly required. However, for other objects added, these take precedence over architecture defined standard events, thus supporting separate events which have the same event code. Signed-off-by: John Garry Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-8-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/Build | 2 + tools/perf/pmu-events/README | 6 ++ tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 172 insertions(+), 3 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 999a4e878162..17783913d330 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -1,10 +1,12 @@ hostprogs := jevents jevents-y += json.o jsmn.o jevents.o +CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include pmu-events-y += pmu-events.o JDIR = pmu-events/arch/$(SRCARCH) JSON = $(shell [ -d $(JDIR) ] && \ find $(JDIR) -name '*.json' -o -name 'mapfile.csv') + # # Locate/process JSON files in pmu-events/arch/ # directory and create tables in pmu-events.c. diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 655286ff8767..e62b09b6a844 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo. - Directories are traversed, but all other files are ignored. + - To reduce JSON event duplication per architecture, platform JSONs may + use "ArchStdEvent" keyword to dereference an "Architecture standard + events", defined in architecture standard JSONs. + Architecture standard JSONs must be located in the architecture root + folder. Matching is based on the "EventName" field. + The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index b08dffeac4bd..1c018445e757 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -45,6 +45,7 @@ #include /* getrlimit */ #include #include +#include #include "jsmn.h" #include "json.h" #include "jevents.h" @@ -351,6 +352,81 @@ static int print_events_table_entry(void *data, char *name, char *event, return 0; } +struct event_struct { + struct list_head list; + char *name; + char *event; + char *desc; + char *long_desc; + char *pmu; + char *unit; + char *perpkg; + char *metric_expr; + char *metric_name; + char *metric_group; +}; + +#define ADD_EVENT_FIELD(field) do { if (field) { \ + es->field = strdup(field); \ + if (!es->field) \ + goto out_free; \ +} } while (0) + +#define FREE_EVENT_FIELD(field) free(es->field) + +#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\ + *field = strdup(es->field); \ + if (!*field) \ + return -ENOMEM; \ +} } while (0) + +#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \ + op(name); \ + op(event); \ + op(desc); \ + op(long_desc); \ + op(pmu); \ + op(unit); \ + op(perpkg); \ + op(metric_expr); \ + op(metric_name); \ + op(metric_group); \ +} while (0) + +static LIST_HEAD(arch_std_events); + +static void free_arch_std_events(void) +{ + struct event_struct *es, *next; + + list_for_each_entry_safe(es, next, &arch_std_events, list) { + FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); + list_del(&es->list); + free(es); + } +} + +static int save_arch_std_events(void *data, char *name, char *event, + char *desc, char *long_desc, char *pmu, + char *unit, char *perpkg, char *metric_expr, + char *metric_name, char *metric_group) +{ + struct event_struct *es; + struct stat *sb = data; + + es = malloc(sizeof(*es)); + if (!es) + return -ENOMEM; + memset(es, 0, sizeof(*es)); + FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD); + list_add_tail(&es->list, &arch_std_events); + return 0; +out_free: + FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); + free(es); + return -ENOMEM; +} + static void print_events_table_suffix(FILE *outfp) { fprintf(outfp, "{\n"); @@ -392,6 +468,32 @@ static char *real_event(const char *name, char *event) return event; } +static int +try_fixup(const char *fn, char *arch_std, char **event, char **desc, + char **name, char **long_desc, char **pmu, char **filter, + char **perpkg, char **unit, char **metric_expr, char **metric_name, + char **metric_group, unsigned long long eventcode) +{ + /* try to find matching event from arch standard values */ + struct event_struct *es; + + list_for_each_entry(es, &arch_std_events, list) { + if (!strcmp(arch_std, es->name)) { + if (!eventcode && es->event) { + /* allow EventCode to be overridden */ + free(*event); + *event = NULL; + } + FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD); + return 0; + } + } + + pr_err("%s: could not find matching %s for %s\n", + prog, arch_std, fn); + return -1; +} + /* Call func with each event in the json file */ int json_events(const char *fn, int (*func)(void *data, char *name, char *event, char *desc, @@ -427,6 +529,7 @@ int json_events(const char *fn, char *metric_expr = NULL; char *metric_name = NULL; char *metric_group = NULL; + char *arch_std = NULL; unsigned long long eventcode = 0; struct msrmap *msr = NULL; jsmntok_t *msrval = NULL; @@ -512,6 +615,10 @@ int json_events(const char *fn, addfield(map, &metric_expr, "", "", val); for (s = metric_expr; *s; s++) *s = tolower(*s); + } else if (json_streq(map, field, "ArchStdEvent")) { + addfield(map, &arch_std, "", "", val); + for (s = arch_std; *s; s++) + *s = tolower(*s); } /* ignore unknown fields */ } @@ -536,8 +643,21 @@ int json_events(const char *fn, if (name) fixname(name); + if (arch_std) { + /* + * An arch standard event is referenced, so try to + * fixup any unassigned values. + */ + err = try_fixup(fn, arch_std, &event, &desc, &name, + &long_desc, &pmu, &filter, &perpkg, + &unit, &metric_expr, &metric_name, + &metric_group, eventcode); + if (err) + goto free_strings; + } err = func(data, name, real_event(name, event), desc, long_desc, pmu, unit, perpkg, metric_expr, metric_name, metric_group); +free_strings: free(event); free(desc); free(name); @@ -550,6 +670,8 @@ int json_events(const char *fn, free(metric_expr); free(metric_name); free(metric_group); + free(arch_std); + if (err) break; tok += j; @@ -774,6 +896,32 @@ static int is_leaf_dir(const char *fpath) return res; } +static int is_json_file(const char *name) +{ + const char *suffix; + + if (strlen(name) < 5) + return 0; + + suffix = name + strlen(name) - 5; + + if (strncmp(suffix, ".json", 5) == 0) + return 1; + return 0; +} + +static int preprocess_arch_std_files(const char *fpath, const struct stat *sb, + int typeflag, struct FTW *ftwbuf) +{ + int level = ftwbuf->level; + int is_file = typeflag == FTW_F; + + if (level == 1 && is_file && is_json_file(fpath)) + return json_events(fpath, save_arch_std_events, (void *)sb); + + return 0; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { @@ -851,9 +999,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, * ignore it. It could be a readme.txt for instance. */ if (is_file) { - char *suffix = bname + strlen(bname) - 5; - - if (strncmp(suffix, ".json", 5)) { + if (!is_json_file(bname)) { pr_info("%s: Ignoring file without .json suffix %s\n", prog, fpath); return 0; @@ -959,12 +1105,26 @@ int main(int argc, char *argv[]) maxfds = get_maxfds(); mapfile = NULL; + rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0); + if (rc && verbose) { + pr_info("%s: Error preprocessing arch standard files %s\n", + prog, ldirname); + goto empty_map; + } else if (rc < 0) { + /* Make build fail */ + free_arch_std_events(); + return 1; + } else if (rc) { + goto empty_map; + } + rc = nftw(ldirname, process_one_file, maxfds, 0); if (rc && verbose) { pr_info("%s: Error walking file tree %s\n", prog, ldirname); goto empty_map; } else if (rc < 0) { /* Make build fail */ + free_arch_std_events(); return 1; } else if (rc) { goto empty_map; @@ -989,5 +1149,6 @@ int main(int argc, char *argv[]) empty_map: fclose(eventsfp); create_empty_mapping(output_file); + free_arch_std_events(); return 0; } From patchwork Tue Mar 13 12:04:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131448 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp644097ljb; Tue, 13 Mar 2018 05:06:37 -0700 (PDT) X-Google-Smtp-Source: AG47ELvK8hV0CVTid4czYHJgOBXjdwaUtal4FSPZmsMHSArb0LpPQdtCsFTyKH/DJVyzspqdhvER X-Received: by 2002:a17:902:44c:: with SMTP id 70-v6mr364732ple.354.1520942796957; Tue, 13 Mar 2018 05:06:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942796; cv=none; d=google.com; s=arc-20160816; b=nxqeKKB2mRdm2ftZDlgoWwREo1WpE5PCLjufVqhdRfIz5eZ16mK99wX4HuoK3K8eF3 Vga5n7iu8U6lLN50QUwjLsgql8l4jJ2QJbpLcGGL6j5ohJqLZmxBhtBLrJ6rTg4UG7tE FimUUIqfEosKD++fPs2kN23KbD4LFFnyaU635o49OLu2xB0w565Ss3iXI3h2wRtQK/H9 eq0DgKoV0WCEYKGqIfTw6jJHg//GWh1LNr4lqRIK7WK/aoxyYzOC8ySrlG7FqRU9EJ0r eSJEt9A7QTSBic+X6cZabbNf60Ye9g8ExnEBH8S9jGh3Km4N3wUgEiUIMCzwJqKnwnzM egaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=jETfXvTnSSm9MtiRHJf1nQAzAKmaQo5McMLhHvZQBEA=; b=mfQ2bxX7JWZxXhnt0vLNM0lTBx565mKmV9Yb50xj+tRFRxY9rcTUbUMmlB0NaXC6Ll XKDBJ4yvQp/4nsmS85cpO8+KDB3XIgJ2bqFb7uKrSQSA/1HWZjVYn/3hkEkpwhJViLtY 6Duue7dKbPg7WzOFhVSL6D8xdkA/zajbHGwRVwyyjsDPjzMdI9774oSez5wlYFj0qIIt aSbXujfoIxbBvDzCET7f0fznKm/kaJ12yn6rI7ondEMJZYspNVSJioXZX7reizVX6OZJ i/+HG3mlxkPmJpRzhml+eHWOsPE6i66xF+6D10JKBQLDzWR14wKARfWQWaeYY1K8ZaFV TSaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y10si46946pge.31.2018.03.13.05.06.36; Tue, 13 Mar 2018 05:06:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933371AbeCMMGe (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:55088 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933352AbeCMMGb (ORCPT ); Tue, 13 Mar 2018 08:06:31 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5FB3D21799; Tue, 13 Mar 2018 12:06:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FB3D21799 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Shaokun Zhang , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json Date: Tue, 13 Mar 2018 09:04:55 -0300 Message-Id: <20180313120508.29327-19-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events. The JSON is copied from ARMv8 architecture reference manual, available here: https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf Signed-off-by: Shaokun Zhang Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry@huawei.com Signed-off-by: John Garry Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json new file mode 100644 index 000000000000..6328828c018c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -0,0 +1,452 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "L1D_CACHE_RD", + "BriefDescription": "L1D cache access, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write", + "EventCode": "0x41", + "EventName": "L1D_CACHE_WR", + "BriefDescription": "L1D cache access, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "L1D_CACHE_REFILL_RD", + "BriefDescription": "L1D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "L1D_CACHE_REFILL_WR", + "BriefDescription": "L1D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, inner", + "EventCode": "0x44", + "EventName": "L1D_CACHE_REFILL_INNER", + "BriefDescription": "L1D cache refill, inner" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, outer", + "EventCode": "0x45", + "EventName": "L1D_CACHE_REFILL_OUTER", + "BriefDescription": "L1D cache refill, outer" + }, + { + "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", + "EventCode": "0x46", + "EventName": "L1D_CACHE_WB_VICTIM", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", + "EventCode": "0x47", + "EventName": "L1D_CACHE_WB_CLEAN", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 1 data cache invalidate", + "EventCode": "0x48", + "EventName": "L1D_CACHE_INVAL", + "BriefDescription": "L1D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "L1D_TLB_REFILL_RD", + "BriefDescription": "L1D tlb refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "L1D_TLB_REFILL_WR", + "BriefDescription": "L1D tlb refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "L1D_TLB_RD", + "BriefDescription": "L1D tlb access, read" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "L1D_TLB_WR", + "BriefDescription": "L1D tlb access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, read", + "EventCode": "0x50", + "EventName": "L2D_CACHE_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, write", + "EventCode": "0x51", + "EventName": "L2D_CACHE_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, read", + "EventCode": "0x52", + "EventName": "L2D_CACHE_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, write", + "EventCode": "0x53", + "EventName": "L2D_CACHE_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache Write-Back, victim", + "EventCode": "0x56", + "EventName": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency", + "EventCode": "0x57", + "EventName": "L2D_CACHE_WB_CLEAN", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 2 data cache invalidate", + "EventCode": "0x58", + "EventName": "L2D_CACHE_INVAL", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", + "EventCode": "0x5c", + "EventName": "L2D_TLB_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, write", + "EventCode": "0x5d", + "EventName": "L2D_TLB_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, read", + "EventCode": "0x5e", + "EventName": "L2D_TLB_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, write", + "EventCode": "0x5f", + "EventName": "L2D_TLB_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "BUS_ACCESS_RD", + "BriefDescription": "Bus access read" + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "BUS_ACCESS_WR", + "BriefDescription": "Bus access write" + } + { + "PublicDescription": "Bus access, Normal, Cacheable, Shareable", + "EventCode": "0x62", + "EventName": "BUS_ACCESS_SHARED", + "BriefDescription": "Bus access, Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", + "EventCode": "0x63", + "EventName": "BUS_ACCESS_NOT_SHARED", + "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, Normal", + "EventCode": "0x64", + "EventName": "BUS_ACCESS_NORMAL", + "BriefDescription": "Bus access, Normal" + } + { + "PublicDescription": "Bus access, peripheral", + "EventCode": "0x65", + "EventName": "BUS_ACCESS_PERIPH", + "BriefDescription": "Bus access, peripheral" + } + { + "PublicDescription": "Data memory access, read", + "EventCode": "0x66", + "EventName": "MEM_ACCESS_RD", + "BriefDescription": "Data memory access, read" + } + { + "PublicDescription": "Data memory access, write", + "EventCode": "0x67", + "EventName": "MEM_ACCESS_WR", + "BriefDescription": "Data memory access, write" + } + { + "PublicDescription": "Unaligned access, read", + "EventCode": "0x68", + "EventName": "UNALIGNED_LD_SPEC", + "BriefDescription": "Unaligned access, read" + } + { + "PublicDescription": "Unaligned access, write", + "EventCode": "0x69", + "EventName": "UNALIGNED_ST_SPEC", + "BriefDescription": "Unaligned access, write" + } + { + "PublicDescription": "Unaligned access", + "EventCode": "0x6a", + "EventName": "UNALIGNED_LDST_SPEC", + "BriefDescription": "Unaligned access" + } + { + "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", + "EventCode": "0x6c", + "EventName": "LDREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", + "EventCode": "0x6d", + "EventName": "STREX_PASS_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", + "EventCode": "0x6e", + "EventName": "STREX_FAIL_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", + "EventCode": "0x6f", + "EventName": "STREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" + } + { + "PublicDescription": "Operation speculatively executed, load", + "EventCode": "0x70", + "EventName": "LD_SPEC", + "BriefDescription": "Operation speculatively executed, load" + } + { + "PublicDescription": "Operation speculatively executed, store" + "EventCode": "0x71", + "EventName": "ST_SPEC", + "BriefDescription": "Operation speculatively executed, store" + } + { + "PublicDescription": "Operation speculatively executed, load or store", + "EventCode": "0x72", + "EventName": "LDST_SPEC", + "BriefDescription": "Operation speculatively executed, load or store" + } + { + "PublicDescription": "Operation speculatively executed, integer data processing", + "EventCode": "0x73", + "EventName": "DP_SPEC", + "BriefDescription": "Operation speculatively executed, integer data processing" + } + { + "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", + "EventCode": "0x74", + "EventName": "ASE_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", + } + { + "PublicDescription": "Operation speculatively executed, floating-point instruction", + "EventCode": "0x75", + "EventName": "VFP_SPEC", + "BriefDescription": "Operation speculatively executed, floating-point instruction" + } + { + "PublicDescription": "Operation speculatively executed, software change of the PC", + "EventCode": "0x76", + "EventName": "PC_WRITE_SPEC", + "BriefDescription": "Operation speculatively executed, software change of the PC" + } + { + "PublicDescription": "Operation speculatively executed, Cryptographic instruction", + "EventCode": "0x77", + "EventName": "CRYPTO_SPEC", + "BriefDescription": "Operation speculatively executed, Cryptographic instruction" + } + { + "PublicDescription": "Branch speculatively executed, immediate branch" + "EventCode": "0x78", + "EventName": "BR_IMMED_SPEC", + "BriefDescription": "Branch speculatively executed, immediate branch" + } + { + "PublicDescription": "Branch speculatively executed, procedure return" + "EventCode": "0x79", + "EventName": "BR_RETURN_SPEC", + "BriefDescription": "Branch speculatively executed, procedure return" + } + { + "PublicDescription": "Branch speculatively executed, indirect branch" + "EventCode": "0x7a", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed, indirect branch" + } + { + "PublicDescription": "Barrier speculatively executed, ISB" + "EventCode": "0x7c", + "EventName": "ISB_SPEC", + "BriefDescription": "Barrier speculatively executed, ISB" + } + { + "PublicDescription": "Barrier speculatively executed, DSB" + "EventCode": "0x7d", + "EventName": "DSB_SPEC", + "BriefDescription": "Barrier speculatively executed, DSB" + } + { + "PublicDescription": "Barrier speculatively executed, DMB" + "EventCode": "0x7e", + "EventName": "DMB_SPEC", + "BriefDescription": "Barrier speculatively executed, DMB" + } + { + "PublicDescription": "Exception taken, Other synchronous" + "EventCode": "0x81", + "EventName": "EXC_UNDEF", + "BriefDescription": "Exception taken, Other synchronous" + } + { + "PublicDescription": "Exception taken, Supervisor Call" + "EventCode": "0x82", + "EventName": "EXC_SVC", + "BriefDescription": "Exception taken, Supervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort" + "EventCode": "0x83", + "EventName": "EXC_PABORT", + "BriefDescription": "Exception taken, Instruction Abort" + } + { + "PublicDescription": "Exception taken, Data Abort and SError" + "EventCode": "0x84", + "EventName": "EXC_DABORT", + "BriefDescription": "Exception taken, Data Abort and SError" + } + { + "PublicDescription": "Exception taken, IRQ" + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + } + { + "PublicDescription": "Exception taken, FIQ" + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + } + { + "PublicDescription": "Exception taken, Secure Monitor Call" + "EventCode": "0x88", + "EventName": "EXC_SMC", + "BriefDescription": "Exception taken, Secure Monitor Call" + } + { + "PublicDescription": "Exception taken, Hypervisor Call" + "EventCode": "0x8a", + "EventName": "EXC_HVC", + "BriefDescription": "Exception taken, Hypervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "EventCode": "0x8b", + "EventName": "EXC_TRAP_PABORT", + "BriefDescription": "Exception taken, Instruction Abort not taken locally" + } + { + "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "EventCode": "0x8c", + "EventName": "EXC_TRAP_DABORT", + "BriefDescription": "Exception taken, Data Abort or SError not taken locally" + } + { + "PublicDescription": "Exception taken, Other traps not taken locally" + "EventCode": "0x8d", + "EventName": "EXC_TRAP_OTHER", + "BriefDescription": "Exception taken, Other traps not taken locally" + } + { + "PublicDescription": "Exception taken, IRQ not taken locally" + "EventCode": "0x8e", + "EventName": "EXC_TRAP_IRQ", + "BriefDescription": "Exception taken, IRQ not taken locally" + } + { + "PublicDescription": "Exception taken, FIQ not taken locally" + "EventCode": "0x8f", + "EventName": "EXC_TRAP_FIQ", + "BriefDescription": "Exception taken, FIQ not taken locally" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire" + "EventCode": "0x90", + "EventName": "RC_LD_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Store-Release" + "EventCode": "0x91", + "EventName": "RC_ST_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Store-Release" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, read" + "EventCode": "0xa0", + "EventName": "L3D_CACHE_RD", + "BriefDescription": "Attributable Level 3 data or unified cache access, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, write" + "EventCode": "0xa1", + "EventName": "L3D_CACHE_WR", + "BriefDescription": "Attributable Level 3 data or unified cache access, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, read" + "EventCode": "0xa2", + "EventName": "L3D_CACHE_REFILL_RD", + "BriefDescription": "Attributable Level 3 data or unified cache refill, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, write" + "EventCode": "0xa3", + "EventName": "L3D_CACHE_REFILL_WR", + "BriefDescription": "Attributable Level 3 data or unified cache refill, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + "EventCode": "0xa6", + "EventName": "L3D_CACHE_WB_VICTIM", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + "EventCode": "0xa7", + "EventName": "L3D_CACHE_WB_CLEAN", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate" + "EventCode": "0xa8", + "EventName": "L3D_CACHE_INVAL", + "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate" + } +] From patchwork Tue Mar 13 12:04:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131449 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp644252ljb; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) X-Google-Smtp-Source: AG47ELtngL4rw8d4HrO493B0kucJqnj3C7VsibeuDiK7VdBppFrwLFBwHohtUYDHyBmrQhx+Imy7 X-Received: by 10.98.89.85 with SMTP id n82mr346344pfb.233.1520942802806; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520942802; cv=none; d=google.com; s=arc-20160816; b=kPlSuRQV8ugizhi+2+DaBPlX27IJZXIhq4scPfgPpYeCVQCbesCQWuYL0h9YH16Gu6 Cs4oi/K9A3NGQjufW3m/q8aXjXUbqBy3hNx45X2Gsxl0dXm72FwpmktuhU6EJFxAatbK WxVbhhUlo0wmsY3B8YwGXvX3MBV8b2wubbvhLYSzkbZC9EvSHVf6aEMdCyiEO14zw0IW pjanDTfN1EliQ6MYnxieR3QW91EmVBShRAkKy6P6yibJbO2XkoyrFkWlW7VFEjsx5x1n DmWgZ9EBTTxYM2SXiiYdjgSBhQHO1a8cJwmHannL0q92JG5IergwnPBUkdlg9o+31GzS xzDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id u12si42663pgb.180.2018.03.13.05.06.42; Tue, 13 Mar 2018 05:06:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933388AbeCMMGj (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:55116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933158AbeCMMGf (ORCPT ); Tue, 13 Mar 2018 08:06:35 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 26950204EF; Tue, 13 Mar 2018 12:06:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 26950204EF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 19/31] perf vendor events arm64: Fixup ThunderX2 to use recommended events Date: Tue, 13 Mar 2018 09:04:56 -0300 Message-Id: <20180313120508.29327-20-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. Signed-off-by: John Garry Tested-by: Ganapatrao Kulkarni Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-10-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++----------------- 1 file changed, 10 insertions(+), 40 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c40ebc7..bc03c06c3918 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,32 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "L1D_CACHE_RD", }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "L1D_CACHE_WR", }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "L1D_CACHE_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "L1D_TLB_RD", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "L1D_TLB_WR", }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "BUS_ACCESS_RD", }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "BUS_ACCESS_WR", } ] From patchwork Tue Mar 13 12:04:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131455 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp649041ljb; Tue, 13 Mar 2018 05:10:34 -0700 (PDT) X-Google-Smtp-Source: AG47ELvcg0vmONJzfJS4j9hmoLhuTSA+fNozyY0X2CgzuQlplhvdLm6fb+0IVaR+ieAdMYsrVf2T X-Received: by 10.101.76.134 with SMTP id m6mr294520pgt.445.1520943034284; Tue, 13 Mar 2018 05:10:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520943034; cv=none; d=google.com; s=arc-20160816; b=CaZwXifbx/ebgO5xyi39oGgD0VlNSqT9Nj30Mm4hOdZh9P6kFTDG6zYPbKUjBrUXAb CnpPtCkiXwP69yphv42WgXYdOQCyzykvXtZowjWIhn5HdTO+0Yyspc1v9etr3NCTP5Ox 4vKG2USCSNhidT1r4Jyl2fTJZkPAjZgExM3LZS/KS1bMzyLyfKcHeyq8VcwCuBAjy+ia SNsMcFH3QJ+SiTaIUYMmc66qkHZcOUbhO7lhvjbP6u6sJfWFBiTtAJCCwXpnajZZUMfO NayuB+M+J6UTn6VnYGUJce46j1XbGLm4OV+yjyEl+QDtCoGZo+nF7zGAK/lCz9nkSUy0 iu5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=T629O/PvQgBqggrrl1g5cuwUTfmm0MMO0brffAeWlU4=; b=bHZ/iEhxDSoHiCuVkyNAOJ6YefXcEHYqNWtGTgCvHiQc0wCclAX3V6Zz+p7ELrZ6B+ 68exRk0BmAAi3HAM3sCrQPd36mR0gcPHxzcHdB/Sa7+bJPBZvHGFXIx8GIdLc6k2cPG6 uN5rYclNqjfSf+AqufqcEgTLXD0mlLaWz9s27JRBYOtlwI+1iLQiUMp5uJa1ZImYGq3y kfzOISd0lrWkiyDNdkEAfF/F1zdYpCVD+Bmkwb9echJ7EBVcU8SQE51Np8R3Ziby9X/r Fdlf+CcgarLLZLxBYFJyyH3LcUddyxXkVc/DtW97BSOZLGKfXkXs1K063UGyrJBFE3PY 3sfw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u16si45439pfl.299.2018.03.13.05.10.33; Tue, 13 Mar 2018 05:10:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933407AbeCMMGp (ORCPT + 28 others); Tue, 13 Mar 2018 08:06:45 -0400 Received: from mail.kernel.org ([198.145.29.99]:55184 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933387AbeCMMGj (ORCPT ); Tue, 13 Mar 2018 08:06:39 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 56CB521783; Tue, 13 Mar 2018 12:06:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 56CB521783 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 20/31] perf vendor events arm64: fixup A53 to use recommended events Date: Tue, 13 Mar 2018 09:04:57 -0300 Message-Id: <20180313120508.29327-21-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry This patch fixes the ARM Cortex-A53 json to use event definition from the ARMv8 recommended events. In addition to this change, other changes were made: - remove stray ',' - remove mirrored events in memory.json and bus.json - fixed indentation to be consistent with other ARM JSONs Signed-off-by: John Garry Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-11-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/arm/cortex-a53/branch.json | 14 +++---- .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++--------- .../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++---------- .../arch/arm64/arm/cortex-a53/memory.json | 14 +------ .../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------ .../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++----- 6 files changed, 62 insertions(+), 92 deletions(-) -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json index 3b6208763e50..0b0e6b26605b 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -1,25 +1,23 @@ [ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" + { + "ArchStdEvent": "BR_INDIRECT_SPEC", }, - {, + { "EventCode": "0xC9", "EventName": "BR_COND", "BriefDescription": "Conditional branch executed" }, - {, + { "EventCode": "0xCA", "EventName": "BR_INDIRECT_MISPRED", "BriefDescription": "Indirect branch mispredicted" }, - {, + { "EventCode": "0xCB", "EventName": "BR_INDIRECT_MISPRED_ADDR", "BriefDescription": "Indirect branch mispredicted because of address miscompare" }, - {, + { "EventCode": "0xCC", "EventName": "BR_COND_MISPRED", "BriefDescription": "Conditional branch mispredicted" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json index 480d9f7460ab..ce33b2553277 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -1,22 +1,8 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" + { + "ArchStdEvent": "BUS_ACCESS_RD", }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" + { + "ArchStdEvent": "BUS_ACCESS_WR", } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json index 11baad6344b9..5dfbec43c9f9 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -1,27 +1,27 @@ [ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" + { + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" + { + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" + { + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" + { + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" + { + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json index 480d9f7460ab..25ae642ba381 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -1,20 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, + { "EventCode": "0xC0", "EventName": "EXT_MEM_REQ", "BriefDescription": "External memory request" }, - {, + { "EventCode": "0xC1", "EventName": "EXT_MEM_REQ_NC", "BriefDescription": "Non-cacheable external memory request" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json index 73a22402d003..6cc6cbd7bf0b 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -1,32 +1,28 @@ [ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" + { + "ArchStdEvent": "EXC_IRQ", }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" + { + "ArchStdEvent": "EXC_FIQ", }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" + { + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + { + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + { + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" + { + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json index 3149fb90555a..f45a6b5d0025 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -1,50 +1,50 @@ [ - {, + { "EventCode": "0xC7", "EventName": "STALL_SB_FULL", "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" }, - {, + { "EventCode": "0xE0", "EventName": "OTHER_IQ_DEP_STALL", "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" }, - {, + { "EventCode": "0xE1", "EventName": "IC_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" }, - {, + { "EventCode": "0xE2", "EventName": "IUTLB_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" }, - {, + { "EventCode": "0xE3", "EventName": "DECODE_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" }, - {, + { "EventCode": "0xE4", "EventName": "OTHER_INTERLOCK_STALL", "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" }, - {, + { "EventCode": "0xE5", "EventName": "AGU_DEP_STALL", "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" }, - {, + { "EventCode": "0xE6", "EventName": "SIMD_DEP_STALL", "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." }, - {, + { "EventCode": "0xE7", "EventName": "LD_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" }, - {, + { "EventCode": "0xE8", "EventName": "ST_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" From patchwork Tue Mar 13 12:04:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaldo Carvalho de Melo X-Patchwork-Id: 131456 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp649158ljb; Tue, 13 Mar 2018 05:10:40 -0700 (PDT) X-Google-Smtp-Source: AG47ELshFuPK5M0PEujHGsBd1uaC3j2voeJ23TNm6HA2SgRWvigq4K5Jz2JvRk09GMWGcEVVcvDQ X-Received: by 10.99.37.7 with SMTP id l7mr337604pgl.212.1520943040200; Tue, 13 Mar 2018 05:10:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520943040; cv=none; d=google.com; s=arc-20160816; b=rbpQrc9HgZMUBMOTmG+/giwpZw7TumL0fpSNKAYbIN4Lr5aBK6nBSa+hWic+VsUh7p vBZ+3sWeOU+Jdk1dI7Kvb4c/tNSasm3MoEkkQA7xcR1VAwwnp0oCj/JZY43/yM8R7Vlz /OTUd4zujOxG43e4A94YBUmFpub9lavvWzVAo8umssqReZHVxVrS4K6YHurB8tG2Yv5n 198V++bBWFyFd4iD493ftc0MZfZ/5S7Ba9EiZ0HzQwYO378kR6jKRaZTwTHJLIuDuIRS kz/Z2eho66eQ5O1TMqe87h1bu1qtWxAIfaMjqcRkTmez3LStX+gyt1iCMVZ4/UaCrX1G lpiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:arc-authentication-results; bh=Xe/+w+iY1a4d1tfBLUo5NAA0uGlyar/B9g4+yu7FqmA=; b=IV75CAlb5DMUC1SLRyz+ctGEq63akwoY7c2iU8N4Pd7b1m67TC/o7/BwTU9+yMEoH2 8N9RXlu1bRS1YaCX4y4GYmgJo/20mqzkRaNiHDSEGy6DZg3qbwn0aw51GEbdjeqxhNQV RFQ36/9bjcL82FrhBwZIqdgNt8IRxMqDPP1f6TCG0RirHqGTPUuBlbEdSH9VwrK7OhnN nuRgNdmUhDJM/8tXeYRfYVBNnq/SVbkxxF9DRTOyBpnlI0dE+gJsyZVpo5dEbrCbVwtN NI87mgJYvXOljTGhWkXcOto6B1hN4dE4rCk2GxY53ITY3F9ww26wMDHcMU4c/7P+8P++ q4vA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k186si51017pgc.15.2018.03.13.05.10.39; Tue, 13 Mar 2018 05:10:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933506AbeCMMKh (ORCPT + 28 others); Tue, 13 Mar 2018 08:10:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:55246 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933395AbeCMMGo (ORCPT ); Tue, 13 Mar 2018 08:06:44 -0400 Received: from jouet.infradead.org (unknown [177.79.83.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C1D7321796; Tue, 13 Mar 2018 12:06:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C1D7321796 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=acme@kernel.org From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Alexander Shishkin , Andi Kleen , Ganapatrao Kulkarni , Jiri Olsa , Namhyung Kim , Peter Zijlstra , Shaokun Zhang , Will Deacon , William Cohen , linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, Arnaldo Carvalho de Melo Subject: [PATCH 21/31] perf vendor events arm64: add HiSilicon hip08 JSON file Date: Tue, 13 Mar 2018 09:04:58 -0300 Message-Id: <20180313120508.29327-22-acme@kernel.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180313120508.29327-1-acme@kernel.org> References: <20180313120508.29327-1-acme@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: John Garry This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: John Garry Cc: Alexander Shishkin Cc: Andi Kleen Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Shaokun Zhang Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-12-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 123 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json -- 2.14.3 diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 000000000000..9f0f15d15f75 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,122 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_RD", + }, + { + "ArchStdEvent": "L1D_TLB_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index cf14e23b6404..8f11aeb003a9 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,3 +14,4 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core