| Message ID | 20231117071704.35040-3-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/stm32xxx: Report error when incorrect CPU is used | expand |
On 11/17/23 17:17, Philippe Mathieu-Daudé wrote: > Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the > CPU type requested by the command line. This might confuse users, > since the following will create a machine with a Cortex-M4 CPU: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > > Set the MachineClass::valid_cpu_types field (introduced in commit > c9cf636d48 "machine: Add a valid_cpu_types property"). > Remove the now unused MachineClass::default_cpu_type field. > > We now get: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu > The valid types are: cortex-m4-arm-cpu > > Since the SoC family can only use Cortex-M4 CPUs, hard-code the > CPU type name at the SoC level, removing the QOM property > entirely. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/hw/arm/stm32f405_soc.h | 4 ---- > hw/arm/netduinoplus2.c | 7 ++++++- > hw/arm/olimex-stm32-h405.c | 8 ++++++-- > hw/arm/stm32f405_soc.c | 8 +------- > 4 files changed, 13 insertions(+), 14 deletions(-) > Reviewed-by: Gavin Shan <gshan@redhat.com>
On Fri, 17 Nov 2023 08:17:02 +0100 Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the > CPU type requested by the command line. This might confuse users, > since the following will create a machine with a Cortex-M4 CPU: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > > Set the MachineClass::valid_cpu_types field (introduced in commit > c9cf636d48 "machine: Add a valid_cpu_types property"). > Remove the now unused MachineClass::default_cpu_type field. Why default_cpu_type is removed? what if user didn't user -cpu at all? > > We now get: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu > The valid types are: cortex-m4-arm-cpu > > Since the SoC family can only use Cortex-M4 CPUs, hard-code the > CPU type name at the SoC level, removing the QOM property > entirely. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/hw/arm/stm32f405_soc.h | 4 ---- > hw/arm/netduinoplus2.c | 7 ++++++- > hw/arm/olimex-stm32-h405.c | 8 ++++++-- > hw/arm/stm32f405_soc.c | 8 +------- > 4 files changed, 13 insertions(+), 14 deletions(-) > > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > index c968ce3ab2..d15c03c4b5 100644 > --- a/include/hw/arm/stm32f405_soc.h > +++ b/include/hw/arm/stm32f405_soc.h > @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) > #define CCM_SIZE (64 * 1024) > > struct STM32F405State { > - /*< private >*/ > SysBusDevice parent_obj; > - /*< public >*/ > - > - char *cpu_type; > > ARMv7MState armv7m; > > diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c > index 515c081605..2e58984947 100644 > --- a/hw/arm/netduinoplus2.c > +++ b/hw/arm/netduinoplus2.c > @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) > clock_set_hz(sysclk, SYSCLK_FRQ); > > dev = qdev_new(TYPE_STM32F405_SOC); > - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_connect_clock_in(dev, "sysclk", sysclk); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > > @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) > > static void netduinoplus2_machine_init(MachineClass *mc) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-m4"), > + NULL > + }; > + > mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; > mc->init = netduinoplus2_init; > + mc->valid_cpu_types = valid_cpu_types; > } > > DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) > diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c > index 3aa61c91b7..d793de7c97 100644 > --- a/hw/arm/olimex-stm32-h405.c > +++ b/hw/arm/olimex-stm32-h405.c > @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) > clock_set_hz(sysclk, SYSCLK_FRQ); > > dev = qdev_new(TYPE_STM32F405_SOC); > - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_connect_clock_in(dev, "sysclk", sysclk); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > > @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) > > static void olimex_stm32_h405_machine_init(MachineClass *mc) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-m4"), > + NULL > + }; > + > mc->desc = "Olimex STM32-H405 (Cortex-M4)"; > mc->init = olimex_stm32_h405_init; > - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); > + mc->valid_cpu_types = valid_cpu_types; > > /* SRAM pre-allocated as part of the SoC instantiation */ > mc->default_ram_size = 0; > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > index cef23d7ee4..a65bbe298d 100644 > --- a/hw/arm/stm32f405_soc.c > +++ b/hw/arm/stm32f405_soc.c > @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > > armv7m = DEVICE(&s->armv7m); > qdev_prop_set_uint32(armv7m, "num-irq", 96); > - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_prop_set_bit(armv7m, "enable-bitband", true); > qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); > qdev_connect_clock_in(armv7m, "refclk", s->refclk); > @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > create_unimplemented_device("RNG", 0x50060800, 0x400); > } > > -static Property stm32f405_soc_properties[] = { > - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > > dc->realize = stm32f405_soc_realize; > - device_class_set_props(dc, stm32f405_soc_properties); > /* No vmstate or reset required: device has no internal state */ > } >
Hi Igor, On 24/11/23 14:13, Igor Mammedov wrote: > On Fri, 17 Nov 2023 08:17:02 +0100 > Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > >> Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the >> CPU type requested by the command line. This might confuse users, >> since the following will create a machine with a Cortex-M4 CPU: >> >> $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f >> >> Set the MachineClass::valid_cpu_types field (introduced in commit >> c9cf636d48 "machine: Add a valid_cpu_types property"). >> Remove the now unused MachineClass::default_cpu_type field. > > Why default_cpu_type is removed? "Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level" > what if user didn't user -cpu at all? The CPU is hardcoded, default value is not used. qemu-system-arm -M olimex-stm32-h405 -S -monitor stdio QEMU 8.1.91 monitor - type 'help' for more information (qemu) info qtree ... dev: armv7m, id "" gpio-in "NMI" 1 gpio-out "SYSRESETREQ" 1 gpio-in "" 96 clock-in "cpuclk" freq_hz=168 MHz clock-in "refclk" freq_hz=21 MHz cpu-type = "cortex-m4-arm-cpu" ... > >> >> We now get: >> >> $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f >> qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu >> The valid types are: cortex-m4-arm-cpu >> >> Since the SoC family can only use Cortex-M4 CPUs, hard-code the >> CPU type name at the SoC level, removing the QOM property >> entirely. >> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> include/hw/arm/stm32f405_soc.h | 4 ---- >> hw/arm/netduinoplus2.c | 7 ++++++- >> hw/arm/olimex-stm32-h405.c | 8 ++++++-- >> hw/arm/stm32f405_soc.c | 8 +------- >> 4 files changed, 13 insertions(+), 14 deletions(-)
On Fri, Nov 17, 2023 at 5:18 PM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the > CPU type requested by the command line. This might confuse users, > since the following will create a machine with a Cortex-M4 CPU: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > > Set the MachineClass::valid_cpu_types field (introduced in commit > c9cf636d48 "machine: Add a valid_cpu_types property"). > Remove the now unused MachineClass::default_cpu_type field. > > We now get: > > $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f > qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu > The valid types are: cortex-m4-arm-cpu > > Since the SoC family can only use Cortex-M4 CPUs, hard-code the > CPU type name at the SoC level, removing the QOM property > entirely. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > include/hw/arm/stm32f405_soc.h | 4 ---- > hw/arm/netduinoplus2.c | 7 ++++++- > hw/arm/olimex-stm32-h405.c | 8 ++++++-- > hw/arm/stm32f405_soc.c | 8 +------- > 4 files changed, 13 insertions(+), 14 deletions(-) > > diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h > index c968ce3ab2..d15c03c4b5 100644 > --- a/include/hw/arm/stm32f405_soc.h > +++ b/include/hw/arm/stm32f405_soc.h > @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) > #define CCM_SIZE (64 * 1024) > > struct STM32F405State { > - /*< private >*/ > SysBusDevice parent_obj; > - /*< public >*/ > - > - char *cpu_type; > > ARMv7MState armv7m; > > diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c > index 515c081605..2e58984947 100644 > --- a/hw/arm/netduinoplus2.c > +++ b/hw/arm/netduinoplus2.c > @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) > clock_set_hz(sysclk, SYSCLK_FRQ); > > dev = qdev_new(TYPE_STM32F405_SOC); > - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_connect_clock_in(dev, "sysclk", sysclk); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > > @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) > > static void netduinoplus2_machine_init(MachineClass *mc) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-m4"), > + NULL > + }; > + > mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; > mc->init = netduinoplus2_init; > + mc->valid_cpu_types = valid_cpu_types; > } > > DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) > diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c > index 3aa61c91b7..d793de7c97 100644 > --- a/hw/arm/olimex-stm32-h405.c > +++ b/hw/arm/olimex-stm32-h405.c > @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) > clock_set_hz(sysclk, SYSCLK_FRQ); > > dev = qdev_new(TYPE_STM32F405_SOC); > - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_connect_clock_in(dev, "sysclk", sysclk); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > > @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) > > static void olimex_stm32_h405_machine_init(MachineClass *mc) > { > + static const char * const valid_cpu_types[] = { > + ARM_CPU_TYPE_NAME("cortex-m4"), > + NULL > + }; > + > mc->desc = "Olimex STM32-H405 (Cortex-M4)"; > mc->init = olimex_stm32_h405_init; > - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); > + mc->valid_cpu_types = valid_cpu_types; > > /* SRAM pre-allocated as part of the SoC instantiation */ > mc->default_ram_size = 0; > diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c > index cef23d7ee4..a65bbe298d 100644 > --- a/hw/arm/stm32f405_soc.c > +++ b/hw/arm/stm32f405_soc.c > @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > > armv7m = DEVICE(&s->armv7m); > qdev_prop_set_uint32(armv7m, "num-irq", 96); > - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); > qdev_prop_set_bit(armv7m, "enable-bitband", true); > qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); > qdev_connect_clock_in(armv7m, "refclk", s->refclk); > @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) > create_unimplemented_device("RNG", 0x50060800, 0x400); > } > > -static Property stm32f405_soc_properties[] = { > - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void stm32f405_soc_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > > dc->realize = stm32f405_soc_realize; > - device_class_set_props(dc, stm32f405_soc_properties); > /* No vmstate or reset required: device has no internal state */ > } > > -- > 2.41.0 > >
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab2..d15c03c4b5 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c081605..2e58984947 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; + mc->valid_cpu_types = valid_cpu_types; } DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b7..d793de7c97 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Olimex STM32-H405 (Cortex-M4)"; mc->init = olimex_stm32_h405_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types = valid_cpu_types; /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size = 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee4..a65bbe298d 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } -static Property stm32f405_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ }