Message ID | 20230330204217.47666-7-prabhakar.mahadev-lad.rj@bp.renesas.com |
---|---|
State | Superseded |
Headers | show |
Series | RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP | expand |
On Fri, Mar 31, 2023 at 9:37 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Thu, Mar 30, 2023 at 10:42 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Explicitly select the required Cache management and Errata configs > > required for the RZ/Five SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index de31589ed054..67604f24973e 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,10 @@ if RISCV config ARCH_R9A07G043 bool "RISC-V Platform support for RZ/Five" select ARCH_RZG2L + select AX45MP_L2_CACHE + select DMA_GLOBAL_POOL + select ERRATA_ANDES + select ERRATA_ANDES_CMO help This enables support for the Renesas RZ/Five SoC.