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RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP
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| 3 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v7,5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP
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-
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2023-03-30
Lad, Prabhakar
New
[v7,3/6] riscv: errata: Add Andes alternative ports
RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP
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-
-
2023-03-30
Lad, Prabhakar
New
[v7,1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP
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-
-
2023-03-30
Lad, Prabhakar
New