diff mbox series

[2/2] usb: dwc3: Set cache type to 'snoop' for freescale layerscape chip

Message ID 20240703-dwc-v1-2-9cbc93d49180@nxp.com
State New
Headers show
Series usb: dwc3: Add cache type configuration support for freescale layerscape | expand

Commit Message

Frank Li July 3, 2024, 11:06 p.m. UTC 
From: Ran Wang <ran.wang_1@nxp.com>

dwc3 have 4 different transfer types: Data Read, Desc Read, Data Write and
Desc write. For each transfer type, controller has a 4-bit register field
to enable different cache type.

Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
----------------------------------------------------------------
MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
----------------------------------------------------------------
AHB      |Cacheable     |Bufferable   |Privilegge |Data
AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
----------------------------------------------------------------
Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
signals, which have the same meaning:
  Bufferable = Posted
  Cacheable = Modifiable = Snoop (negation of No Snoop)

In most cases, driver work well with default value. But USB device detect
failure sometime on Layerscape platforms if bit[1] not set and enable
dma-coherent.

Set bit[1] "Snoop" for Data Read, Desc Read, Data Write and Desc write if
compatible string contain fsl,ls-dwc3.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/usb/dwc3/core.c | 12 ++++++++++++
 drivers/usb/dwc3/core.h |  4 ++++
 2 files changed, 16 insertions(+)
diff mbox series

Patch

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index cb82557678ddd..2b474de83b783 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1061,6 +1061,18 @@  static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 
 	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 
+	if (of_device_is_compatible(dev->of_node, "fsl,ls-dwc3")) {
+
+		cfg &= ~(DWC3_GSBUSCFG0_DATARD | DWC3_GSBUSCFG0_DESCRD |
+			 DWC3_GSBUSCFG0_DATAWR | DWC3_GSBUSCFG0_DESCWR);
+		cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DATARD, 2) |
+		       FIELD_PREP(DWC3_GSBUSCFG0_DESCRD, 2) |
+		       FIELD_PREP(DWC3_GSBUSCFG0_DATAWR, 2) |
+		       FIELD_PREP(DWC3_GSBUSCFG0_DESCWR, 2);
+
+		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+	}
+
 	/*
 	 * Handle property "snps,incr-burst-type-adjustment".
 	 * Get the number of value from this property:
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 3781c736c1a17..99edfabd89673 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -184,6 +184,10 @@ 
 /* Bit fields */
 
 /* Global SoC Bus Configuration INCRx Register 0 */
+#define DWC3_GSBUSCFG0_DATARD		GENMASK(31, 28)
+#define DWC3_GSBUSCFG0_DESCRD		GENMASK(27, 24)
+#define DWC3_GSBUSCFG0_DATAWR		GENMASK(23, 20)
+#define DWC3_GSBUSCFG0_DESCWR		GENMASK(19, 16)
 #define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
 #define DWC3_GSBUSCFG0_INCR128BRSTENA	(1 << 6) /* INCR128 burst */
 #define DWC3_GSBUSCFG0_INCR64BRSTENA	(1 << 5) /* INCR64 burst */