Show patches with: State = Action Required       |   23741 patches
« 1 2 3 4 … 237 238 »
Patch Series S/W/F Date Submitter Delegate State
[v8,6/6] hw/ssi/xilinx_spi: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[v8,5/6] hw/char/xilinx_uartlite: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[v8,4/6] hw/timer/xilinx_timer: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[v8,3/6] hw/net/xilinx_ethlite: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[v8,2/6] hw/intc/xilinx_intc: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[v8,1/6] hw/qdev-properties-system: Introduce EndianMode QAPI enum hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-13 Philippe Mathieu-Daudé New
[9/9] target/microblaze: Simplify compute_ldst_addr_type{a,b} target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[8/9] target/microblaze: Drop DisasContext.r0 target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[7/9] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[6/9] target/microblaze: Fix printf format in mmu_translate target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[5/9] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[4/9] target/microblaze: Use uint64_t for CPUMBState.ear target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[3/9] target/microblaze: Implement extended address load/store out of line target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[2/9] target/microblaze: Split out mb_transaction_failed_internal target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[1/9] target/microblaze: Split out mb_unaligned_access_internal target/microblaze: Always use TARGET_LONG_BITS == 32 --- 2025-02-12 Richard Henderson New
[v3,19/19] qom: Require TypeInfo::class_data points to const data qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,18/19] hw: Constify various TypeInfo and associated structures qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,17/19] hw/virtio/virtio-pci: Reduce generic_type_info scope qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,16/19] hw/virtio/virtio-pci: Constify generic_type_info qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,15/19] hw/virtio/virtio-pci: Constify base_type_info qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,14/19] hw/virtio/virtio-pci: Do not access base_type_info.name directly qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,13/19] hw/virtio/virtio-pci: Assert before registering QOM types qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,12/19] hw/virtio/virtio-pci: Always allocate QOM type base_name qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,11/19] qom: Constify InterfaceInfo[] interfaces qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,10/19] qom: Constify TypeInfo::class_data qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,09/19] qom: Have class_init() take a const data argument qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,08/19] qom: Have class_base_init() take a const data argument qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,07/19] target/riscv: Convert misa_mxl_max using GLib macros qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,06/19] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,05/19] target/xtensa: Finalize config in xtensa_register_core() qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,04/19] target/sparc: Constify SPARCCPUClass::cpu_def qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,03/19] target/i386: Constify X86CPUModel uses qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,02/19] hw: Make class data 'const' qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[v3,01/19] hw: Declare various const data as 'const' qom: Constify class_data --- 2025-02-12 Philippe Mathieu-Daudé New
[PULL,00/29] Misc HW patches for 2025-02-12 --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,7/8] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,6/8] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,3/8] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v2,1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore --- 2025-02-12 Philippe Mathieu-Daudé New
[v7,10/10] tests/functional: Have microblaze tests inherit common parent class hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[v7,09/10] tests/functional: Remove sleep() kludges from microblaze tests hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[v7,08/10] tests/functional: Allow microblaze tests to take a machine name argument hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[v7,07/10] tests/functional: Explicit endianness of microblaze assets hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[5/5] target/i386: Mark WHPX APIC region as little-endian hw: More DEVICE_ [NATIVE -> LITTLE] _ENDIAN conversions --- 2025-02-12 Philippe Mathieu-Daudé New
[4/5] hw/pci-host: Mark versatile regions as little-endian hw: More DEVICE_ [NATIVE -> LITTLE] _ENDIAN conversions --- 2025-02-12 Philippe Mathieu-Daudé New
[3/5] hw/mips: Mark Loonson3 Virt machine devices as little-endian hw: More DEVICE_ [NATIVE -> LITTLE] _ENDIAN conversions --- 2025-02-12 Philippe Mathieu-Daudé New
[2/5] hw/mips: Mark Boston machine devices as little-endian hw: More DEVICE_ [NATIVE -> LITTLE] _ENDIAN conversions --- 2025-02-12 Philippe Mathieu-Daudé New
[1/5] hw/arm: Mark Allwinner Technology devices as little-endian hw: More DEVICE_ [NATIVE -> LITTLE] _ENDIAN conversions --- 2025-02-12 Philippe Mathieu-Daudé New
meson: Display summary of Darwin libraries detected meson: Display summary of Darwin libraries detected --- 2025-02-12 Philippe Mathieu-Daudé New
[v6,07/11] tests/functional: Avoid using www.qemu-advent-calendar.org URL hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[v6,03/11] hw/net/xilinx_ethlite: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs --- 2025-02-12 Philippe Mathieu-Daudé New
[6/6] tcg/sparc64: Use 'z' constraint tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
[5/6] tcg/riscv: Use 'z' constraint tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
[4/6] tcg/mips: Use 'z' constraint tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
[3/6] tcg/loongarch64: Use 'z' constraint tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
[2/6] tcg/aarch64: Use 'z' constraint tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
[1/6] tcg: Introduce the 'z' constraint for a hardware zero register tcg: Introduce constraint for zero register --- 2025-02-12 Richard Henderson New
target/alpha: Do not mix exception flags and FPCR bits target/alpha: Do not mix exception flags and FPCR bits --- 2025-02-11 Philippe Mathieu-Daudé New
[PULL,64/68] target/arm: Remove fp_status_a32 [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,63/68] target/arm: Remove fp_status_a64 [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,62/68] target/arm: Remove fp_status_f16_a32 [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,60/68] target/arm: Remove ah_fp_status [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,59/68] target/arm: Remove ah_fp_status_f16 [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,38/68] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,36/68] target/arm: Handle FPCR.AH in negation steps in SVE FCADD [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,31/68] target/arm: Implement FPCR.AH handling for scalar FABS and FABD [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,27/68] target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,23/68] target/arm: Implement FPCR.AH semantics for scalar FMIN/FMAX [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,14/68] target/arm: Add FPCR.NEP to TBFLAGS [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,10/68] target/arm: Set up float_status to use for FPCR.AH=1 behaviour [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,09/68] target/arm: Add FPCR.AH to tbflags [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,07/68] target/arm: Adjust FP behaviour for FPCR.AH = 1 [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,04/68] fpu: allow flushing of output denormals to be after rounding [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,03/68] fpu: Implement float_flag_input_denormal_used [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,02/68] fpu: Add float_class_denormal [PULL,01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags --- 2025-02-11 Peter Maydell New
[PULL,00/68] target-arm queue --- 2025-02-11 Peter Maydell New
[v3,10/10] disas: Remove target_words_bigendian() call in initialize_debug_target() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,09/10] target/xtensa: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,08/10] target/sh4: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,07/10] target/riscv: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,06/10] target/ppc: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,05/10] target/mips: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,04/10] target/microblaze: Set disassemble_info::endian value in disas_set_info disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,03/10] target/arm: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,02/10] target: Set disassemble_info::endian value for big-endian targets disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v3,01/10] target: Set disassemble_info::endian value for little-endian targets disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v2,10/10] disas: Remove target_words_bigendian() call in initialize_debug_target() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v2,09/10] target/xtensa: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v2,08/10] target/sh4: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v2,05/10] target/mips: Set disassemble_info::endian value in disas_set_info() disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[v2,01/10] target: Set disassemble_info::endian value for little-endian targets disas: Have CPUClass::disas_set_info() callback set the endianness --- 2025-02-10 Philippe Mathieu-Daudé New
[PULL,32/32] hw/net/smc91c111: Ignore attempt to pop from empty RX fifo [PULL,01/32] backends/tpm: Use qemu_hexdump_line() to avoid sprintf() --- 2025-02-10 Philippe Mathieu-Daudé New
[PULL,31/32] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header [PULL,01/32] backends/tpm: Use qemu_hexdump_line() to avoid sprintf() --- 2025-02-10 Philippe Mathieu-Daudé New
[PULL,26/32] hw/boards: Ensure machine setting auto_create_sdcard expose a SD Bus [PULL,01/32] backends/tpm: Use qemu_hexdump_line() to avoid sprintf() --- 2025-02-10 Philippe Mathieu-Daudé New
[PULL,25/32] hw/riscv: Remove all invalid uses of auto_create_sdcard=true [PULL,01/32] backends/tpm: Use qemu_hexdump_line() to avoid sprintf() --- 2025-02-10 Philippe Mathieu-Daudé New
[PULL,24/32] hw/arm: Remove all invalid uses of auto_create_sdcard=true [PULL,01/32] backends/tpm: Use qemu_hexdump_line() to avoid sprintf() --- 2025-02-10 Philippe Mathieu-Daudé New
« 1 2 3 4 … 237 238 »