Toggle navigation
Patchwork
qemu-devel
Patches
Bundles
About this project
Login
Register
Mail settings
Show patches with
: Series =
target/arm: decode generator and initial sve patches
| State =
Action Required
| Archived =
No
| 21 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Search
Archived
No
Yes
Both
Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
Apply
Patch
Series
S/W/F
Date
Submitter
Delegate
State
[23/23] target/arm: Implement SVE Element Count Group, register destinations
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[22/23] target/arm: Implement SVE floating-point trig select coefficient
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[21/23] target/arm: Implement SVE floating-point exponential accelerator
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[20/23] target/arm: Implement SVE Compute Vector Address Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[19/23] target/arm: Implement SVE Bitwise Shift - Unpredicated Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[18/23] target/arm: Implement SVE Stack Allocation Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[16/23] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[15/23] target/arm: Implement SVE Integer Multiply-Add Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[13/23] target/arm: Implement SVE bitwise shift by wide elements (predicated)
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[12/23] target/arm: Implement SVE bitwise shift by vector (predicated)
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[11/23] target/arm: Implement SVE bitwise shift by immediate (predicated)
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[10/23] target/arm: Implement SVE Integer Reduction Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[09/23] target/arm: Handle SVE registers when using clear_vec_high
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[08/23] target/arm: Handle SVE registers in write_fp_dreg
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[07/23] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[06/23] target/arm: Implement SVE load vector/predicate
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[05/23] target/arm: Implement SVE predicate logical operations
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[04/23] target/arm: Implement PTRUE, PFALSE, SETFFR
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[03/23] target/arm: Implement SVE Bitwise Logical - Unpredicated Group
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[02/23] target/arm: Add SVE decode skeleton
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New
[01/23] scripts: Add decodetree.py
target/arm: decode generator and initial sve patches
-
-
-
2017-12-18
Richard Henderson
New